1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/CodeGen/RuntimeLibcalls.h"
27 #include "llvm/ADT/APFloat.h"
28 #include "llvm/ADT/STLExtras.h"
37 class TargetRegisterClass;
41 class MachineBasicBlock;
45 //===----------------------------------------------------------------------===//
46 /// TargetLowering - This class defines information used to lower LLVM code to
47 /// legal SelectionDAG operators that the target instruction selector can accept
50 /// This class also defines callbacks that targets must implement to lower
51 /// target-specific constructs to SelectionDAG operators.
53 class TargetLowering {
55 /// LegalizeAction - This enum indicates whether operations are valid for a
56 /// target, and if not, what action should be used to make them valid.
58 Legal, // The target natively supports this operation.
59 Promote, // This operation should be executed in a larger type.
60 Expand, // Try to expand this to other ops, otherwise use a libcall.
61 Custom // Use the LowerOperation hook to implement custom lowering.
64 enum OutOfRangeShiftAmount {
65 Undefined, // Oversized shift amounts are undefined (default).
66 Mask, // Shift amounts are auto masked (anded) to value size.
67 Extend // Oversized shift pulls in zeros or sign bits.
70 enum SetCCResultValue {
71 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend.
72 ZeroOrOneSetCCResult, // SetCC returns a zero extended result.
73 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result.
76 enum SchedPreference {
77 SchedulingForLatency, // Scheduling for shortest total latency.
78 SchedulingForRegPressure // Scheduling for lowest register pressure.
81 explicit TargetLowering(TargetMachine &TM);
82 virtual ~TargetLowering();
84 TargetMachine &getTargetMachine() const { return TM; }
85 const TargetData *getTargetData() const { return TD; }
87 bool isLittleEndian() const { return IsLittleEndian; }
88 MVT::ValueType getPointerTy() const { return PointerTy; }
89 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
90 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
92 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
94 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
96 /// isSelectExpensive - Return true if the select operation is expensive for
98 bool isSelectExpensive() const { return SelectIsExpensive; }
100 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
101 /// a sequence of several shifts, adds, and multiplies for this target.
102 bool isIntDivCheap() const { return IntDivIsCheap; }
104 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
106 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
108 /// getSetCCResultTy - Return the ValueType of the result of setcc operations.
110 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; }
112 /// getSetCCResultContents - For targets without boolean registers, this flag
113 /// returns information about the contents of the high-bits in the setcc
115 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;}
117 /// getSchedulingPreference - Return target scheduling preference.
118 SchedPreference getSchedulingPreference() const {
119 return SchedPreferenceInfo;
122 /// getRegClassFor - Return the register class that should be used for the
123 /// specified value type. This may only be called on legal types.
124 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const {
125 assert(!MVT::isExtendedVT(VT));
126 TargetRegisterClass *RC = RegClassForVT[VT];
127 assert(RC && "This value type is not natively supported!");
131 /// isTypeLegal - Return true if the target has native support for the
132 /// specified value type. This means that it has a register that directly
133 /// holds it without promotions or expansions.
134 bool isTypeLegal(MVT::ValueType VT) const {
135 return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0;
138 class ValueTypeActionImpl {
139 /// ValueTypeActions - This is a bitvector that contains two bits for each
140 /// value type, where the two bits correspond to the LegalizeAction enum.
141 /// This can be queried with "getTypeAction(VT)".
142 uint32_t ValueTypeActions[2];
144 ValueTypeActionImpl() {
145 ValueTypeActions[0] = ValueTypeActions[1] = 0;
147 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
148 ValueTypeActions[0] = RHS.ValueTypeActions[0];
149 ValueTypeActions[1] = RHS.ValueTypeActions[1];
152 LegalizeAction getTypeAction(MVT::ValueType VT) const {
153 if (MVT::isExtendedVT(VT)) {
154 if (MVT::isVector(VT)) return Expand;
155 if (MVT::isInteger(VT))
156 // First promote to a power-of-two size, then expand if necessary.
157 return VT == MVT::RoundIntegerType(VT) ? Expand : Promote;
158 assert(0 && "Unsupported extended type!");
160 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3);
162 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) {
163 assert(!MVT::isExtendedVT(VT));
164 assert(unsigned(VT >> 4) < array_lengthof(ValueTypeActions));
165 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31);
169 const ValueTypeActionImpl &getValueTypeActions() const {
170 return ValueTypeActions;
173 /// getTypeAction - Return how we should legalize values of this type, either
174 /// it is already legal (return 'Legal') or we need to promote it to a larger
175 /// type (return 'Promote'), or we need to expand it into multiple registers
176 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
177 LegalizeAction getTypeAction(MVT::ValueType VT) const {
178 return ValueTypeActions.getTypeAction(VT);
181 /// getTypeToTransformTo - For types supported by the target, this is an
182 /// identity function. For types that must be promoted to larger types, this
183 /// returns the larger type to promote to. For integer types that are larger
184 /// than the largest integer register, this contains one step in the expansion
185 /// to get to the smaller register. For illegal floating point types, this
186 /// returns the integer type to transform to.
187 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
188 if (!MVT::isExtendedVT(VT)) {
189 MVT::ValueType NVT = TransformToType[VT];
190 assert(getTypeAction(NVT) != Promote &&
191 "Promote may not follow Expand or Promote");
195 if (MVT::isVector(VT))
196 return MVT::getVectorType(MVT::getVectorElementType(VT),
197 MVT::getVectorNumElements(VT) / 2);
198 if (MVT::isInteger(VT)) {
199 MVT::ValueType NVT = MVT::RoundIntegerType(VT);
201 // Size is a power of two - expand to half the size.
202 return MVT::getIntegerType(MVT::getSizeInBits(VT) / 2);
204 // Promote to a power of two size, avoiding multi-step promotion.
205 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
207 assert(0 && "Unsupported extended type!");
210 /// getTypeToExpandTo - For types supported by the target, this is an
211 /// identity function. For types that must be expanded (i.e. integer types
212 /// that are larger than the largest integer register or illegal floating
213 /// point types), this returns the largest legal type it will be expanded to.
214 MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const {
215 assert(!MVT::isVector(VT));
217 switch (getTypeAction(VT)) {
221 VT = getTypeToTransformTo(VT);
224 assert(false && "Type is not legal nor is it to be expanded!");
231 /// getVectorTypeBreakdown - Vector types are broken down into some number of
232 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
233 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
234 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
236 /// This method returns the number of registers needed, and the VT for each
237 /// register. It also returns the VT and quantity of the intermediate values
238 /// before they are promoted/expanded.
240 unsigned getVectorTypeBreakdown(MVT::ValueType VT,
241 MVT::ValueType &IntermediateVT,
242 unsigned &NumIntermediates,
243 MVT::ValueType &RegisterVT) const;
245 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator;
246 legal_fpimm_iterator legal_fpimm_begin() const {
247 return LegalFPImmediates.begin();
249 legal_fpimm_iterator legal_fpimm_end() const {
250 return LegalFPImmediates.end();
253 /// isShuffleMaskLegal - Targets can use this to indicate that they only
254 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
255 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
256 /// are assumed to be legal.
257 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
261 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
262 /// used by Targets can use this to indicate if there is a suitable
263 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
265 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
267 SelectionDAG &DAG) const {
271 /// getOperationAction - Return how this operation should be treated: either
272 /// it is legal, needs to be promoted to a larger size, needs to be
273 /// expanded to some other code sequence, or the target has a custom expander
275 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
276 if (MVT::isExtendedVT(VT)) return Expand;
277 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
280 /// isOperationLegal - Return true if the specified operation is legal on this
282 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
283 return getOperationAction(Op, VT) == Legal ||
284 getOperationAction(Op, VT) == Custom;
287 /// getLoadXAction - Return how this load with extension should be treated:
288 /// either it is legal, needs to be promoted to a larger size, needs to be
289 /// expanded to some other code sequence, or the target has a custom expander
291 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const {
292 if (MVT::isExtendedVT(VT)) return getTypeAction(VT);
293 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3);
296 /// isLoadXLegal - Return true if the specified load with extension is legal
298 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const {
299 return getLoadXAction(LType, VT) == Legal ||
300 getLoadXAction(LType, VT) == Custom;
303 /// getStoreXAction - Return how this store with truncation should be treated:
304 /// either it is legal, needs to be promoted to a larger size, needs to be
305 /// expanded to some other code sequence, or the target has a custom expander
307 LegalizeAction getStoreXAction(MVT::ValueType VT) const {
308 if (MVT::isExtendedVT(VT)) return getTypeAction(VT);
309 return (LegalizeAction)((StoreXActions >> (2*VT)) & 3);
312 /// isStoreXLegal - Return true if the specified store with truncation is
313 /// legal on this target.
314 bool isStoreXLegal(MVT::ValueType VT) const {
315 return getStoreXAction(VT) == Legal || getStoreXAction(VT) == Custom;
318 /// getIndexedLoadAction - Return how the indexed load should be treated:
319 /// either it is legal, needs to be promoted to a larger size, needs to be
320 /// expanded to some other code sequence, or the target has a custom expander
323 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const {
324 if (MVT::isExtendedVT(VT)) return getTypeAction(VT);
325 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3);
328 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
330 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const {
331 return getIndexedLoadAction(IdxMode, VT) == Legal ||
332 getIndexedLoadAction(IdxMode, VT) == Custom;
335 /// getIndexedStoreAction - Return how the indexed store should be treated:
336 /// either it is legal, needs to be promoted to a larger size, needs to be
337 /// expanded to some other code sequence, or the target has a custom expander
340 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const {
341 if (MVT::isExtendedVT(VT)) return getTypeAction(VT);
342 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3);
345 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
347 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const {
348 return getIndexedStoreAction(IdxMode, VT) == Legal ||
349 getIndexedStoreAction(IdxMode, VT) == Custom;
352 /// getConvertAction - Return how the conversion should be treated:
353 /// either it is legal, needs to be promoted to a larger size, needs to be
354 /// expanded to some other code sequence, or the target has a custom expander
357 getConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT) const {
358 assert(FromVT < MVT::LAST_VALUETYPE && ToVT < 32 &&
359 "Table isn't big enough!");
360 return (LegalizeAction)((ConvertActions[FromVT] >> (2*ToVT)) & 3);
363 /// isConvertLegal - Return true if the specified conversion is legal
365 bool isConvertLegal(MVT::ValueType FromVT, MVT::ValueType ToVT) const {
366 return getConvertAction(FromVT, ToVT) == Legal ||
367 getConvertAction(FromVT, ToVT) == Custom;
370 /// getTypeToPromoteTo - If the action for this operation is to promote, this
371 /// method returns the ValueType to promote to.
372 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
373 assert(getOperationAction(Op, VT) == Promote &&
374 "This operation isn't promoted!");
376 // See if this has an explicit type specified.
377 std::map<std::pair<unsigned, MVT::ValueType>,
378 MVT::ValueType>::const_iterator PTTI =
379 PromoteToType.find(std::make_pair(Op, VT));
380 if (PTTI != PromoteToType.end()) return PTTI->second;
382 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) &&
383 "Cannot autopromote this type, add it with AddPromotedToType.");
385 MVT::ValueType NVT = VT;
387 NVT = (MVT::ValueType)(NVT+1);
388 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid &&
389 "Didn't find type to promote to!");
390 } while (!isTypeLegal(NVT) ||
391 getOperationAction(Op, NVT) == Promote);
395 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type.
396 /// This is fixed by the LLVM operations except for the pointer size. If
397 /// AllowUnknown is true, this will return MVT::Other for types with no MVT
398 /// counterpart (e.g. structs), otherwise it will assert.
399 MVT::ValueType getValueType(const Type *Ty, bool AllowUnknown = false) const {
400 MVT::ValueType VT = MVT::getValueType(Ty, AllowUnknown);
401 return VT == MVT::iPTR ? PointerTy : VT;
404 /// getRegisterType - Return the type of registers that this ValueType will
405 /// eventually require.
406 MVT::ValueType getRegisterType(MVT::ValueType VT) const {
407 if (!MVT::isExtendedVT(VT))
408 return RegisterTypeForVT[VT];
409 if (MVT::isVector(VT)) {
410 MVT::ValueType VT1, RegisterVT;
411 unsigned NumIntermediates;
412 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
415 assert(0 && "Unsupported extended type!");
418 /// getNumRegisters - Return the number of registers that this ValueType will
419 /// eventually require. This is one for any types promoted to live in larger
420 /// registers, but may be more than one for types (like i64) that are split
422 unsigned getNumRegisters(MVT::ValueType VT) const {
423 if (!MVT::isExtendedVT(VT))
424 return NumRegistersForVT[VT];
425 if (MVT::isVector(VT)) {
426 MVT::ValueType VT1, VT2;
427 unsigned NumIntermediates;
428 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
430 assert(0 && "Unsupported extended type!");
433 /// hasTargetDAGCombine - If true, the target has custom DAG combine
434 /// transformations that it can perform for the specified node.
435 bool hasTargetDAGCombine(ISD::NodeType NT) const {
436 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
439 /// This function returns the maximum number of store operations permitted
440 /// to replace a call to llvm.memset. The value is set by the target at the
441 /// performance threshold for such a replacement.
442 /// @brief Get maximum # of store operations permitted for llvm.memset
443 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
445 /// This function returns the maximum number of store operations permitted
446 /// to replace a call to llvm.memcpy. The value is set by the target at the
447 /// performance threshold for such a replacement.
448 /// @brief Get maximum # of store operations permitted for llvm.memcpy
449 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
451 /// This function returns the maximum number of store operations permitted
452 /// to replace a call to llvm.memmove. The value is set by the target at the
453 /// performance threshold for such a replacement.
454 /// @brief Get maximum # of store operations permitted for llvm.memmove
455 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
457 /// This function returns true if the target allows unaligned memory accesses.
458 /// This is used, for example, in situations where an array copy/move/set is
459 /// converted to a sequence of store operations. It's use helps to ensure that
460 /// such replacements don't generate code that causes an alignment error
461 /// (trap) on the target machine.
462 /// @brief Determine if the target supports unaligned memory accesses.
463 bool allowsUnalignedMemoryAccesses() const {
464 return allowUnalignedMemoryAccesses;
467 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
468 /// to implement llvm.setjmp.
469 bool usesUnderscoreSetJmp() const {
470 return UseUnderscoreSetJmp;
473 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
474 /// to implement llvm.longjmp.
475 bool usesUnderscoreLongJmp() const {
476 return UseUnderscoreLongJmp;
479 /// getStackPointerRegisterToSaveRestore - If a physical register, this
480 /// specifies the register that llvm.savestack/llvm.restorestack should save
482 unsigned getStackPointerRegisterToSaveRestore() const {
483 return StackPointerRegisterToSaveRestore;
486 /// getExceptionAddressRegister - If a physical register, this returns
487 /// the register that receives the exception address on entry to a landing
489 unsigned getExceptionAddressRegister() const {
490 return ExceptionPointerRegister;
493 /// getExceptionSelectorRegister - If a physical register, this returns
494 /// the register that receives the exception typeid on entry to a landing
496 unsigned getExceptionSelectorRegister() const {
497 return ExceptionSelectorRegister;
500 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
501 /// set, the default is 200)
502 unsigned getJumpBufSize() const {
506 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
507 /// (if never set, the default is 0)
508 unsigned getJumpBufAlignment() const {
509 return JumpBufAlignment;
512 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
513 /// limit. Any block whose size is greater should not be predicated.
514 virtual unsigned getIfCvtBlockSizeLimit() const {
515 return IfCvtBlockSizeLimit;
518 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
519 /// block to be considered for duplication. Any block whose size is greater
520 /// should not be duplicated to facilitate its predication.
521 virtual unsigned getIfCvtDupBlockSizeLimit() const {
522 return IfCvtDupBlockSizeLimit;
525 /// getPreIndexedAddressParts - returns true by value, base pointer and
526 /// offset pointer and addressing mode by reference if the node's address
527 /// can be legally represented as pre-indexed load / store address.
528 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
530 ISD::MemIndexedMode &AM,
535 /// getPostIndexedAddressParts - returns true by value, base pointer and
536 /// offset pointer and addressing mode by reference if this node can be
537 /// combined with a load / store to form a post-indexed load / store.
538 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
539 SDOperand &Base, SDOperand &Offset,
540 ISD::MemIndexedMode &AM,
545 //===--------------------------------------------------------------------===//
546 // TargetLowering Optimization Methods
549 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
550 /// SDOperands for returning information from TargetLowering to its clients
551 /// that want to combine
552 struct TargetLoweringOpt {
557 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
559 bool CombineTo(SDOperand O, SDOperand N) {
565 /// ShrinkDemandedConstant - Check to see if the specified operand of the
566 /// specified instruction is a constant integer. If so, check to see if
567 /// there are any bits set in the constant that are not demanded. If so,
568 /// shrink the constant and return true.
569 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded);
572 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
573 /// DemandedMask bits of the result of Op are ever used downstream. If we can
574 /// use this information to simplify Op, create a new simplified DAG node and
575 /// return true, returning the original and new nodes in Old and New.
576 /// Otherwise, analyze the expression and return a mask of KnownOne and
577 /// KnownZero bits for the expression (used to simplify the caller).
578 /// The KnownZero/One bits may only be accurate for those bits in the
580 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
581 uint64_t &KnownZero, uint64_t &KnownOne,
582 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
584 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
585 /// Mask are known to be either zero or one and return them in the
586 /// KnownZero/KnownOne bitsets.
587 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
591 const SelectionDAG &DAG,
592 unsigned Depth = 0) const;
594 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
595 /// targets that want to expose additional information about sign bits to the
597 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op,
598 unsigned Depth = 0) const;
600 struct DAGCombinerInfo {
601 void *DC; // The DAG Combiner object.
603 bool CalledByLegalizer;
607 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc)
608 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {}
610 bool isBeforeLegalize() const { return BeforeLegalize; }
611 bool isCalledByLegalizer() const { return CalledByLegalizer; }
613 void AddToWorklist(SDNode *N);
614 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To);
615 SDOperand CombineTo(SDNode *N, SDOperand Res);
616 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1);
619 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
620 /// and cc. If it is unable to simplify it, return a null SDOperand.
621 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
622 ISD::CondCode Cond, bool foldBooleans,
623 DAGCombinerInfo &DCI) const;
625 /// PerformDAGCombine - This method will be invoked for all target nodes and
626 /// for any target-independent nodes that the target has registered with
629 /// The semantics are as follows:
631 /// SDOperand.Val == 0 - No change was made
632 /// SDOperand.Val == N - N was replaced, is dead, and is already handled.
633 /// otherwise - N should be replaced by the returned Operand.
635 /// In addition, methods provided by DAGCombinerInfo may be used to perform
636 /// more complex transformations.
638 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
640 //===--------------------------------------------------------------------===//
641 // TargetLowering Configuration Methods - These methods should be invoked by
642 // the derived class constructor to configure this object for the target.
646 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
647 /// GOT for PC-relative code.
648 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
650 /// setShiftAmountType - Describe the type that should be used for shift
651 /// amounts. This type defaults to the pointer type.
652 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
654 /// setSetCCResultType - Describe the type that shoudl be used as the result
655 /// of a setcc operation. This defaults to the pointer type.
656 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; }
658 /// setSetCCResultContents - Specify how the target extends the result of a
659 /// setcc operation in a register.
660 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
662 /// setSchedulingPreference - Specify the target scheduling preference.
663 void setSchedulingPreference(SchedPreference Pref) {
664 SchedPreferenceInfo = Pref;
667 /// setShiftAmountFlavor - Describe how the target handles out of range shift
669 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
670 ShiftAmtHandling = OORSA;
673 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
674 /// use _setjmp to implement llvm.setjmp or the non _ version.
675 /// Defaults to false.
676 void setUseUnderscoreSetJmp(bool Val) {
677 UseUnderscoreSetJmp = Val;
680 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
681 /// use _longjmp to implement llvm.longjmp or the non _ version.
682 /// Defaults to false.
683 void setUseUnderscoreLongJmp(bool Val) {
684 UseUnderscoreLongJmp = Val;
687 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
688 /// specifies the register that llvm.savestack/llvm.restorestack should save
690 void setStackPointerRegisterToSaveRestore(unsigned R) {
691 StackPointerRegisterToSaveRestore = R;
694 /// setExceptionPointerRegister - If set to a physical register, this sets
695 /// the register that receives the exception address on entry to a landing
697 void setExceptionPointerRegister(unsigned R) {
698 ExceptionPointerRegister = R;
701 /// setExceptionSelectorRegister - If set to a physical register, this sets
702 /// the register that receives the exception typeid on entry to a landing
704 void setExceptionSelectorRegister(unsigned R) {
705 ExceptionSelectorRegister = R;
708 /// SelectIsExpensive - Tells the code generator not to expand operations
709 /// into sequences that use the select operations if possible.
710 void setSelectIsExpensive() { SelectIsExpensive = true; }
712 /// setIntDivIsCheap - Tells the code generator that integer divide is
713 /// expensive, and if possible, should be replaced by an alternate sequence
714 /// of instructions not containing an integer divide.
715 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
717 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
718 /// srl/add/sra for a signed divide by power of two, and let the target handle
720 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
722 /// addRegisterClass - Add the specified register class as an available
723 /// regclass for the specified value type. This indicates the selector can
724 /// handle values of that class natively.
725 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) {
726 assert(!MVT::isExtendedVT(VT));
727 AvailableRegClasses.push_back(std::make_pair(VT, RC));
728 RegClassForVT[VT] = RC;
731 /// computeRegisterProperties - Once all of the register classes are added,
732 /// this allows us to compute derived properties we expose.
733 void computeRegisterProperties();
735 /// setOperationAction - Indicate that the specified operation does not work
736 /// with the specified type and indicate what to do about it.
737 void setOperationAction(unsigned Op, MVT::ValueType VT,
738 LegalizeAction Action) {
739 assert(VT < 32 && Op < array_lengthof(OpActions) &&
740 "Table isn't big enough!");
741 OpActions[Op] &= ~(uint64_t(3UL) << VT*2);
742 OpActions[Op] |= (uint64_t)Action << VT*2;
745 /// setLoadXAction - Indicate that the specified load with extension does not
746 /// work with the with specified type and indicate what to do about it.
747 void setLoadXAction(unsigned ExtType, MVT::ValueType VT,
748 LegalizeAction Action) {
749 assert(VT < 32 && ExtType < array_lengthof(LoadXActions) &&
750 "Table isn't big enough!");
751 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2);
752 LoadXActions[ExtType] |= (uint64_t)Action << VT*2;
755 /// setStoreXAction - Indicate that the specified store with truncation does
756 /// not work with the with specified type and indicate what to do about it.
757 void setStoreXAction(MVT::ValueType VT, LegalizeAction Action) {
758 assert(VT < 32 && "Table isn't big enough!");
759 StoreXActions &= ~(uint64_t(3UL) << VT*2);
760 StoreXActions |= (uint64_t)Action << VT*2;
763 /// setIndexedLoadAction - Indicate that the specified indexed load does or
764 /// does not work with the with specified type and indicate what to do abort
765 /// it. NOTE: All indexed mode loads are initialized to Expand in
766 /// TargetLowering.cpp
767 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT,
768 LegalizeAction Action) {
769 assert(VT < 32 && IdxMode <
770 array_lengthof(IndexedModeActions[0]) &&
771 "Table isn't big enough!");
772 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2);
773 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2;
776 /// setIndexedStoreAction - Indicate that the specified indexed store does or
777 /// does not work with the with specified type and indicate what to do about
778 /// it. NOTE: All indexed mode stores are initialized to Expand in
779 /// TargetLowering.cpp
780 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT,
781 LegalizeAction Action) {
782 assert(VT < 32 && IdxMode <
783 array_lengthof(IndexedModeActions[1]) &&
784 "Table isn't big enough!");
785 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2);
786 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2;
789 /// setConvertAction - Indicate that the specified conversion does or does
790 /// not work with the with specified type and indicate what to do about it.
791 void setConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT,
792 LegalizeAction Action) {
793 assert(FromVT < MVT::LAST_VALUETYPE && ToVT < 32 &&
794 "Table isn't big enough!");
795 ConvertActions[FromVT] &= ~(uint64_t(3UL) << ToVT*2);
796 ConvertActions[FromVT] |= (uint64_t)Action << ToVT*2;
799 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
800 /// promotion code defaults to trying a larger integer/fp until it can find
801 /// one that works. If that default is insufficient, this method can be used
802 /// by the target to override the default.
803 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT,
804 MVT::ValueType DestVT) {
805 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
808 /// addLegalFPImmediate - Indicate that this target can instruction select
809 /// the specified FP immediate natively.
810 void addLegalFPImmediate(const APFloat& Imm) {
811 LegalFPImmediates.push_back(Imm);
814 /// setTargetDAGCombine - Targets should invoke this method for each target
815 /// independent node that they want to provide a custom DAG combiner for by
816 /// implementing the PerformDAGCombine virtual method.
817 void setTargetDAGCombine(ISD::NodeType NT) {
818 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
821 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
822 /// bytes); default is 200
823 void setJumpBufSize(unsigned Size) {
827 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
828 /// alignment (in bytes); default is 0
829 void setJumpBufAlignment(unsigned Align) {
830 JumpBufAlignment = Align;
833 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
834 /// limit (in number of instructions); default is 2.
835 void setIfCvtBlockSizeLimit(unsigned Limit) {
836 IfCvtBlockSizeLimit = Limit;
839 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
840 /// of instructions) to be considered for code duplication during
841 /// if-conversion; default is 2.
842 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
843 IfCvtDupBlockSizeLimit = Limit;
848 //===--------------------------------------------------------------------===//
849 // Lowering methods - These methods must be implemented by targets so that
850 // the SelectionDAGLowering code knows how to lower these.
853 /// LowerArguments - This hook must be implemented to indicate how we should
854 /// lower the arguments for the specified function, into the specified DAG.
855 virtual std::vector<SDOperand>
856 LowerArguments(Function &F, SelectionDAG &DAG);
858 /// LowerCallTo - This hook lowers an abstract call to a function into an
859 /// actual call. This returns a pair of operands. The first element is the
860 /// return value for the function (if RetTy is not VoidTy). The second
861 /// element is the outgoing token chain.
862 struct ArgListEntry {
872 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
873 isSRet(false), isNest(false), isByVal(false) { }
875 typedef std::vector<ArgListEntry> ArgListTy;
876 virtual std::pair<SDOperand, SDOperand>
877 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned,
878 bool isVarArg, unsigned CallingConv, bool isTailCall,
879 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
881 /// LowerOperation - This callback is invoked for operations that are
882 /// unsupported by the target, which are registered to use 'custom' lowering,
883 /// and whose defined values are all legal.
884 /// If the target has no operations that require custom lowering, it need not
885 /// implement this. The default implementation of this aborts.
886 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
888 /// ExpandOperationResult - This callback is invoked for operations that are
889 /// unsupported by the target, which are registered to use 'custom' lowering,
890 /// and whose result type needs to be expanded.
892 /// If the target has no operations that require custom lowering, it need not
893 /// implement this. The default implementation of this aborts.
894 virtual std::pair<SDOperand,SDOperand>
895 ExpandOperationResult(SDNode *N, SelectionDAG &DAG);
897 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for
898 /// tail call optimization. Targets which want to do tail call optimization
899 /// should override this function.
900 virtual bool IsEligibleForTailCallOptimization(SDOperand Call,
902 SelectionDAG &DAG) const {
906 /// CustomPromoteOperation - This callback is invoked for operations that are
907 /// unsupported by the target, are registered to use 'custom' lowering, and
908 /// whose type needs to be promoted.
909 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG);
911 /// getTargetNodeName() - This method returns the name of a target specific
913 virtual const char *getTargetNodeName(unsigned Opcode) const;
915 //===--------------------------------------------------------------------===//
916 // Inline Asm Support hooks
919 enum ConstraintType {
920 C_Register, // Constraint represents a single register.
921 C_RegisterClass, // Constraint represents one or more registers.
922 C_Memory, // Memory constraint.
923 C_Other, // Something else.
924 C_Unknown // Unsupported constraint.
927 /// getConstraintType - Given a constraint, return the type of constraint it
928 /// is for this target.
929 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
932 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
933 /// return a list of registers that can be used to satisfy the constraint.
934 /// This should only be used for C_RegisterClass constraints.
935 virtual std::vector<unsigned>
936 getRegClassForInlineAsmConstraint(const std::string &Constraint,
937 MVT::ValueType VT) const;
939 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
940 /// {edx}), return the register number and the register class for the
943 /// Given a register class constraint, like 'r', if this corresponds directly
944 /// to an LLVM register class, return a register of 0 and the register class
947 /// This should only be used for C_Register constraints. On error,
948 /// this returns a register number of 0 and a null register class pointer..
949 virtual std::pair<unsigned, const TargetRegisterClass*>
950 getRegForInlineAsmConstraint(const std::string &Constraint,
951 MVT::ValueType VT) const;
954 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
955 /// vector. If it is invalid, don't add anything to Ops.
956 virtual void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter,
957 std::vector<SDOperand> &Ops,
960 //===--------------------------------------------------------------------===//
964 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
965 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
966 // instructions are special in various ways, which require special support to
967 // insert. The specified MachineInstr is created but not inserted into any
968 // basic blocks, and the scheduler passes ownership of it to this method.
969 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
970 MachineBasicBlock *MBB);
972 //===--------------------------------------------------------------------===//
973 // Addressing mode description hooks (used by LSR etc).
976 /// AddrMode - This represents an addressing mode of:
977 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
978 /// If BaseGV is null, there is no BaseGV.
979 /// If BaseOffs is zero, there is no base offset.
980 /// If HasBaseReg is false, there is no base register.
981 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
989 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
992 /// isLegalAddressingMode - Return true if the addressing mode represented by
993 /// AM is legal for this target, for a load/store of the specified type.
994 /// TODO: Handle pre/postinc as well.
995 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
997 //===--------------------------------------------------------------------===//
998 // Div utility functions
1000 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG,
1001 std::vector<SDNode*>* Created) const;
1002 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG,
1003 std::vector<SDNode*>* Created) const;
1006 //===--------------------------------------------------------------------===//
1007 // Runtime Library hooks
1010 /// setLibcallName - Rename the default libcall routine name for the specified
1012 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1013 LibcallRoutineNames[Call] = Name;
1016 /// getLibcallName - Get the libcall routine name for the specified libcall.
1018 const char *getLibcallName(RTLIB::Libcall Call) const {
1019 return LibcallRoutineNames[Call];
1022 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1023 /// result of the comparison libcall against zero.
1024 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1025 CmpLibcallCCs[Call] = CC;
1028 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1029 /// the comparison libcall against zero.
1030 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1031 return CmpLibcallCCs[Call];
1036 const TargetData *TD;
1038 /// IsLittleEndian - True if this is a little endian target.
1040 bool IsLittleEndian;
1042 /// PointerTy - The type to use for pointers, usually i32 or i64.
1044 MVT::ValueType PointerTy;
1046 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
1048 bool UsesGlobalOffsetTable;
1050 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1052 MVT::ValueType ShiftAmountTy;
1054 OutOfRangeShiftAmount ShiftAmtHandling;
1056 /// SelectIsExpensive - Tells the code generator not to expand operations
1057 /// into sequences that use the select operations if possible.
1058 bool SelectIsExpensive;
1060 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1061 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1062 /// a real cost model is in place. If we ever optimize for size, this will be
1063 /// set to true unconditionally.
1066 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1067 /// srl/add/sra for a signed divide by power of two, and let the target handle
1069 bool Pow2DivIsCheap;
1071 /// SetCCResultTy - The type that SetCC operations use. This defaults to the
1073 MVT::ValueType SetCCResultTy;
1075 /// SetCCResultContents - Information about the contents of the high-bits in
1076 /// the result of a setcc comparison operation.
1077 SetCCResultValue SetCCResultContents;
1079 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1080 /// total cycles or lowest register usage.
1081 SchedPreference SchedPreferenceInfo;
1083 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1084 /// llvm.setjmp. Defaults to false.
1085 bool UseUnderscoreSetJmp;
1087 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1088 /// llvm.longjmp. Defaults to false.
1089 bool UseUnderscoreLongJmp;
1091 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1092 unsigned JumpBufSize;
1094 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1096 unsigned JumpBufAlignment;
1098 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1100 unsigned IfCvtBlockSizeLimit;
1102 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1103 /// duplicated during if-conversion.
1104 unsigned IfCvtDupBlockSizeLimit;
1106 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1107 /// specifies the register that llvm.savestack/llvm.restorestack should save
1109 unsigned StackPointerRegisterToSaveRestore;
1111 /// ExceptionPointerRegister - If set to a physical register, this specifies
1112 /// the register that receives the exception address on entry to a landing
1114 unsigned ExceptionPointerRegister;
1116 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1117 /// the register that receives the exception typeid on entry to a landing
1119 unsigned ExceptionSelectorRegister;
1121 /// RegClassForVT - This indicates the default register class to use for
1122 /// each ValueType the target supports natively.
1123 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1124 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1125 MVT::ValueType RegisterTypeForVT[MVT::LAST_VALUETYPE];
1127 /// TransformToType - For any value types we are promoting or expanding, this
1128 /// contains the value type that we are changing to. For Expanded types, this
1129 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1130 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1131 /// by the system, this holds the same type (e.g. i32 -> i32).
1132 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
1134 /// OpActions - For each operation and each value type, keep a LegalizeAction
1135 /// that indicates how instruction selection should deal with the operation.
1136 /// Most operations are Legal (aka, supported natively by the target), but
1137 /// operations that are not should be described. Note that operations on
1138 /// non-legal value types are not described here.
1139 uint64_t OpActions[156];
1141 /// LoadXActions - For each load of load extension type and each value type,
1142 /// keep a LegalizeAction that indicates how instruction selection should deal
1144 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE];
1146 /// StoreXActions - For each store with truncation of each value type, keep a
1147 /// LegalizeAction that indicates how instruction selection should deal with
1149 uint64_t StoreXActions;
1151 /// IndexedModeActions - For each indexed mode and each value type, keep a
1152 /// pair of LegalizeAction that indicates how instruction selection should
1153 /// deal with the load / store.
1154 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
1156 /// ConvertActions - For each conversion from source type to destination type,
1157 /// keep a LegalizeAction that indicates how instruction selection should
1158 /// deal with the conversion.
1159 /// Currently, this is used only for floating->floating conversions
1160 /// (FP_EXTEND and FP_ROUND).
1161 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
1163 ValueTypeActionImpl ValueTypeActions;
1165 std::vector<APFloat> LegalFPImmediates;
1167 std::vector<std::pair<MVT::ValueType,
1168 TargetRegisterClass*> > AvailableRegClasses;
1170 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1171 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1172 /// which sets a bit in this array.
1173 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)];
1175 /// PromoteToType - For operations that must be promoted to a specific type,
1176 /// this holds the destination type. This map should be sparse, so don't hold
1179 /// Targets add entries to this map with AddPromotedToType(..), clients access
1180 /// this with getTypeToPromoteTo(..).
1181 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType;
1183 /// LibcallRoutineNames - Stores the name each libcall.
1185 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1187 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1188 /// of each of the comparison libcall against zero.
1189 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1192 /// When lowering %llvm.memset this field specifies the maximum number of
1193 /// store operations that may be substituted for the call to memset. Targets
1194 /// must set this value based on the cost threshold for that target. Targets
1195 /// should assume that the memset will be done using as many of the largest
1196 /// store operations first, followed by smaller ones, if necessary, per
1197 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1198 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1199 /// store. This only applies to setting a constant array of a constant size.
1200 /// @brief Specify maximum number of store instructions per memset call.
1201 unsigned maxStoresPerMemset;
1203 /// When lowering %llvm.memcpy this field specifies the maximum number of
1204 /// store operations that may be substituted for a call to memcpy. Targets
1205 /// must set this value based on the cost threshold for that target. Targets
1206 /// should assume that the memcpy will be done using as many of the largest
1207 /// store operations first, followed by smaller ones, if necessary, per
1208 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1209 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1210 /// and one 1-byte store. This only applies to copying a constant array of
1212 /// @brief Specify maximum bytes of store instructions per memcpy call.
1213 unsigned maxStoresPerMemcpy;
1215 /// When lowering %llvm.memmove this field specifies the maximum number of
1216 /// store instructions that may be substituted for a call to memmove. Targets
1217 /// must set this value based on the cost threshold for that target. Targets
1218 /// should assume that the memmove will be done using as many of the largest
1219 /// store operations first, followed by smaller ones, if necessary, per
1220 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1221 /// with 8-bit alignment would result in nine 1-byte stores. This only
1222 /// applies to copying a constant array of constant size.
1223 /// @brief Specify maximum bytes of store instructions per memmove call.
1224 unsigned maxStoresPerMemmove;
1226 /// This field specifies whether the target machine permits unaligned memory
1227 /// accesses. This is used, for example, to determine the size of store
1228 /// operations when copying small arrays and other similar tasks.
1229 /// @brief Indicate whether the target permits unaligned memory accesses.
1230 bool allowUnalignedMemoryAccesses;
1232 } // end llvm namespace