1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/IRBuilder.h"
34 #include "llvm/IR/InlineAsm.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/Target/TargetCallingConv.h"
38 #include "llvm/Target/TargetMachine.h"
47 class FunctionLoweringInfo;
48 class ImmutableCallSite;
50 class MachineBasicBlock;
51 class MachineFunction;
53 class MachineJumpTableInfo;
59 template<typename T> class SmallVectorImpl;
61 class TargetRegisterClass;
62 class TargetLibraryInfo;
63 class TargetLoweringObjectFile;
68 None, // No preference
69 Source, // Follow source order.
70 RegPressure, // Scheduling for lowest register pressure.
71 Hybrid, // Scheduling for both latency and register pressure.
72 ILP, // Scheduling for ILP in low register pressure mode.
73 VLIW // Scheduling for VLIW targets.
77 /// This base class for TargetLowering contains the SelectionDAG-independent
78 /// parts that can be used from the rest of CodeGen.
79 class TargetLoweringBase {
80 TargetLoweringBase(const TargetLoweringBase&) = delete;
81 void operator=(const TargetLoweringBase&) = delete;
84 /// This enum indicates whether operations are valid for a target, and if not,
85 /// what action should be used to make them valid.
87 Legal, // The target natively supports this operation.
88 Promote, // This operation should be executed in a larger type.
89 Expand, // Try to expand this to other ops, otherwise use a libcall.
90 LibCall, // Don't try to expand this to other ops, always use a libcall.
91 Custom // Use the LowerOperation hook to implement custom lowering.
94 /// This enum indicates whether a types are legal for a target, and if not,
95 /// what action should be used to make them valid.
96 enum LegalizeTypeAction {
97 TypeLegal, // The target natively supports this type.
98 TypePromoteInteger, // Replace this integer with a larger one.
99 TypeExpandInteger, // Split this integer into two of half the size.
100 TypeSoftenFloat, // Convert this float to a same size integer type.
101 TypeExpandFloat, // Split this float into two of half the size.
102 TypeScalarizeVector, // Replace this one-element vector with its element.
103 TypeSplitVector, // Split this vector into two of half the size.
104 TypeWidenVector, // This vector should be widened into a larger vector.
105 TypePromoteFloat // Replace this float with a larger one.
108 /// LegalizeKind holds the legalization kind that needs to happen to EVT
109 /// in order to type-legalize it.
110 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
112 /// Enum that describes how the target represents true/false values.
113 enum BooleanContent {
114 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
115 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
116 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
119 /// Enum that describes what type of support for selects the target has.
120 enum SelectSupportKind {
121 ScalarValSelect, // The target supports scalar selects (ex: cmov).
122 ScalarCondVectorVal, // The target supports selects with a scalar condition
123 // and vector values (ex: cmov).
124 VectorMaskSelect // The target supports vector selects with a vector
125 // mask (ex: x86 blends).
128 /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
129 /// to, if at all. Exists because different targets have different levels of
130 /// support for these atomic instructions, and also have different options
131 /// w.r.t. what they should expand to.
132 enum class AtomicExpansionKind {
133 None, // Don't expand the instruction.
134 LLSC, // Expand the instruction into loadlinked/storeconditional; used
136 CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
139 static ISD::NodeType getExtendForContent(BooleanContent Content) {
141 case UndefinedBooleanContent:
142 // Extend by adding rubbish bits.
143 return ISD::ANY_EXTEND;
144 case ZeroOrOneBooleanContent:
145 // Extend by adding zero bits.
146 return ISD::ZERO_EXTEND;
147 case ZeroOrNegativeOneBooleanContent:
148 // Extend by copying the sign bit.
149 return ISD::SIGN_EXTEND;
151 llvm_unreachable("Invalid content kind");
154 /// NOTE: The TargetMachine owns TLOF.
155 explicit TargetLoweringBase(const TargetMachine &TM);
156 virtual ~TargetLoweringBase() {}
159 /// \brief Initialize all of the actions to default values.
163 const TargetMachine &getTargetMachine() const { return TM; }
165 virtual bool useSoftFloat() const { return false; }
167 /// Return the pointer type for the given address space, defaults to
168 /// the pointer type from the data layout.
169 /// FIXME: The default needs to be removed once all the code is updated.
170 MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
171 return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
174 /// EVT is not used in-tree, but is used by out-of-tree target.
175 /// A documentation for this function would be nice...
176 virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
178 EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const;
180 /// Returns the type to be used for the index operand of:
181 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
182 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
183 virtual MVT getVectorIdxTy(const DataLayout &DL) const {
184 return getPointerTy(DL);
187 /// Return true if the select operation is expensive for this target.
188 bool isSelectExpensive() const { return SelectIsExpensive; }
190 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
194 /// Return true if multiple condition registers are available.
195 bool hasMultipleConditionRegisters() const {
196 return HasMultipleConditionRegisters;
199 /// Return true if the target has BitExtract instructions.
200 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
202 /// Return the preferred vector type legalization action.
203 virtual TargetLoweringBase::LegalizeTypeAction
204 getPreferredVectorAction(EVT VT) const {
205 // The default action for one element vectors is to scalarize
206 if (VT.getVectorNumElements() == 1)
207 return TypeScalarizeVector;
208 // The default action for other vectors is to promote
209 return TypePromoteInteger;
212 // There are two general methods for expanding a BUILD_VECTOR node:
213 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
215 // 2. Build the vector on the stack and then load it.
216 // If this function returns true, then method (1) will be used, subject to
217 // the constraint that all of the necessary shuffles are legal (as determined
218 // by isShuffleMaskLegal). If this function returns false, then method (2) is
219 // always used. The vector type, and the number of defined values, are
222 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
223 unsigned DefinedValues) const {
224 return DefinedValues < 3;
227 /// Return true if integer divide is usually cheaper than a sequence of
228 /// several shifts, adds, and multiplies for this target.
229 /// The definition of "cheaper" may depend on whether we're optimizing
230 /// for speed or for size.
231 virtual bool isIntDivCheap(EVT VT, AttributeSet Attr) const {
235 /// Return true if sqrt(x) is as cheap or cheaper than 1 / rsqrt(x)
236 bool isFsqrtCheap() const {
240 /// Returns true if target has indicated at least one type should be bypassed.
241 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
243 /// Returns map of slow types for division or remainder with corresponding
245 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
246 return BypassSlowDivWidths;
249 /// Return true if Flow Control is an expensive operation that should be
251 bool isJumpExpensive() const { return JumpIsExpensive; }
253 /// Return true if selects are only cheaper than branches if the branch is
254 /// unlikely to be predicted right.
255 bool isPredictableSelectExpensive() const {
256 return PredictableSelectIsExpensive;
259 /// isLoadBitCastBeneficial() - Return true if the following transform
261 /// fold (conv (load x)) -> (load (conv*)x)
262 /// On architectures that don't natively support some vector loads
263 /// efficiently, casting the load to a smaller vector of larger types and
264 /// loading is more efficient, however, this can be undone by optimizations in
266 virtual bool isLoadBitCastBeneficial(EVT /* Load */,
267 EVT /* Bitcast */) const {
271 /// Return true if it is expected to be cheaper to do a store of a non-zero
272 /// vector constant with the given size and type for the address space than to
273 /// store the individual scalar element constants.
274 virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
276 unsigned AddrSpace) const {
280 /// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
281 virtual bool isCheapToSpeculateCttz() const {
285 /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
286 virtual bool isCheapToSpeculateCtlz() const {
290 /// \brief Return if the target supports combining a
293 /// %andResult = and %val1, #imm-with-one-bit-set;
294 /// %icmpResult = icmp %andResult, 0
295 /// br i1 %icmpResult, label %dest1, label %dest2
297 /// into a single machine instruction of a form like:
299 /// brOnBitSet %register, #bitNumber, dest
301 bool isMaskAndBranchFoldingLegal() const {
302 return MaskAndBranchFoldingIsLegal;
305 /// \brief Return true if the target wants to use the optimization that
306 /// turns ext(promotableInst1(...(promotableInstN(load)))) into
307 /// promotedInst1(...(promotedInstN(ext(load)))).
308 bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
310 /// Return true if the target can combine store(extractelement VectorTy,
312 /// \p Cost[out] gives the cost of that transformation when this is true.
313 virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
314 unsigned &Cost) const {
318 /// Return true if target supports floating point exceptions.
319 bool hasFloatingPointExceptions() const {
320 return HasFloatingPointExceptions;
323 /// Return true if target always beneficiates from combining into FMA for a
324 /// given value type. This must typically return false on targets where FMA
325 /// takes more cycles to execute than FADD.
326 virtual bool enableAggressiveFMAFusion(EVT VT) const {
330 /// Return the ValueType of the result of SETCC operations.
331 virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
334 /// Return the ValueType for comparison libcalls. Comparions libcalls include
335 /// floating point comparion calls, and Ordered/Unordered check calls on
336 /// floating point numbers.
338 MVT::SimpleValueType getCmpLibcallReturnType() const;
340 /// For targets without i1 registers, this gives the nature of the high-bits
341 /// of boolean values held in types wider than i1.
343 /// "Boolean values" are special true/false values produced by nodes like
344 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
345 /// Not to be confused with general values promoted from i1. Some cpus
346 /// distinguish between vectors of boolean and scalars; the isVec parameter
347 /// selects between the two kinds. For example on X86 a scalar boolean should
348 /// be zero extended from i1, while the elements of a vector of booleans
349 /// should be sign extended from i1.
351 /// Some cpus also treat floating point types the same way as they treat
352 /// vectors instead of the way they treat scalars.
353 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
355 return BooleanVectorContents;
356 return isFloat ? BooleanFloatContents : BooleanContents;
359 BooleanContent getBooleanContents(EVT Type) const {
360 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
363 /// Return target scheduling preference.
364 Sched::Preference getSchedulingPreference() const {
365 return SchedPreferenceInfo;
368 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
369 /// for different nodes. This function returns the preference (or none) for
371 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
375 /// Return the register class that should be used for the specified value
377 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
378 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
379 assert(RC && "This value type is not natively supported!");
383 /// Return the 'representative' register class for the specified value
386 /// The 'representative' register class is the largest legal super-reg
387 /// register class for the register class of the value type. For example, on
388 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
389 /// register class is GR64 on x86_64.
390 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
391 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
395 /// Return the cost of the 'representative' register class for the specified
397 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
398 return RepRegClassCostForVT[VT.SimpleTy];
401 /// Return true if the target has native support for the specified value type.
402 /// This means that it has a register that directly holds it without
403 /// promotions or expansions.
404 bool isTypeLegal(EVT VT) const {
405 assert(!VT.isSimple() ||
406 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
407 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
410 class ValueTypeActionImpl {
411 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
412 /// that indicates how instruction selection should deal with the type.
413 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
416 ValueTypeActionImpl() {
417 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions), 0);
420 LegalizeTypeAction getTypeAction(MVT VT) const {
421 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
424 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
425 unsigned I = VT.SimpleTy;
426 ValueTypeActions[I] = Action;
430 const ValueTypeActionImpl &getValueTypeActions() const {
431 return ValueTypeActions;
434 /// Return how we should legalize values of this type, either it is already
435 /// legal (return 'Legal') or we need to promote it to a larger type (return
436 /// 'Promote'), or we need to expand it into multiple registers of smaller
437 /// integer type (return 'Expand'). 'Custom' is not an option.
438 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
439 return getTypeConversion(Context, VT).first;
441 LegalizeTypeAction getTypeAction(MVT VT) const {
442 return ValueTypeActions.getTypeAction(VT);
445 /// For types supported by the target, this is an identity function. For
446 /// types that must be promoted to larger types, this returns the larger type
447 /// to promote to. For integer types that are larger than the largest integer
448 /// register, this contains one step in the expansion to get to the smaller
449 /// register. For illegal floating point types, this returns the integer type
451 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
452 return getTypeConversion(Context, VT).second;
455 /// For types supported by the target, this is an identity function. For
456 /// types that must be expanded (i.e. integer types that are larger than the
457 /// largest integer register or illegal floating point types), this returns
458 /// the largest legal type it will be expanded to.
459 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
460 assert(!VT.isVector());
462 switch (getTypeAction(Context, VT)) {
465 case TypeExpandInteger:
466 VT = getTypeToTransformTo(Context, VT);
469 llvm_unreachable("Type is not legal nor is it to be expanded!");
474 /// Vector types are broken down into some number of legal first class types.
475 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
476 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
477 /// turns into 4 EVT::i32 values with both PPC and X86.
479 /// This method returns the number of registers needed, and the VT for each
480 /// register. It also returns the VT and quantity of the intermediate values
481 /// before they are promoted/expanded.
482 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
484 unsigned &NumIntermediates,
485 MVT &RegisterVT) const;
487 struct IntrinsicInfo {
488 unsigned opc; // target opcode
489 EVT memVT; // memory VT
490 const Value* ptrVal; // value representing memory location
491 int offset; // offset off of ptrVal
492 unsigned size; // the size of the memory location
493 // (taken from memVT if zero)
494 unsigned align; // alignment
495 bool vol; // is volatile?
496 bool readMem; // reads memory?
497 bool writeMem; // writes memory?
499 IntrinsicInfo() : opc(0), ptrVal(nullptr), offset(0), size(0), align(1),
500 vol(false), readMem(false), writeMem(false) {}
503 /// Given an intrinsic, checks if on the target the intrinsic will need to map
504 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
505 /// true and store the intrinsic information into the IntrinsicInfo that was
506 /// passed to the function.
507 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
508 unsigned /*Intrinsic*/) const {
512 /// Returns true if the target can instruction select the specified FP
513 /// immediate natively. If false, the legalizer will materialize the FP
514 /// immediate as a load from a constant pool.
515 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
519 /// Targets can use this to indicate that they only support *some*
520 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
521 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
523 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
528 /// Returns true if the operation can trap for the value type.
530 /// VT must be a legal type. By default, we optimistically assume most
531 /// operations don't trap except for divide and remainder.
532 virtual bool canOpTrap(unsigned Op, EVT VT) const;
534 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
535 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
536 /// a VAND with a constant pool entry.
537 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
542 /// Return how this operation should be treated: either it is legal, needs to
543 /// be promoted to a larger size, needs to be expanded to some other code
544 /// sequence, or the target has a custom expander for it.
545 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
546 if (VT.isExtended()) return Expand;
547 // If a target-specific SDNode requires legalization, require the target
548 // to provide custom legalization for it.
549 if (Op > array_lengthof(OpActions[0])) return Custom;
550 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
551 return (LegalizeAction)OpActions[I][Op];
554 /// Return true if the specified operation is legal on this target or can be
555 /// made legal with custom lowering. This is used to help guide high-level
556 /// lowering decisions.
557 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
558 return (VT == MVT::Other || isTypeLegal(VT)) &&
559 (getOperationAction(Op, VT) == Legal ||
560 getOperationAction(Op, VT) == Custom);
563 /// Return true if the specified operation is legal on this target or can be
564 /// made legal using promotion. This is used to help guide high-level lowering
566 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
567 return (VT == MVT::Other || isTypeLegal(VT)) &&
568 (getOperationAction(Op, VT) == Legal ||
569 getOperationAction(Op, VT) == Promote);
572 /// Return true if the specified operation is illegal on this target or
573 /// unlikely to be made legal with custom lowering. This is used to help guide
574 /// high-level lowering decisions.
575 bool isOperationExpand(unsigned Op, EVT VT) const {
576 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
579 /// Return true if the specified operation is legal on this target.
580 bool isOperationLegal(unsigned Op, EVT VT) const {
581 return (VT == MVT::Other || isTypeLegal(VT)) &&
582 getOperationAction(Op, VT) == Legal;
585 /// Return how this load with extension should be treated: either it is legal,
586 /// needs to be promoted to a larger size, needs to be expanded to some other
587 /// code sequence, or the target has a custom expander for it.
588 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
590 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
591 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
592 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
593 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
594 MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
595 return (LegalizeAction)LoadExtActions[ValI][MemI][ExtType];
598 /// Return true if the specified load with extension is legal on this target.
599 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
600 return ValVT.isSimple() && MemVT.isSimple() &&
601 getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
604 /// Return true if the specified load with extension is legal or custom
606 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
607 return ValVT.isSimple() && MemVT.isSimple() &&
608 (getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
609 getLoadExtAction(ExtType, ValVT, MemVT) == Custom);
612 /// Return how this store with truncation should be treated: either it is
613 /// legal, needs to be promoted to a larger size, needs to be expanded to some
614 /// other code sequence, or the target has a custom expander for it.
615 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
616 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
617 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
618 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
619 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
620 "Table isn't big enough!");
621 return (LegalizeAction)TruncStoreActions[ValI][MemI];
624 /// Return true if the specified store with truncation is legal on this
626 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
627 return isTypeLegal(ValVT) && MemVT.isSimple() &&
628 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
631 /// Return how the indexed load should be treated: either it is legal, needs
632 /// to be promoted to a larger size, needs to be expanded to some other code
633 /// sequence, or the target has a custom expander for it.
635 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
636 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
637 "Table isn't big enough!");
638 unsigned Ty = (unsigned)VT.SimpleTy;
639 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
642 /// Return true if the specified indexed load is legal on this target.
643 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
644 return VT.isSimple() &&
645 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
646 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
649 /// Return how the indexed store should be treated: either it is legal, needs
650 /// to be promoted to a larger size, needs to be expanded to some other code
651 /// sequence, or the target has a custom expander for it.
653 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
654 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
655 "Table isn't big enough!");
656 unsigned Ty = (unsigned)VT.SimpleTy;
657 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
660 /// Return true if the specified indexed load is legal on this target.
661 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
662 return VT.isSimple() &&
663 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
664 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
667 /// Return how the condition code should be treated: either it is legal, needs
668 /// to be expanded to some other code sequence, or the target has a custom
671 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
672 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
673 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
674 "Table isn't big enough!");
675 // See setCondCodeAction for how this is encoded.
676 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
677 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
678 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
679 assert(Action != Promote && "Can't promote condition code!");
683 /// Return true if the specified condition code is legal on this target.
684 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
686 getCondCodeAction(CC, VT) == Legal ||
687 getCondCodeAction(CC, VT) == Custom;
691 /// If the action for this operation is to promote, this method returns the
692 /// ValueType to promote to.
693 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
694 assert(getOperationAction(Op, VT) == Promote &&
695 "This operation isn't promoted!");
697 // See if this has an explicit type specified.
698 std::map<std::pair<unsigned, MVT::SimpleValueType>,
699 MVT::SimpleValueType>::const_iterator PTTI =
700 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
701 if (PTTI != PromoteToType.end()) return PTTI->second;
703 assert((VT.isInteger() || VT.isFloatingPoint()) &&
704 "Cannot autopromote this type, add it with AddPromotedToType.");
708 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
709 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
710 "Didn't find type to promote to!");
711 } while (!isTypeLegal(NVT) ||
712 getOperationAction(Op, NVT) == Promote);
716 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
717 /// operations except for the pointer size. If AllowUnknown is true, this
718 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
719 /// otherwise it will assert.
720 EVT getValueType(const DataLayout &DL, Type *Ty,
721 bool AllowUnknown = false) const {
722 // Lower scalar pointers to native pointer types.
723 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
724 return getPointerTy(DL, PTy->getAddressSpace());
726 if (Ty->isVectorTy()) {
727 VectorType *VTy = cast<VectorType>(Ty);
728 Type *Elm = VTy->getElementType();
729 // Lower vectors of pointers to native pointer types.
730 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
731 EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
732 Elm = PointerTy.getTypeForEVT(Ty->getContext());
735 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
736 VTy->getNumElements());
738 return EVT::getEVT(Ty, AllowUnknown);
741 /// Return the MVT corresponding to this LLVM type. See getValueType.
742 MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
743 bool AllowUnknown = false) const {
744 return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
747 /// Return the desired alignment for ByVal or InAlloca aggregate function
748 /// arguments in the caller parameter area. This is the actual alignment, not
750 virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
752 /// Return the type of registers that this ValueType will eventually require.
753 MVT getRegisterType(MVT VT) const {
754 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
755 return RegisterTypeForVT[VT.SimpleTy];
758 /// Return the type of registers that this ValueType will eventually require.
759 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
761 assert((unsigned)VT.getSimpleVT().SimpleTy <
762 array_lengthof(RegisterTypeForVT));
763 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
768 unsigned NumIntermediates;
769 (void)getVectorTypeBreakdown(Context, VT, VT1,
770 NumIntermediates, RegisterVT);
773 if (VT.isInteger()) {
774 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
776 llvm_unreachable("Unsupported extended type!");
779 /// Return the number of registers that this ValueType will eventually
782 /// This is one for any types promoted to live in larger registers, but may be
783 /// more than one for types (like i64) that are split into pieces. For types
784 /// like i140, which are first promoted then expanded, it is the number of
785 /// registers needed to hold all the bits of the original type. For an i140
786 /// on a 32 bit machine this means 5 registers.
787 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
789 assert((unsigned)VT.getSimpleVT().SimpleTy <
790 array_lengthof(NumRegistersForVT));
791 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
796 unsigned NumIntermediates;
797 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
799 if (VT.isInteger()) {
800 unsigned BitWidth = VT.getSizeInBits();
801 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
802 return (BitWidth + RegWidth - 1) / RegWidth;
804 llvm_unreachable("Unsupported extended type!");
807 /// If true, then instruction selection should seek to shrink the FP constant
808 /// of the specified type to a smaller type in order to save space and / or
810 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
812 // Return true if it is profitable to reduce the given load node to a smaller
815 // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
816 virtual bool shouldReduceLoadWidth(SDNode *Load,
817 ISD::LoadExtType ExtTy,
822 /// When splitting a value of the specified type into parts, does the Lo
823 /// or Hi part come first? This usually follows the endianness, except
824 /// for ppcf128, where the Hi part always comes first.
825 bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
826 return DL.isBigEndian() || VT == MVT::ppcf128;
829 /// If true, the target has custom DAG combine transformations that it can
830 /// perform for the specified node.
831 bool hasTargetDAGCombine(ISD::NodeType NT) const {
832 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
833 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
836 /// \brief Get maximum # of store operations permitted for llvm.memset
838 /// This function returns the maximum number of store operations permitted
839 /// to replace a call to llvm.memset. The value is set by the target at the
840 /// performance threshold for such a replacement. If OptSize is true,
841 /// return the limit for functions that have OptSize attribute.
842 unsigned getMaxStoresPerMemset(bool OptSize) const {
843 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
846 /// \brief Get maximum # of store operations permitted for llvm.memcpy
848 /// This function returns the maximum number of store operations permitted
849 /// to replace a call to llvm.memcpy. The value is set by the target at the
850 /// performance threshold for such a replacement. If OptSize is true,
851 /// return the limit for functions that have OptSize attribute.
852 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
853 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
856 /// \brief Get maximum # of store operations permitted for llvm.memmove
858 /// This function returns the maximum number of store operations permitted
859 /// to replace a call to llvm.memmove. The value is set by the target at the
860 /// performance threshold for such a replacement. If OptSize is true,
861 /// return the limit for functions that have OptSize attribute.
862 unsigned getMaxStoresPerMemmove(bool OptSize) const {
863 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
866 /// \brief Determine if the target supports unaligned memory accesses.
868 /// This function returns true if the target allows unaligned memory accesses
869 /// of the specified type in the given address space. If true, it also returns
870 /// whether the unaligned memory access is "fast" in the last argument by
871 /// reference. This is used, for example, in situations where an array
872 /// copy/move/set is converted to a sequence of store operations. Its use
873 /// helps to ensure that such replacements don't generate code that causes an
874 /// alignment error (trap) on the target machine.
875 virtual bool allowsMisalignedMemoryAccesses(EVT,
876 unsigned AddrSpace = 0,
878 bool * /*Fast*/ = nullptr) const {
882 /// Return true if the target supports a memory access of this type for the
883 /// given address space and alignment. If the access is allowed, the optional
884 /// final parameter returns if the access is also fast (as defined by the
886 bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
887 unsigned AddrSpace = 0, unsigned Alignment = 1,
888 bool *Fast = nullptr) const;
890 /// Returns the target specific optimal type for load and store operations as
891 /// a result of memset, memcpy, and memmove lowering.
893 /// If DstAlign is zero that means it's safe to destination alignment can
894 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
895 /// a need to check it against alignment requirement, probably because the
896 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
897 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
898 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
899 /// does not need to be loaded. It returns EVT::Other if the type should be
900 /// determined using generic target-independent logic.
901 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
902 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
905 bool /*MemcpyStrSrc*/,
906 MachineFunction &/*MF*/) const {
910 /// Returns true if it's safe to use load / store of the specified type to
911 /// expand memcpy / memset inline.
913 /// This is mostly true for all types except for some special cases. For
914 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
915 /// fstpl which also does type conversion. Note the specified type doesn't
916 /// have to be legal as the hook is used before type legalization.
917 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
919 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
920 bool usesUnderscoreSetJmp() const {
921 return UseUnderscoreSetJmp;
924 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
925 bool usesUnderscoreLongJmp() const {
926 return UseUnderscoreLongJmp;
929 /// Return integer threshold on number of blocks to use jump tables rather
930 /// than if sequence.
931 int getMinimumJumpTableEntries() const {
932 return MinimumJumpTableEntries;
935 /// If a physical register, this specifies the register that
936 /// llvm.savestack/llvm.restorestack should save and restore.
937 unsigned getStackPointerRegisterToSaveRestore() const {
938 return StackPointerRegisterToSaveRestore;
941 /// If a physical register, this returns the register that receives the
942 /// exception address on entry to a landing pad.
943 unsigned getExceptionPointerRegister() const {
944 return ExceptionPointerRegister;
947 /// If a physical register, this returns the register that receives the
948 /// exception typeid on entry to a landing pad.
949 unsigned getExceptionSelectorRegister() const {
950 return ExceptionSelectorRegister;
953 /// Returns the target's jmp_buf size in bytes (if never set, the default is
955 unsigned getJumpBufSize() const {
959 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
961 unsigned getJumpBufAlignment() const {
962 return JumpBufAlignment;
965 /// Return the minimum stack alignment of an argument.
966 unsigned getMinStackArgumentAlignment() const {
967 return MinStackArgumentAlignment;
970 /// Return the minimum function alignment.
971 unsigned getMinFunctionAlignment() const {
972 return MinFunctionAlignment;
975 /// Return the preferred function alignment.
976 unsigned getPrefFunctionAlignment() const {
977 return PrefFunctionAlignment;
980 /// Return the preferred loop alignment.
981 virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
982 return PrefLoopAlignment;
985 /// Return whether the DAG builder should automatically insert fences and
986 /// reduce ordering for atomics.
987 bool getInsertFencesForAtomic() const {
988 return InsertFencesForAtomic;
991 /// Return true if the target stores stack protector cookies at a fixed offset
992 /// in some non-standard address space, and populates the address space and
993 /// offset as appropriate.
994 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
995 unsigned &/*Offset*/) const {
999 /// Return true if the target stores SafeStack pointer at a fixed offset in
1000 /// some non-standard address space, and populates the address space and
1001 /// offset as appropriate.
1002 virtual bool getSafeStackPointerLocation(unsigned & /*AddressSpace*/,
1003 unsigned & /*Offset*/) const {
1007 /// Returns true if a cast between SrcAS and DestAS is a noop.
1008 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1012 /// Return true if the pointer arguments to CI should be aligned by aligning
1013 /// the object whose address is being passed. If so then MinSize is set to the
1014 /// minimum size the object must be to be aligned and PrefAlign is set to the
1015 /// preferred alignment.
1016 virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1017 unsigned & /*PrefAlign*/) const {
1021 //===--------------------------------------------------------------------===//
1022 /// \name Helpers for TargetTransformInfo implementations
1025 /// Get the ISD node that corresponds to the Instruction class opcode.
1026 int InstructionOpcodeToISD(unsigned Opcode) const;
1028 /// Estimate the cost of type-legalization and the legalized type.
1029 std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1034 //===--------------------------------------------------------------------===//
1035 /// \name Helpers for atomic expansion.
1038 /// Perform a load-linked operation on Addr, returning a "Value *" with the
1039 /// corresponding pointee type. This may entail some non-trivial operations to
1040 /// truncate or reconstruct types that will be illegal in the backend. See
1041 /// ARMISelLowering for an example implementation.
1042 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1043 AtomicOrdering Ord) const {
1044 llvm_unreachable("Load linked unimplemented on this target");
1047 /// Perform a store-conditional operation to Addr. Return the status of the
1048 /// store. This should be 0 if the store succeeded, non-zero otherwise.
1049 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1050 Value *Addr, AtomicOrdering Ord) const {
1051 llvm_unreachable("Store conditional unimplemented on this target");
1054 /// Inserts in the IR a target-specific intrinsic specifying a fence.
1055 /// It is called by AtomicExpandPass before expanding an
1056 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad.
1057 /// RMW and CmpXchg set both IsStore and IsLoad to true.
1058 /// This function should either return a nullptr, or a pointer to an IR-level
1059 /// Instruction*. Even complex fence sequences can be represented by a
1060 /// single Instruction* through an intrinsic to be lowered later.
1061 /// Backends with !getInsertFencesForAtomic() should keep a no-op here.
1062 /// Backends should override this method to produce target-specific intrinsic
1063 /// for their fences.
1064 /// FIXME: Please note that the default implementation here in terms of
1065 /// IR-level fences exists for historical/compatibility reasons and is
1066 /// *unsound* ! Fences cannot, in general, be used to restore sequential
1067 /// consistency. For example, consider the following example:
1068 /// atomic<int> x = y = 0;
1069 /// int r1, r2, r3, r4;
1080 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1081 /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1082 /// IR-level fences can prevent it.
1084 virtual Instruction *emitLeadingFence(IRBuilder<> &Builder,
1085 AtomicOrdering Ord, bool IsStore,
1086 bool IsLoad) const {
1087 if (!getInsertFencesForAtomic())
1090 if (isAtLeastRelease(Ord) && IsStore)
1091 return Builder.CreateFence(Ord);
1096 virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
1097 AtomicOrdering Ord, bool IsStore,
1098 bool IsLoad) const {
1099 if (!getInsertFencesForAtomic())
1102 if (isAtLeastAcquire(Ord))
1103 return Builder.CreateFence(Ord);
1109 // Emits code that executes when the comparison result in the ll/sc
1110 // expansion of a cmpxchg instruction is such that the store-conditional will
1111 // not execute. This makes it possible to balance out the load-linked with
1112 // a dedicated instruction, if desired.
1113 // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1114 // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1115 virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1117 /// Returns true if the given (atomic) store should be expanded by the
1118 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1119 virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1123 /// Returns true if arguments should be sign-extended in lib calls.
1124 virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1128 /// Returns how the given (atomic) load should be expanded by the
1129 /// IR-level AtomicExpand pass.
1130 virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const {
1131 return AtomicExpansionKind::None;
1134 /// Returns true if the given atomic cmpxchg should be expanded by the
1135 /// IR-level AtomicExpand pass into a load-linked/store-conditional sequence
1136 /// (through emitLoadLinked() and emitStoreConditional()).
1137 virtual bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
1141 /// Returns how the IR-level AtomicExpand pass should expand the given
1142 /// AtomicRMW, if at all. Default is to never expand.
1143 virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
1144 return AtomicExpansionKind::None;
1147 /// On some platforms, an AtomicRMW that never actually modifies the value
1148 /// (such as fetch_add of 0) can be turned into a fence followed by an
1149 /// atomic load. This may sound useless, but it makes it possible for the
1150 /// processor to keep the cacheline shared, dramatically improving
1151 /// performance. And such idempotent RMWs are useful for implementing some
1152 /// kinds of locks, see for example (justification + benchmarks):
1153 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1154 /// This method tries doing that transformation, returning the atomic load if
1155 /// it succeeds, and nullptr otherwise.
1156 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1157 /// another round of expansion.
1159 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1163 /// Returns true if we should normalize
1164 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1165 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1166 /// that it saves us from materializing N0 and N1 in an integer register.
1167 /// Targets that are able to perform and/or on flags should return false here.
1168 virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1170 // If a target has multiple condition registers, then it likely has logical
1171 // operations on those registers.
1172 if (hasMultipleConditionRegisters())
1174 // Only do the transform if the value won't be split into multiple
1176 LegalizeTypeAction Action = getTypeAction(Context, VT);
1177 return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1178 Action != TypeSplitVector;
1181 //===--------------------------------------------------------------------===//
1182 // TargetLowering Configuration Methods - These methods should be invoked by
1183 // the derived class constructor to configure this object for the target.
1186 /// Specify how the target extends the result of integer and floating point
1187 /// boolean values from i1 to a wider type. See getBooleanContents.
1188 void setBooleanContents(BooleanContent Ty) {
1189 BooleanContents = Ty;
1190 BooleanFloatContents = Ty;
1193 /// Specify how the target extends the result of integer and floating point
1194 /// boolean values from i1 to a wider type. See getBooleanContents.
1195 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1196 BooleanContents = IntTy;
1197 BooleanFloatContents = FloatTy;
1200 /// Specify how the target extends the result of a vector boolean value from a
1201 /// vector of i1 to a wider type. See getBooleanContents.
1202 void setBooleanVectorContents(BooleanContent Ty) {
1203 BooleanVectorContents = Ty;
1206 /// Specify the target scheduling preference.
1207 void setSchedulingPreference(Sched::Preference Pref) {
1208 SchedPreferenceInfo = Pref;
1211 /// Indicate whether this target prefers to use _setjmp to implement
1212 /// llvm.setjmp or the version without _. Defaults to false.
1213 void setUseUnderscoreSetJmp(bool Val) {
1214 UseUnderscoreSetJmp = Val;
1217 /// Indicate whether this target prefers to use _longjmp to implement
1218 /// llvm.longjmp or the version without _. Defaults to false.
1219 void setUseUnderscoreLongJmp(bool Val) {
1220 UseUnderscoreLongJmp = Val;
1223 /// Indicate the number of blocks to generate jump tables rather than if
1225 void setMinimumJumpTableEntries(int Val) {
1226 MinimumJumpTableEntries = Val;
1229 /// If set to a physical register, this specifies the register that
1230 /// llvm.savestack/llvm.restorestack should save and restore.
1231 void setStackPointerRegisterToSaveRestore(unsigned R) {
1232 StackPointerRegisterToSaveRestore = R;
1235 /// If set to a physical register, this sets the register that receives the
1236 /// exception address on entry to a landing pad.
1237 void setExceptionPointerRegister(unsigned R) {
1238 ExceptionPointerRegister = R;
1241 /// If set to a physical register, this sets the register that receives the
1242 /// exception typeid on entry to a landing pad.
1243 void setExceptionSelectorRegister(unsigned R) {
1244 ExceptionSelectorRegister = R;
1247 /// Tells the code generator not to expand operations into sequences that use
1248 /// the select operations if possible.
1249 void setSelectIsExpensive(bool isExpensive = true) {
1250 SelectIsExpensive = isExpensive;
1253 /// Tells the code generator that the target has multiple (allocatable)
1254 /// condition registers that can be used to store the results of comparisons
1255 /// for use by selects and conditional branches. With multiple condition
1256 /// registers, the code generator will not aggressively sink comparisons into
1257 /// the blocks of their users.
1258 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1259 HasMultipleConditionRegisters = hasManyRegs;
1262 /// Tells the code generator that the target has BitExtract instructions.
1263 /// The code generator will aggressively sink "shift"s into the blocks of
1264 /// their users if the users will generate "and" instructions which can be
1265 /// combined with "shift" to BitExtract instructions.
1266 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1267 HasExtractBitsInsn = hasExtractInsn;
1270 /// Tells the code generator not to expand logic operations on comparison
1271 /// predicates into separate sequences that increase the amount of flow
1273 void setJumpIsExpensive(bool isExpensive = true);
1275 /// Tells the code generator that fsqrt is cheap, and should not be replaced
1276 /// with an alternative sequence of instructions.
1277 void setFsqrtIsCheap(bool isCheap = true) { FsqrtIsCheap = isCheap; }
1279 /// Tells the code generator that this target supports floating point
1280 /// exceptions and cares about preserving floating point exception behavior.
1281 void setHasFloatingPointExceptions(bool FPExceptions = true) {
1282 HasFloatingPointExceptions = FPExceptions;
1285 /// Tells the code generator which bitwidths to bypass.
1286 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1287 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1290 /// Add the specified register class as an available regclass for the
1291 /// specified value type. This indicates the selector can handle values of
1292 /// that class natively.
1293 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1294 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1295 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1296 RegClassForVT[VT.SimpleTy] = RC;
1299 /// Remove all register classes.
1300 void clearRegisterClasses() {
1301 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1303 AvailableRegClasses.clear();
1306 /// \brief Remove all operation actions.
1307 void clearOperationActions() {
1310 /// Return the largest legal super-reg register class of the register class
1311 /// for the specified type and its associated "cost".
1312 virtual std::pair<const TargetRegisterClass *, uint8_t>
1313 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1315 /// Once all of the register classes are added, this allows us to compute
1316 /// derived properties we expose.
1317 void computeRegisterProperties(const TargetRegisterInfo *TRI);
1319 /// Indicate that the specified operation does not work with the specified
1320 /// type and indicate what to do about it.
1321 void setOperationAction(unsigned Op, MVT VT,
1322 LegalizeAction Action) {
1323 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1324 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1327 /// Indicate that the specified load with extension does not work with the
1328 /// specified type and indicate what to do about it.
1329 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1330 LegalizeAction Action) {
1331 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1332 MemVT.isValid() && "Table isn't big enough!");
1333 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy][ExtType] = (uint8_t)Action;
1336 /// Indicate that the specified truncating store does not work with the
1337 /// specified type and indicate what to do about it.
1338 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1339 LegalizeAction Action) {
1340 assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1341 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1344 /// Indicate that the specified indexed load does or does not work with the
1345 /// specified type and indicate what to do abort it.
1347 /// NOTE: All indexed mode loads are initialized to Expand in
1348 /// TargetLowering.cpp
1349 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1350 LegalizeAction Action) {
1351 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1352 (unsigned)Action < 0xf && "Table isn't big enough!");
1353 // Load action are kept in the upper half.
1354 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1355 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1358 /// Indicate that the specified indexed store does or does not work with the
1359 /// specified type and indicate what to do about it.
1361 /// NOTE: All indexed mode stores are initialized to Expand in
1362 /// TargetLowering.cpp
1363 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1364 LegalizeAction Action) {
1365 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1366 (unsigned)Action < 0xf && "Table isn't big enough!");
1367 // Store action are kept in the lower half.
1368 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1369 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1372 /// Indicate that the specified condition code is or isn't supported on the
1373 /// target and indicate what to do about it.
1374 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1375 LegalizeAction Action) {
1376 assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1377 "Table isn't big enough!");
1378 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1379 /// value and the upper 27 bits index into the second dimension of the array
1380 /// to select what 32-bit value to use.
1381 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1382 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1383 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1386 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1387 /// to trying a larger integer/fp until it can find one that works. If that
1388 /// default is insufficient, this method can be used by the target to override
1390 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1391 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1394 /// Targets should invoke this method for each target independent node that
1395 /// they want to provide a custom DAG combiner for by implementing the
1396 /// PerformDAGCombine virtual method.
1397 void setTargetDAGCombine(ISD::NodeType NT) {
1398 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1399 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1402 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1403 void setJumpBufSize(unsigned Size) {
1407 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1409 void setJumpBufAlignment(unsigned Align) {
1410 JumpBufAlignment = Align;
1413 /// Set the target's minimum function alignment (in log2(bytes))
1414 void setMinFunctionAlignment(unsigned Align) {
1415 MinFunctionAlignment = Align;
1418 /// Set the target's preferred function alignment. This should be set if
1419 /// there is a performance benefit to higher-than-minimum alignment (in
1421 void setPrefFunctionAlignment(unsigned Align) {
1422 PrefFunctionAlignment = Align;
1425 /// Set the target's preferred loop alignment. Default alignment is zero, it
1426 /// means the target does not care about loop alignment. The alignment is
1427 /// specified in log2(bytes). The target may also override
1428 /// getPrefLoopAlignment to provide per-loop values.
1429 void setPrefLoopAlignment(unsigned Align) {
1430 PrefLoopAlignment = Align;
1433 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1434 void setMinStackArgumentAlignment(unsigned Align) {
1435 MinStackArgumentAlignment = Align;
1438 /// Set if the DAG builder should automatically insert fences and reduce the
1439 /// order of atomic memory operations to Monotonic.
1440 void setInsertFencesForAtomic(bool fence) {
1441 InsertFencesForAtomic = fence;
1445 //===--------------------------------------------------------------------===//
1446 // Addressing mode description hooks (used by LSR etc).
1449 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1450 /// instructions reading the address. This allows as much computation as
1451 /// possible to be done in the address mode for that operand. This hook lets
1452 /// targets also pass back when this should be done on intrinsics which
1454 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1455 SmallVectorImpl<Value*> &/*Ops*/,
1456 Type *&/*AccessTy*/,
1457 unsigned AddrSpace = 0) const {
1461 /// This represents an addressing mode of:
1462 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1463 /// If BaseGV is null, there is no BaseGV.
1464 /// If BaseOffs is zero, there is no base offset.
1465 /// If HasBaseReg is false, there is no base register.
1466 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1469 GlobalValue *BaseGV;
1473 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1476 /// Return true if the addressing mode represented by AM is legal for this
1477 /// target, for a load/store of the specified type.
1479 /// The type may be VoidTy, in which case only return true if the addressing
1480 /// mode is legal for a load/store of any legal type. TODO: Handle
1481 /// pre/postinc as well.
1483 /// If the address space cannot be determined, it will be -1.
1485 /// TODO: Remove default argument
1486 virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1487 Type *Ty, unsigned AddrSpace) const;
1489 /// \brief Return the cost of the scaling factor used in the addressing mode
1490 /// represented by AM for this target, for a load/store of the specified type.
1492 /// If the AM is supported, the return value must be >= 0.
1493 /// If the AM is not supported, it returns a negative value.
1494 /// TODO: Handle pre/postinc as well.
1495 /// TODO: Remove default argument
1496 virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
1497 Type *Ty, unsigned AS = 0) const {
1498 // Default: assume that any scaling factor used in a legal AM is free.
1499 if (isLegalAddressingMode(DL, AM, Ty, AS))
1504 /// Return true if the specified immediate is legal icmp immediate, that is
1505 /// the target has icmp instructions which can compare a register against the
1506 /// immediate without having to materialize the immediate into a register.
1507 virtual bool isLegalICmpImmediate(int64_t) const {
1511 /// Return true if the specified immediate is legal add immediate, that is the
1512 /// target has add instructions which can add a register with the immediate
1513 /// without having to materialize the immediate into a register.
1514 virtual bool isLegalAddImmediate(int64_t) const {
1518 /// Return true if it's significantly cheaper to shift a vector by a uniform
1519 /// scalar than by an amount which will vary across each lane. On x86, for
1520 /// example, there is a "psllw" instruction for the former case, but no simple
1521 /// instruction for a general "a << b" operation on vectors.
1522 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1526 /// Return true if it's free to truncate a value of type FromTy to type
1527 /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1528 /// by referencing its sub-register AX.
1529 /// Targets must return false when FromTy <= ToTy.
1530 virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
1534 /// Return true if a truncation from FromTy to ToTy is permitted when deciding
1535 /// whether a call is in tail position. Typically this means that both results
1536 /// would be assigned to the same register or stack slot, but it could mean
1537 /// the target performs adequate checks of its own before proceeding with the
1538 /// tail call. Targets must return false when FromTy <= ToTy.
1539 virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
1543 virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
1547 virtual bool isProfitableToHoist(Instruction *I) const { return true; }
1549 /// Return true if the extension represented by \p I is free.
1550 /// Unlikely the is[Z|FP]ExtFree family which is based on types,
1551 /// this method can use the context provided by \p I to decide
1552 /// whether or not \p I is free.
1553 /// This method extends the behavior of the is[Z|FP]ExtFree family.
1554 /// In other words, if is[Z|FP]Free returns true, then this method
1555 /// returns true as well. The converse is not true.
1556 /// The target can perform the adequate checks by overriding isExtFreeImpl.
1557 /// \pre \p I must be a sign, zero, or fp extension.
1558 bool isExtFree(const Instruction *I) const {
1559 switch (I->getOpcode()) {
1560 case Instruction::FPExt:
1561 if (isFPExtFree(EVT::getEVT(I->getType())))
1564 case Instruction::ZExt:
1565 if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
1568 case Instruction::SExt:
1571 llvm_unreachable("Instruction is not an extension");
1573 return isExtFreeImpl(I);
1576 /// Return true if any actual instruction that defines a value of type FromTy
1577 /// implicitly zero-extends the value to ToTy in the result register.
1579 /// The function should return true when it is likely that the truncate can
1580 /// be freely folded with an instruction defining a value of FromTy. If
1581 /// the defining instruction is unknown (because you're looking at a
1582 /// function argument, PHI, etc.) then the target may require an
1583 /// explicit truncate, which is not necessarily free, but this function
1584 /// does not deal with those cases.
1585 /// Targets must return false when FromTy >= ToTy.
1586 virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
1590 virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
1594 /// Return true if the target supplies and combines to a paired load
1595 /// two loaded values of type LoadedType next to each other in memory.
1596 /// RequiredAlignment gives the minimal alignment constraints that must be met
1597 /// to be able to select this paired load.
1599 /// This information is *not* used to generate actual paired loads, but it is
1600 /// used to generate a sequence of loads that is easier to combine into a
1602 /// For instance, something like this:
1603 /// a = load i64* addr
1604 /// b = trunc i64 a to i32
1605 /// c = lshr i64 a, 32
1606 /// d = trunc i64 c to i32
1607 /// will be optimized into:
1608 /// b = load i32* addr1
1609 /// d = load i32* addr2
1610 /// Where addr1 = addr2 +/- sizeof(i32).
1612 /// In other words, unless the target performs a post-isel load combining,
1613 /// this information should not be provided because it will generate more
1615 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1616 unsigned & /*RequiredAligment*/) const {
1620 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1621 unsigned & /*RequiredAligment*/) const {
1625 /// \brief Get the maximum supported factor for interleaved memory accesses.
1626 /// Default to be the minimum interleave factor: 2.
1627 virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
1629 /// \brief Lower an interleaved load to target specific intrinsics. Return
1630 /// true on success.
1632 /// \p LI is the vector load instruction.
1633 /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
1634 /// \p Indices is the corresponding indices for each shufflevector.
1635 /// \p Factor is the interleave factor.
1636 virtual bool lowerInterleavedLoad(LoadInst *LI,
1637 ArrayRef<ShuffleVectorInst *> Shuffles,
1638 ArrayRef<unsigned> Indices,
1639 unsigned Factor) const {
1643 /// \brief Lower an interleaved store to target specific intrinsics. Return
1644 /// true on success.
1646 /// \p SI is the vector store instruction.
1647 /// \p SVI is the shufflevector to RE-interleave the stored vector.
1648 /// \p Factor is the interleave factor.
1649 virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
1650 unsigned Factor) const {
1654 /// Return true if zero-extending the specific node Val to type VT2 is free
1655 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1656 /// because it's folded such as X86 zero-extending loads).
1657 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1658 return isZExtFree(Val.getValueType(), VT2);
1661 /// Return true if an fpext operation is free (for instance, because
1662 /// single-precision floating-point numbers are implicitly extended to
1663 /// double-precision).
1664 virtual bool isFPExtFree(EVT VT) const {
1665 assert(VT.isFloatingPoint());
1669 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
1670 /// extend node) is profitable.
1671 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
1673 /// Return true if an fneg operation is free to the point where it is never
1674 /// worthwhile to replace it with a bitwise operation.
1675 virtual bool isFNegFree(EVT VT) const {
1676 assert(VT.isFloatingPoint());
1680 /// Return true if an fabs operation is free to the point where it is never
1681 /// worthwhile to replace it with a bitwise operation.
1682 virtual bool isFAbsFree(EVT VT) const {
1683 assert(VT.isFloatingPoint());
1687 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1688 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1689 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1691 /// NOTE: This may be called before legalization on types for which FMAs are
1692 /// not legal, but should return true if those types will eventually legalize
1693 /// to types that support FMAs. After legalization, it will only be called on
1694 /// types that support FMAs (via Legal or Custom actions)
1695 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1699 /// Return true if it's profitable to narrow operations of type VT1 to
1700 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1702 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1706 /// \brief Return true if it is beneficial to convert a load of a constant to
1707 /// just the constant itself.
1708 /// On some targets it might be more efficient to use a combination of
1709 /// arithmetic instructions to materialize the constant instead of loading it
1710 /// from a constant pool.
1711 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1716 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
1717 /// with this index. This is needed because EXTRACT_SUBVECTOR usually
1718 /// has custom lowering that depends on the index of the first element,
1719 /// and only the target knows which lowering is cheap.
1720 virtual bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const {
1724 // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
1725 // even if the vector itself has multiple uses.
1726 virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
1730 //===--------------------------------------------------------------------===//
1731 // Runtime Library hooks
1734 /// Rename the default libcall routine name for the specified libcall.
1735 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1736 LibcallRoutineNames[Call] = Name;
1739 /// Get the libcall routine name for the specified libcall.
1740 const char *getLibcallName(RTLIB::Libcall Call) const {
1741 return LibcallRoutineNames[Call];
1744 /// Override the default CondCode to be used to test the result of the
1745 /// comparison libcall against zero.
1746 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1747 CmpLibcallCCs[Call] = CC;
1750 /// Get the CondCode that's to be used to test the result of the comparison
1751 /// libcall against zero.
1752 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1753 return CmpLibcallCCs[Call];
1756 /// Set the CallingConv that should be used for the specified libcall.
1757 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1758 LibcallCallingConvs[Call] = CC;
1761 /// Get the CallingConv that should be used for the specified libcall.
1762 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1763 return LibcallCallingConvs[Call];
1767 const TargetMachine &TM;
1769 /// Tells the code generator not to expand operations into sequences that use
1770 /// the select operations if possible.
1771 bool SelectIsExpensive;
1773 /// Tells the code generator that the target has multiple (allocatable)
1774 /// condition registers that can be used to store the results of comparisons
1775 /// for use by selects and conditional branches. With multiple condition
1776 /// registers, the code generator will not aggressively sink comparisons into
1777 /// the blocks of their users.
1778 bool HasMultipleConditionRegisters;
1780 /// Tells the code generator that the target has BitExtract instructions.
1781 /// The code generator will aggressively sink "shift"s into the blocks of
1782 /// their users if the users will generate "and" instructions which can be
1783 /// combined with "shift" to BitExtract instructions.
1784 bool HasExtractBitsInsn;
1786 // Don't expand fsqrt with an approximation based on the inverse sqrt.
1789 /// Tells the code generator to bypass slow divide or remainder
1790 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1791 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1792 /// div/rem when the operands are positive and less than 256.
1793 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1795 /// Tells the code generator that it shouldn't generate extra flow control
1796 /// instructions and should attempt to combine flow control instructions via
1798 bool JumpIsExpensive;
1800 /// Whether the target supports or cares about preserving floating point
1801 /// exception behavior.
1802 bool HasFloatingPointExceptions;
1804 /// This target prefers to use _setjmp to implement llvm.setjmp.
1806 /// Defaults to false.
1807 bool UseUnderscoreSetJmp;
1809 /// This target prefers to use _longjmp to implement llvm.longjmp.
1811 /// Defaults to false.
1812 bool UseUnderscoreLongJmp;
1814 /// Number of blocks threshold to use jump tables.
1815 int MinimumJumpTableEntries;
1817 /// Information about the contents of the high-bits in boolean values held in
1818 /// a type wider than i1. See getBooleanContents.
1819 BooleanContent BooleanContents;
1821 /// Information about the contents of the high-bits in boolean values held in
1822 /// a type wider than i1. See getBooleanContents.
1823 BooleanContent BooleanFloatContents;
1825 /// Information about the contents of the high-bits in boolean vector values
1826 /// when the element type is wider than i1. See getBooleanContents.
1827 BooleanContent BooleanVectorContents;
1829 /// The target scheduling preference: shortest possible total cycles or lowest
1831 Sched::Preference SchedPreferenceInfo;
1833 /// The size, in bytes, of the target's jmp_buf buffers
1834 unsigned JumpBufSize;
1836 /// The alignment, in bytes, of the target's jmp_buf buffers
1837 unsigned JumpBufAlignment;
1839 /// The minimum alignment that any argument on the stack needs to have.
1840 unsigned MinStackArgumentAlignment;
1842 /// The minimum function alignment (used when optimizing for size, and to
1843 /// prevent explicitly provided alignment from leading to incorrect code).
1844 unsigned MinFunctionAlignment;
1846 /// The preferred function alignment (used when alignment unspecified and
1847 /// optimizing for speed).
1848 unsigned PrefFunctionAlignment;
1850 /// The preferred loop alignment.
1851 unsigned PrefLoopAlignment;
1853 /// Whether the DAG builder should automatically insert fences and reduce
1854 /// ordering for atomics. (This will be set for for most architectures with
1855 /// weak memory ordering.)
1856 bool InsertFencesForAtomic;
1858 /// If set to a physical register, this specifies the register that
1859 /// llvm.savestack/llvm.restorestack should save and restore.
1860 unsigned StackPointerRegisterToSaveRestore;
1862 /// If set to a physical register, this specifies the register that receives
1863 /// the exception address on entry to a landing pad.
1864 unsigned ExceptionPointerRegister;
1866 /// If set to a physical register, this specifies the register that receives
1867 /// the exception typeid on entry to a landing pad.
1868 unsigned ExceptionSelectorRegister;
1870 /// This indicates the default register class to use for each ValueType the
1871 /// target supports natively.
1872 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1873 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1874 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1876 /// This indicates the "representative" register class to use for each
1877 /// ValueType the target supports natively. This information is used by the
1878 /// scheduler to track register pressure. By default, the representative
1879 /// register class is the largest legal super-reg register class of the
1880 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1881 /// representative class would be GR32.
1882 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1884 /// This indicates the "cost" of the "representative" register class for each
1885 /// ValueType. The cost is used by the scheduler to approximate register
1887 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1889 /// For any value types we are promoting or expanding, this contains the value
1890 /// type that we are changing to. For Expanded types, this contains one step
1891 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1892 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1893 /// the same type (e.g. i32 -> i32).
1894 MVT TransformToType[MVT::LAST_VALUETYPE];
1896 /// For each operation and each value type, keep a LegalizeAction that
1897 /// indicates how instruction selection should deal with the operation. Most
1898 /// operations are Legal (aka, supported natively by the target), but
1899 /// operations that are not should be described. Note that operations on
1900 /// non-legal value types are not described here.
1901 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1903 /// For each load extension type and each value type, keep a LegalizeAction
1904 /// that indicates how instruction selection should deal with a load of a
1905 /// specific value type and extension type.
1906 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
1907 [ISD::LAST_LOADEXT_TYPE];
1909 /// For each value type pair keep a LegalizeAction that indicates whether a
1910 /// truncating store of a specific value type and truncating type is legal.
1911 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1913 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1914 /// that indicates how instruction selection should deal with the load /
1917 /// The first dimension is the value_type for the reference. The second
1918 /// dimension represents the various modes for load store.
1919 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1921 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1922 /// indicates how instruction selection should deal with the condition code.
1924 /// Because each CC action takes up 2 bits, we need to have the array size be
1925 /// large enough to fit all of the value types. This can be done by rounding
1926 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1927 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1929 ValueTypeActionImpl ValueTypeActions;
1932 LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
1935 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1937 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1938 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1941 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1943 /// For operations that must be promoted to a specific type, this holds the
1944 /// destination type. This map should be sparse, so don't hold it as an
1947 /// Targets add entries to this map with AddPromotedToType(..), clients access
1948 /// this with getTypeToPromoteTo(..).
1949 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1952 /// Stores the name each libcall.
1953 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1955 /// The ISD::CondCode that should be used to test the result of each of the
1956 /// comparison libcall against zero.
1957 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1959 /// Stores the CallingConv that should be used for each libcall.
1960 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1963 /// Return true if the extension represented by \p I is free.
1964 /// \pre \p I is a sign, zero, or fp extension and
1965 /// is[Z|FP]ExtFree of the related types is not true.
1966 virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
1968 /// \brief Specify maximum number of store instructions per memset call.
1970 /// When lowering \@llvm.memset this field specifies the maximum number of
1971 /// store operations that may be substituted for the call to memset. Targets
1972 /// must set this value based on the cost threshold for that target. Targets
1973 /// should assume that the memset will be done using as many of the largest
1974 /// store operations first, followed by smaller ones, if necessary, per
1975 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1976 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1977 /// store. This only applies to setting a constant array of a constant size.
1978 unsigned MaxStoresPerMemset;
1980 /// Maximum number of stores operations that may be substituted for the call
1981 /// to memset, used for functions with OptSize attribute.
1982 unsigned MaxStoresPerMemsetOptSize;
1984 /// \brief Specify maximum bytes of store instructions per memcpy call.
1986 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1987 /// store operations that may be substituted for a call to memcpy. Targets
1988 /// must set this value based on the cost threshold for that target. Targets
1989 /// should assume that the memcpy will be done using as many of the largest
1990 /// store operations first, followed by smaller ones, if necessary, per
1991 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1992 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1993 /// and one 1-byte store. This only applies to copying a constant array of
1995 unsigned MaxStoresPerMemcpy;
1997 /// Maximum number of store operations that may be substituted for a call to
1998 /// memcpy, used for functions with OptSize attribute.
1999 unsigned MaxStoresPerMemcpyOptSize;
2001 /// \brief Specify maximum bytes of store instructions per memmove call.
2003 /// When lowering \@llvm.memmove this field specifies the maximum number of
2004 /// store instructions that may be substituted for a call to memmove. Targets
2005 /// must set this value based on the cost threshold for that target. Targets
2006 /// should assume that the memmove will be done using as many of the largest
2007 /// store operations first, followed by smaller ones, if necessary, per
2008 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2009 /// with 8-bit alignment would result in nine 1-byte stores. This only
2010 /// applies to copying a constant array of constant size.
2011 unsigned MaxStoresPerMemmove;
2013 /// Maximum number of store instructions that may be substituted for a call to
2014 /// memmove, used for functions with OptSize attribute.
2015 unsigned MaxStoresPerMemmoveOptSize;
2017 /// Tells the code generator that select is more expensive than a branch if
2018 /// the branch is usually predicted right.
2019 bool PredictableSelectIsExpensive;
2021 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
2022 /// a mask of a single bit, a compare, and a branch into a single instruction.
2023 bool MaskAndBranchFoldingIsLegal;
2025 /// \see enableExtLdPromotion.
2026 bool EnableExtLdPromotion;
2029 /// Return true if the value types that can be represented by the specified
2030 /// register class are all legal.
2031 bool isLegalRC(const TargetRegisterClass *RC) const;
2033 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2034 /// sequence of memory operands that is recognized by PrologEpilogInserter.
2035 MachineBasicBlock *emitPatchPoint(MachineInstr *MI,
2036 MachineBasicBlock *MBB) const;
2039 /// This class defines information used to lower LLVM code to legal SelectionDAG
2040 /// operators that the target instruction selector can accept natively.
2042 /// This class also defines callbacks that targets must implement to lower
2043 /// target-specific constructs to SelectionDAG operators.
2044 class TargetLowering : public TargetLoweringBase {
2045 TargetLowering(const TargetLowering&) = delete;
2046 void operator=(const TargetLowering&) = delete;
2049 /// NOTE: The TargetMachine owns TLOF.
2050 explicit TargetLowering(const TargetMachine &TM);
2052 /// Returns true by value, base pointer and offset pointer and addressing mode
2053 /// by reference if the node's address can be legally represented as
2054 /// pre-indexed load / store address.
2055 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2056 SDValue &/*Offset*/,
2057 ISD::MemIndexedMode &/*AM*/,
2058 SelectionDAG &/*DAG*/) const {
2062 /// Returns true by value, base pointer and offset pointer and addressing mode
2063 /// by reference if this node can be combined with a load / store to form a
2064 /// post-indexed load / store.
2065 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2067 SDValue &/*Offset*/,
2068 ISD::MemIndexedMode &/*AM*/,
2069 SelectionDAG &/*DAG*/) const {
2073 /// Return the entry encoding for a jump table in the current function. The
2074 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2075 virtual unsigned getJumpTableEncoding() const;
2077 virtual const MCExpr *
2078 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2079 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2080 MCContext &/*Ctx*/) const {
2081 llvm_unreachable("Need to implement this hook if target has custom JTIs");
2084 /// Returns relocation base for the given PIC jumptable.
2085 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2086 SelectionDAG &DAG) const;
2088 /// This returns the relocation base for the given PIC jumptable, the same as
2089 /// getPICJumpTableRelocBase, but as an MCExpr.
2090 virtual const MCExpr *
2091 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2092 unsigned JTI, MCContext &Ctx) const;
2094 /// Return true if folding a constant offset with the given GlobalAddress is
2095 /// legal. It is frequently not legal in PIC relocation models.
2096 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2098 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2099 SDValue &Chain) const;
2101 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
2102 SDValue &NewLHS, SDValue &NewRHS,
2103 ISD::CondCode &CCCode, SDLoc DL) const;
2105 /// Returns a pair of (return value, chain).
2106 /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2107 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2108 EVT RetVT, const SDValue *Ops,
2109 unsigned NumOps, bool isSigned,
2110 SDLoc dl, bool doesNotReturn = false,
2111 bool isReturnValueUsed = true) const;
2113 //===--------------------------------------------------------------------===//
2114 // TargetLowering Optimization Methods
2117 /// A convenience struct that encapsulates a DAG, and two SDValues for
2118 /// returning information from TargetLowering to its clients that want to
2120 struct TargetLoweringOpt {
2127 explicit TargetLoweringOpt(SelectionDAG &InDAG,
2129 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2131 bool LegalTypes() const { return LegalTys; }
2132 bool LegalOperations() const { return LegalOps; }
2134 bool CombineTo(SDValue O, SDValue N) {
2140 /// Check to see if the specified operand of the specified instruction is a
2141 /// constant integer. If so, check to see if there are any bits set in the
2142 /// constant that are not demanded. If so, shrink the constant and return
2144 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
2146 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2147 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2148 /// generalized for targets with other types of implicit widening casts.
2149 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2153 /// Look at Op. At this point, we know that only the DemandedMask bits of the
2154 /// result of Op are ever used downstream. If we can use this information to
2155 /// simplify Op, create a new simplified DAG node and return true, returning
2156 /// the original and new nodes in Old and New. Otherwise, analyze the
2157 /// expression and return a mask of KnownOne and KnownZero bits for the
2158 /// expression (used to simplify the caller). The KnownZero/One bits may only
2159 /// be accurate for those bits in the DemandedMask.
2160 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2161 APInt &KnownZero, APInt &KnownOne,
2162 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2164 /// Determine which of the bits specified in Mask are known to be either zero
2165 /// or one and return them in the KnownZero/KnownOne bitsets.
2166 virtual void computeKnownBitsForTargetNode(const SDValue Op,
2169 const SelectionDAG &DAG,
2170 unsigned Depth = 0) const;
2172 /// This method can be implemented by targets that want to expose additional
2173 /// information about sign bits to the DAG Combiner.
2174 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2175 const SelectionDAG &DAG,
2176 unsigned Depth = 0) const;
2178 struct DAGCombinerInfo {
2179 void *DC; // The DAG Combiner object.
2181 bool CalledByLegalizer;
2185 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2186 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2188 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2189 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2190 bool isAfterLegalizeVectorOps() const {
2191 return Level == AfterLegalizeDAG;
2193 CombineLevel getDAGCombineLevel() { return Level; }
2194 bool isCalledByLegalizer() const { return CalledByLegalizer; }
2196 void AddToWorklist(SDNode *N);
2197 void RemoveFromWorklist(SDNode *N);
2198 SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2199 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2200 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2202 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2205 /// Return if the N is a constant or constant vector equal to the true value
2206 /// from getBooleanContents().
2207 bool isConstTrueVal(const SDNode *N) const;
2209 /// Return if the N is a constant or constant vector equal to the false value
2210 /// from getBooleanContents().
2211 bool isConstFalseVal(const SDNode *N) const;
2213 /// Try to simplify a setcc built with the specified operands and cc. If it is
2214 /// unable to simplify it, return a null SDValue.
2215 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2216 ISD::CondCode Cond, bool foldBooleans,
2217 DAGCombinerInfo &DCI, SDLoc dl) const;
2219 /// Returns true (and the GlobalValue and the offset) if the node is a
2220 /// GlobalAddress + offset.
2222 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2224 /// This method will be invoked for all target nodes and for any
2225 /// target-independent nodes that the target has registered with invoke it
2228 /// The semantics are as follows:
2230 /// SDValue.Val == 0 - No change was made
2231 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2232 /// otherwise - N should be replaced by the returned Operand.
2234 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2235 /// more complex transformations.
2237 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2239 /// Return true if it is profitable to move a following shift through this
2240 // node, adjusting any immediate operands as necessary to preserve semantics.
2241 // This transformation may not be desirable if it disrupts a particularly
2242 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2243 // By default, it returns true.
2244 virtual bool isDesirableToCommuteWithShift(const SDNode *N /*Op*/) const {
2248 /// Return true if the target has native support for the specified value type
2249 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2250 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2251 /// and some i16 instructions are slow.
2252 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2253 // By default, assume all legal types are desirable.
2254 return isTypeLegal(VT);
2257 /// Return true if it is profitable for dag combiner to transform a floating
2258 /// point op of specified opcode to a equivalent op of an integer
2259 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2260 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2265 /// This method query the target whether it is beneficial for dag combiner to
2266 /// promote the specified node. If true, it should return the desired
2267 /// promotion type by reference.
2268 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2272 //===--------------------------------------------------------------------===//
2273 // Lowering methods - These methods must be implemented by targets so that
2274 // the SelectionDAGBuilder code knows how to lower these.
2277 /// This hook must be implemented to lower the incoming (formal) arguments,
2278 /// described by the Ins array, into the specified DAG. The implementation
2279 /// should fill in the InVals array with legal-type argument values, and
2280 /// return the resulting token chain value.
2283 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2285 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
2286 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
2287 SmallVectorImpl<SDValue> &/*InVals*/) const {
2288 llvm_unreachable("Not Implemented");
2291 struct ArgListEntry {
2300 bool isInAlloca : 1;
2301 bool isReturned : 1;
2304 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2305 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2306 isReturned(false), Alignment(0) { }
2308 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2310 typedef std::vector<ArgListEntry> ArgListTy;
2312 /// This structure contains all information that is necessary for lowering
2313 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2314 /// needs to lower a call, and targets will see this struct in their LowerCall
2316 struct CallLoweringInfo {
2323 bool DoesNotReturn : 1;
2324 bool IsReturnValueUsed : 1;
2326 // IsTailCall should be modified by implementations of
2327 // TargetLowering::LowerCall that perform tail call conversions.
2330 unsigned NumFixedArgs;
2331 CallingConv::ID CallConv;
2336 ImmutableCallSite *CS;
2338 SmallVector<ISD::OutputArg, 32> Outs;
2339 SmallVector<SDValue, 32> OutVals;
2340 SmallVector<ISD::InputArg, 32> Ins;
2342 CallLoweringInfo(SelectionDAG &DAG)
2343 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
2344 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
2345 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
2346 DAG(DAG), CS(nullptr), IsPatchPoint(false) {}
2348 CallLoweringInfo &setDebugLoc(SDLoc dl) {
2353 CallLoweringInfo &setChain(SDValue InChain) {
2358 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
2359 SDValue Target, ArgListTy &&ArgsList,
2360 unsigned FixedArgs = -1) {
2365 (FixedArgs == static_cast<unsigned>(-1) ? Args.size() : FixedArgs);
2366 Args = std::move(ArgsList);
2370 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
2371 SDValue Target, ArgListTy &&ArgsList,
2372 ImmutableCallSite &Call) {
2375 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
2376 DoesNotReturn = Call.doesNotReturn();
2377 IsVarArg = FTy->isVarArg();
2378 IsReturnValueUsed = !Call.getInstruction()->use_empty();
2379 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
2380 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
2384 CallConv = Call.getCallingConv();
2385 NumFixedArgs = FTy->getNumParams();
2386 Args = std::move(ArgsList);
2393 CallLoweringInfo &setInRegister(bool Value = true) {
2398 CallLoweringInfo &setNoReturn(bool Value = true) {
2399 DoesNotReturn = Value;
2403 CallLoweringInfo &setVarArg(bool Value = true) {
2408 CallLoweringInfo &setTailCall(bool Value = true) {
2413 CallLoweringInfo &setDiscardResult(bool Value = true) {
2414 IsReturnValueUsed = !Value;
2418 CallLoweringInfo &setSExtResult(bool Value = true) {
2423 CallLoweringInfo &setZExtResult(bool Value = true) {
2428 CallLoweringInfo &setIsPatchPoint(bool Value = true) {
2429 IsPatchPoint = Value;
2433 ArgListTy &getArgs() {
2439 /// This function lowers an abstract call to a function into an actual call.
2440 /// This returns a pair of operands. The first element is the return value
2441 /// for the function (if RetTy is not VoidTy). The second element is the
2442 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2443 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2445 /// This hook must be implemented to lower calls into the specified
2446 /// DAG. The outgoing arguments to the call are described by the Outs array,
2447 /// and the values to be returned by the call are described by the Ins
2448 /// array. The implementation should fill in the InVals array with legal-type
2449 /// return values from the call, and return the resulting token chain value.
2451 LowerCall(CallLoweringInfo &/*CLI*/,
2452 SmallVectorImpl<SDValue> &/*InVals*/) const {
2453 llvm_unreachable("Not Implemented");
2456 /// Target-specific cleanup for formal ByVal parameters.
2457 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2459 /// This hook should be implemented to check whether the return values
2460 /// described by the Outs array can fit into the return registers. If false
2461 /// is returned, an sret-demotion is performed.
2462 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2463 MachineFunction &/*MF*/, bool /*isVarArg*/,
2464 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2465 LLVMContext &/*Context*/) const
2467 // Return true by default to get preexisting behavior.
2471 /// This hook must be implemented to lower outgoing return values, described
2472 /// by the Outs array, into the specified DAG. The implementation should
2473 /// return the resulting token chain value.
2475 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2477 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2478 const SmallVectorImpl<SDValue> &/*OutVals*/,
2479 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2480 llvm_unreachable("Not Implemented");
2483 /// Return true if result of the specified node is used by a return node
2484 /// only. It also compute and return the input chain for the tail call.
2486 /// This is used to determine whether it is possible to codegen a libcall as
2487 /// tail call at legalization time.
2488 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2492 /// Return true if the target may be able emit the call instruction as a tail
2493 /// call. This is used by optimization passes to determine if it's profitable
2494 /// to duplicate return instructions to enable tailcall optimization.
2495 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2499 /// Return the builtin name for the __builtin___clear_cache intrinsic
2500 /// Default is to invoke the clear cache library call
2501 virtual const char * getClearCacheBuiltinName() const {
2502 return "__clear_cache";
2505 /// Return the register ID of the name passed in. Used by named register
2506 /// global variables extension. There is no target-independent behaviour
2507 /// so the default action is to bail.
2508 virtual unsigned getRegisterByName(const char* RegName, EVT VT,
2509 SelectionDAG &DAG) const {
2510 report_fatal_error("Named registers not implemented for this target");
2513 /// Return the type that should be used to zero or sign extend a
2514 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2515 /// convention requires the return type to be promoted, but this is not true
2516 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2517 /// calling conventions. The frontend should handle this and include all of
2518 /// the necessary information.
2519 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2520 ISD::NodeType /*ExtendKind*/) const {
2521 EVT MinVT = getRegisterType(Context, MVT::i32);
2522 return VT.bitsLT(MinVT) ? MinVT : VT;
2525 /// For some targets, an LLVM struct type must be broken down into multiple
2526 /// simple types, but the calling convention specifies that the entire struct
2527 /// must be passed in a block of consecutive registers.
2529 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
2530 bool isVarArg) const {
2534 /// Returns a 0 terminated array of registers that can be safely used as
2535 /// scratch registers.
2536 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
2540 /// This callback is used to prepare for a volatile or atomic load.
2541 /// It takes a chain node as input and returns the chain for the load itself.
2543 /// Having a callback like this is necessary for targets like SystemZ,
2544 /// which allows a CPU to reuse the result of a previous load indefinitely,
2545 /// even if a cache-coherent store is performed by another CPU. The default
2546 /// implementation does nothing.
2547 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2548 SelectionDAG &DAG) const {
2552 /// This callback is invoked by the type legalizer to legalize nodes with an
2553 /// illegal operand type but legal result types. It replaces the
2554 /// LowerOperation callback in the type Legalizer. The reason we can not do
2555 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2556 /// use this callback.
2558 /// TODO: Consider merging with ReplaceNodeResults.
2560 /// The target places new result values for the node in Results (their number
2561 /// and types must exactly match those of the original return values of
2562 /// the node), or leaves Results empty, which indicates that the node is not
2563 /// to be custom lowered after all.
2564 /// The default implementation calls LowerOperation.
2565 virtual void LowerOperationWrapper(SDNode *N,
2566 SmallVectorImpl<SDValue> &Results,
2567 SelectionDAG &DAG) const;
2569 /// This callback is invoked for operations that are unsupported by the
2570 /// target, which are registered to use 'custom' lowering, and whose defined
2571 /// values are all legal. If the target has no operations that require custom
2572 /// lowering, it need not implement this. The default implementation of this
2574 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2576 /// This callback is invoked when a node result type is illegal for the
2577 /// target, and the operation was registered to use 'custom' lowering for that
2578 /// result type. The target places new result values for the node in Results
2579 /// (their number and types must exactly match those of the original return
2580 /// values of the node), or leaves Results empty, which indicates that the
2581 /// node is not to be custom lowered after all.
2583 /// If the target has no operations that require custom lowering, it need not
2584 /// implement this. The default implementation aborts.
2585 virtual void ReplaceNodeResults(SDNode * /*N*/,
2586 SmallVectorImpl<SDValue> &/*Results*/,
2587 SelectionDAG &/*DAG*/) const {
2588 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2591 /// This method returns the name of a target specific DAG node.
2592 virtual const char *getTargetNodeName(unsigned Opcode) const;
2594 /// This method returns a target specific FastISel object, or null if the
2595 /// target does not support "fast" ISel.
2596 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2597 const TargetLibraryInfo *) const {
2602 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2603 SelectionDAG &DAG) const;
2605 //===--------------------------------------------------------------------===//
2606 // Inline Asm Support hooks
2609 /// This hook allows the target to expand an inline asm call to be explicit
2610 /// llvm code if it wants to. This is useful for turning simple inline asms
2611 /// into LLVM intrinsics, which gives the compiler more information about the
2612 /// behavior of the code.
2613 virtual bool ExpandInlineAsm(CallInst *) const {
2617 enum ConstraintType {
2618 C_Register, // Constraint represents specific register(s).
2619 C_RegisterClass, // Constraint represents any of register(s) in class.
2620 C_Memory, // Memory constraint.
2621 C_Other, // Something else.
2622 C_Unknown // Unsupported constraint.
2625 enum ConstraintWeight {
2627 CW_Invalid = -1, // No match.
2628 CW_Okay = 0, // Acceptable.
2629 CW_Good = 1, // Good weight.
2630 CW_Better = 2, // Better weight.
2631 CW_Best = 3, // Best weight.
2633 // Well-known weights.
2634 CW_SpecificReg = CW_Okay, // Specific register operands.
2635 CW_Register = CW_Good, // Register operands.
2636 CW_Memory = CW_Better, // Memory operands.
2637 CW_Constant = CW_Best, // Constant operand.
2638 CW_Default = CW_Okay // Default or don't know type.
2641 /// This contains information for each constraint that we are lowering.
2642 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2643 /// This contains the actual string for the code, like "m". TargetLowering
2644 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2645 /// matches the operand.
2646 std::string ConstraintCode;
2648 /// Information about the constraint code, e.g. Register, RegisterClass,
2649 /// Memory, Other, Unknown.
2650 TargetLowering::ConstraintType ConstraintType;
2652 /// If this is the result output operand or a clobber, this is null,
2653 /// otherwise it is the incoming operand to the CallInst. This gets
2654 /// modified as the asm is processed.
2655 Value *CallOperandVal;
2657 /// The ValueType for the operand value.
2660 /// Return true of this is an input operand that is a matching constraint
2662 bool isMatchingInputConstraint() const;
2664 /// If this is an input matching constraint, this method returns the output
2665 /// operand it matches.
2666 unsigned getMatchedOperand() const;
2668 /// Copy constructor for copying from a ConstraintInfo.
2669 AsmOperandInfo(InlineAsm::ConstraintInfo Info)
2670 : InlineAsm::ConstraintInfo(std::move(Info)),
2671 ConstraintType(TargetLowering::C_Unknown), CallOperandVal(nullptr),
2672 ConstraintVT(MVT::Other) {}
2675 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2677 /// Split up the constraint string from the inline assembly value into the
2678 /// specific constraints and their prefixes, and also tie in the associated
2679 /// operand values. If this returns an empty vector, and if the constraint
2680 /// string itself isn't empty, there was an error parsing.
2681 virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
2682 const TargetRegisterInfo *TRI,
2683 ImmutableCallSite CS) const;
2685 /// Examine constraint type and operand type and determine a weight value.
2686 /// The operand object must already have been set up with the operand type.
2687 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2688 AsmOperandInfo &info, int maIndex) const;
2690 /// Examine constraint string and operand type and determine a weight value.
2691 /// The operand object must already have been set up with the operand type.
2692 virtual ConstraintWeight getSingleConstraintMatchWeight(
2693 AsmOperandInfo &info, const char *constraint) const;
2695 /// Determines the constraint code and constraint type to use for the specific
2696 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2697 /// If the actual operand being passed in is available, it can be passed in as
2698 /// Op, otherwise an empty SDValue can be passed.
2699 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2701 SelectionDAG *DAG = nullptr) const;
2703 /// Given a constraint, return the type of constraint it is for this target.
2704 virtual ConstraintType getConstraintType(StringRef Constraint) const;
2706 /// Given a physical register constraint (e.g. {edx}), return the register
2707 /// number and the register class for the register.
2709 /// Given a register class constraint, like 'r', if this corresponds directly
2710 /// to an LLVM register class, return a register of 0 and the register class
2713 /// This should only be used for C_Register constraints. On error, this
2714 /// returns a register number of 0 and a null register class pointer.
2715 virtual std::pair<unsigned, const TargetRegisterClass *>
2716 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2717 StringRef Constraint, MVT VT) const;
2719 virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
2720 if (ConstraintCode == "i")
2721 return InlineAsm::Constraint_i;
2722 else if (ConstraintCode == "m")
2723 return InlineAsm::Constraint_m;
2724 return InlineAsm::Constraint_Unknown;
2727 /// Try to replace an X constraint, which matches anything, with another that
2728 /// has more specific requirements based on the type of the corresponding
2729 /// operand. This returns null if there is no replacement to make.
2730 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2732 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2733 /// add anything to Ops.
2734 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2735 std::vector<SDValue> &Ops,
2736 SelectionDAG &DAG) const;
2738 //===--------------------------------------------------------------------===//
2739 // Div utility functions
2741 SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2742 bool IsAfterLegalization,
2743 std::vector<SDNode *> *Created) const;
2744 SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2745 bool IsAfterLegalization,
2746 std::vector<SDNode *> *Created) const;
2748 /// Targets may override this function to provide custom SDIV lowering for
2749 /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
2750 /// assumes SDIV is expensive and replaces it with a series of other integer
2752 virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
2754 std::vector<SDNode *> *Created) const;
2756 /// Indicate whether this target prefers to combine FDIVs with the same
2757 /// divisor. If the transform should never be done, return zero. If the
2758 /// transform should be done, return the minimum number of divisor uses
2759 /// that must exist.
2760 virtual unsigned combineRepeatedFPDivisors() const {
2764 /// Hooks for building estimates in place of slower divisions and square
2767 /// Return a reciprocal square root estimate value for the input operand.
2768 /// The RefinementSteps output is the number of Newton-Raphson refinement
2769 /// iterations required to generate a sufficient (though not necessarily
2770 /// IEEE-754 compliant) estimate for the value type.
2771 /// The boolean UseOneConstNR output is used to select a Newton-Raphson
2772 /// algorithm implementation that uses one constant or two constants.
2773 /// A target may choose to implement its own refinement within this function.
2774 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2775 /// any further refinement of the estimate.
2776 /// An empty SDValue return means no estimate sequence can be created.
2777 virtual SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
2778 unsigned &RefinementSteps,
2779 bool &UseOneConstNR) const {
2783 /// Return a reciprocal estimate value for the input operand.
2784 /// The RefinementSteps output is the number of Newton-Raphson refinement
2785 /// iterations required to generate a sufficient (though not necessarily
2786 /// IEEE-754 compliant) estimate for the value type.
2787 /// A target may choose to implement its own refinement within this function.
2788 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2789 /// any further refinement of the estimate.
2790 /// An empty SDValue return means no estimate sequence can be created.
2791 virtual SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
2792 unsigned &RefinementSteps) const {
2796 //===--------------------------------------------------------------------===//
2797 // Legalization utility functions
2800 /// Expand a MUL into two nodes. One that computes the high bits of
2801 /// the result and one that computes the low bits.
2802 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
2803 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
2804 /// if you want to control how low bits are extracted from the LHS.
2805 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
2806 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
2807 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
2808 /// \returns true if the node has been expanded. false if it has not
2809 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2810 SelectionDAG &DAG, SDValue LL = SDValue(),
2811 SDValue LH = SDValue(), SDValue RL = SDValue(),
2812 SDValue RH = SDValue()) const;
2814 /// Expand float(f32) to SINT(i64) conversion
2815 /// \param N Node to expand
2816 /// \param Result output after conversion
2817 /// \returns True, if the expansion was successful, false otherwise
2818 bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
2820 //===--------------------------------------------------------------------===//
2821 // Instruction Emitting Hooks
2824 /// This method should be implemented by targets that mark instructions with
2825 /// the 'usesCustomInserter' flag. These instructions are special in various
2826 /// ways, which require special support to insert. The specified MachineInstr
2827 /// is created but not inserted into any basic blocks, and this method is
2828 /// called to expand it into a sequence of instructions, potentially also
2829 /// creating new basic blocks and control flow.
2830 /// As long as the returned basic block is different (i.e., we created a new
2831 /// one), the custom inserter is free to modify the rest of \p MBB.
2832 virtual MachineBasicBlock *
2833 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2835 /// This method should be implemented by targets that mark instructions with
2836 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2837 /// instruction selection by target hooks. e.g. To fill in optional defs for
2838 /// ARM 's' setting instructions.
2840 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2842 /// If this function returns true, SelectionDAGBuilder emits a
2843 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
2844 virtual bool useLoadStackGuardNode() const {
2848 /// Lower TLS global address SDNode for target independent emulated TLS model.
2849 virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
2850 SelectionDAG &DAG) const;
2853 /// Given an LLVM IR type and return type attributes, compute the return value
2854 /// EVTs and flags, and optionally also the offsets, if the return value is
2855 /// being lowered to memory.
2856 void GetReturnInfo(Type *ReturnType, AttributeSet attr,
2857 SmallVectorImpl<ISD::OutputArg> &Outs,
2858 const TargetLowering &TLI, const DataLayout &DL);
2860 } // end llvm namespace