1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/Target/TargetCallingConv.h"
35 #include "llvm/Target/TargetMachine.h"
44 class FunctionLoweringInfo;
45 class ImmutableCallSite;
47 class MachineBasicBlock;
48 class MachineFunction;
50 class MachineJumpTableInfo;
55 template<typename T> class SmallVectorImpl;
57 class TargetRegisterClass;
58 class TargetLibraryInfo;
59 class TargetLoweringObjectFile;
64 None, // No preference
65 Source, // Follow source order.
66 RegPressure, // Scheduling for lowest register pressure.
67 Hybrid, // Scheduling for both latency and register pressure.
68 ILP, // Scheduling for ILP in low register pressure mode.
69 VLIW // Scheduling for VLIW targets.
73 /// This base class for TargetLowering contains the SelectionDAG-independent
74 /// parts that can be used from the rest of CodeGen.
75 class TargetLoweringBase {
76 TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
77 void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
80 /// This enum indicates whether operations are valid for a target, and if not,
81 /// what action should be used to make them valid.
83 Legal, // The target natively supports this operation.
84 Promote, // This operation should be executed in a larger type.
85 Expand, // Try to expand this to other ops, otherwise use a libcall.
86 Custom // Use the LowerOperation hook to implement custom lowering.
89 /// This enum indicates whether a types are legal for a target, and if not,
90 /// what action should be used to make them valid.
91 enum LegalizeTypeAction {
92 TypeLegal, // The target natively supports this type.
93 TypePromoteInteger, // Replace this integer with a larger one.
94 TypeExpandInteger, // Split this integer into two of half the size.
95 TypeSoftenFloat, // Convert this float to a same size integer type.
96 TypeExpandFloat, // Split this float into two of half the size.
97 TypeScalarizeVector, // Replace this one-element vector with its element.
98 TypeSplitVector, // Split this vector into two of half the size.
99 TypeWidenVector // This vector should be widened into a larger vector.
102 /// LegalizeKind holds the legalization kind that needs to happen to EVT
103 /// in order to type-legalize it.
104 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
106 /// Enum that describes how the target represents true/false values.
107 enum BooleanContent {
108 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
109 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
110 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
113 /// Enum that describes what type of support for selects the target has.
114 enum SelectSupportKind {
115 ScalarValSelect, // The target supports scalar selects (ex: cmov).
116 ScalarCondVectorVal, // The target supports selects with a scalar condition
117 // and vector values (ex: cmov).
118 VectorMaskSelect // The target supports vector selects with a vector
119 // mask (ex: x86 blends).
122 static ISD::NodeType getExtendForContent(BooleanContent Content) {
124 case UndefinedBooleanContent:
125 // Extend by adding rubbish bits.
126 return ISD::ANY_EXTEND;
127 case ZeroOrOneBooleanContent:
128 // Extend by adding zero bits.
129 return ISD::ZERO_EXTEND;
130 case ZeroOrNegativeOneBooleanContent:
131 // Extend by copying the sign bit.
132 return ISD::SIGN_EXTEND;
134 llvm_unreachable("Invalid content kind");
137 /// NOTE: The constructor takes ownership of TLOF.
138 explicit TargetLoweringBase(const TargetMachine &TM,
139 const TargetLoweringObjectFile *TLOF);
140 virtual ~TargetLoweringBase();
143 /// \brief Initialize all of the actions to default values.
147 const TargetMachine &getTargetMachine() const { return TM; }
148 const DataLayout *getDataLayout() const { return DL; }
149 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
151 bool isBigEndian() const { return !IsLittleEndian; }
152 bool isLittleEndian() const { return IsLittleEndian; }
154 /// Return the pointer type for the given address space, defaults to
155 /// the pointer type from the data layout.
156 /// FIXME: The default needs to be removed once all the code is updated.
157 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const;
158 unsigned getPointerSizeInBits(uint32_t AS = 0) const;
159 unsigned getPointerTypeSizeInBits(Type *Ty) const;
160 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
162 EVT getShiftAmountTy(EVT LHSTy) const;
164 /// Returns the type to be used for the index operand of:
165 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
166 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
167 virtual MVT getVectorIdxTy() const {
168 return getPointerTy();
171 /// Return true if the select operation is expensive for this target.
172 bool isSelectExpensive() const { return SelectIsExpensive; }
174 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
178 /// Return true if multiple condition registers are available.
179 bool hasMultipleConditionRegisters() const {
180 return HasMultipleConditionRegisters;
183 /// Return true if a vector of the given type should be split
184 /// (TypeSplitVector) instead of promoted (TypePromoteInteger) during type
186 virtual bool shouldSplitVectorElementType(EVT /*VT*/) const { return false; }
188 /// Return true if integer divide is usually cheaper than a sequence of
189 /// several shifts, adds, and multiplies for this target.
190 bool isIntDivCheap() const { return IntDivIsCheap; }
192 /// Returns true if target has indicated at least one type should be bypassed.
193 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
195 /// Returns map of slow types for division or remainder with corresponding
197 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
198 return BypassSlowDivWidths;
201 /// Return true if pow2 div is cheaper than a chain of srl/add/sra.
202 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
204 /// Return true if Flow Control is an expensive operation that should be
206 bool isJumpExpensive() const { return JumpIsExpensive; }
208 /// Return true if selects are only cheaper than branches if the branch is
209 /// unlikely to be predicted right.
210 bool isPredictableSelectExpensive() const {
211 return PredictableSelectIsExpensive;
214 /// isLoadBitCastBeneficial() - Return true if the following transform
216 /// fold (conv (load x)) -> (load (conv*)x)
217 /// On architectures that don't natively support some vector loads efficiently,
218 /// casting the load to a smaller vector of larger types and loading
219 /// is more efficient, however, this can be undone by optimizations in
221 virtual bool isLoadBitCastBeneficial(EVT /* Load */, EVT /* Bitcast */) const {
225 /// \brief Return if the target supports combining a
228 /// %andResult = and %val1, #imm-with-one-bit-set;
229 /// %icmpResult = icmp %andResult, 0
230 /// br i1 %icmpResult, label %dest1, label %dest2
232 /// into a single machine instruction of a form like:
234 /// brOnBitSet %register, #bitNumber, dest
236 bool isMaskAndBranchFoldingLegal() const {
237 return MaskAndBranchFoldingIsLegal;
240 /// Return the ValueType of the result of SETCC operations. Also used to
241 /// obtain the target's preferred type for the condition operand of SELECT and
242 /// BRCOND nodes. In the case of BRCOND the argument passed is MVT::Other
243 /// since there are no other operands to get a type hint from.
244 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
246 /// Return the ValueType for comparison libcalls. Comparions libcalls include
247 /// floating point comparion calls, and Ordered/Unordered check calls on
248 /// floating point numbers.
250 MVT::SimpleValueType getCmpLibcallReturnType() const;
252 /// For targets without i1 registers, this gives the nature of the high-bits
253 /// of boolean values held in types wider than i1.
255 /// "Boolean values" are special true/false values produced by nodes like
256 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
257 /// Not to be confused with general values promoted from i1. Some cpus
258 /// distinguish between vectors of boolean and scalars; the isVec parameter
259 /// selects between the two kinds. For example on X86 a scalar boolean should
260 /// be zero extended from i1, while the elements of a vector of booleans
261 /// should be sign extended from i1.
262 BooleanContent getBooleanContents(bool isVec) const {
263 return isVec ? BooleanVectorContents : BooleanContents;
266 /// Return target scheduling preference.
267 Sched::Preference getSchedulingPreference() const {
268 return SchedPreferenceInfo;
271 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
272 /// for different nodes. This function returns the preference (or none) for
274 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
278 /// Return the register class that should be used for the specified value
280 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
281 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
282 assert(RC && "This value type is not natively supported!");
286 /// Return the 'representative' register class for the specified value
289 /// The 'representative' register class is the largest legal super-reg
290 /// register class for the register class of the value type. For example, on
291 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
292 /// register class is GR64 on x86_64.
293 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
294 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
298 /// Return the cost of the 'representative' register class for the specified
300 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
301 return RepRegClassCostForVT[VT.SimpleTy];
304 /// Return true if the target has native support for the specified value type.
305 /// This means that it has a register that directly holds it without
306 /// promotions or expansions.
307 bool isTypeLegal(EVT VT) const {
308 assert(!VT.isSimple() ||
309 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
310 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
313 class ValueTypeActionImpl {
314 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
315 /// that indicates how instruction selection should deal with the type.
316 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
319 ValueTypeActionImpl() {
320 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0);
323 LegalizeTypeAction getTypeAction(MVT VT) const {
324 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
327 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
328 unsigned I = VT.SimpleTy;
329 ValueTypeActions[I] = Action;
333 const ValueTypeActionImpl &getValueTypeActions() const {
334 return ValueTypeActions;
337 /// Return how we should legalize values of this type, either it is already
338 /// legal (return 'Legal') or we need to promote it to a larger type (return
339 /// 'Promote'), or we need to expand it into multiple registers of smaller
340 /// integer type (return 'Expand'). 'Custom' is not an option.
341 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
342 return getTypeConversion(Context, VT).first;
344 LegalizeTypeAction getTypeAction(MVT VT) const {
345 return ValueTypeActions.getTypeAction(VT);
348 /// For types supported by the target, this is an identity function. For
349 /// types that must be promoted to larger types, this returns the larger type
350 /// to promote to. For integer types that are larger than the largest integer
351 /// register, this contains one step in the expansion to get to the smaller
352 /// register. For illegal floating point types, this returns the integer type
354 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
355 return getTypeConversion(Context, VT).second;
358 /// For types supported by the target, this is an identity function. For
359 /// types that must be expanded (i.e. integer types that are larger than the
360 /// largest integer register or illegal floating point types), this returns
361 /// the largest legal type it will be expanded to.
362 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
363 assert(!VT.isVector());
365 switch (getTypeAction(Context, VT)) {
368 case TypeExpandInteger:
369 VT = getTypeToTransformTo(Context, VT);
372 llvm_unreachable("Type is not legal nor is it to be expanded!");
377 /// Vector types are broken down into some number of legal first class types.
378 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
379 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
380 /// turns into 4 EVT::i32 values with both PPC and X86.
382 /// This method returns the number of registers needed, and the VT for each
383 /// register. It also returns the VT and quantity of the intermediate values
384 /// before they are promoted/expanded.
385 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
387 unsigned &NumIntermediates,
388 MVT &RegisterVT) const;
390 struct IntrinsicInfo {
391 unsigned opc; // target opcode
392 EVT memVT; // memory VT
393 const Value* ptrVal; // value representing memory location
394 int offset; // offset off of ptrVal
395 unsigned align; // alignment
396 bool vol; // is volatile?
397 bool readMem; // reads memory?
398 bool writeMem; // writes memory?
401 /// Given an intrinsic, checks if on the target the intrinsic will need to map
402 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
403 /// true and store the intrinsic information into the IntrinsicInfo that was
404 /// passed to the function.
405 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
406 unsigned /*Intrinsic*/) const {
410 /// Returns true if the target can instruction select the specified FP
411 /// immediate natively. If false, the legalizer will materialize the FP
412 /// immediate as a load from a constant pool.
413 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
417 /// Targets can use this to indicate that they only support *some*
418 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
419 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
421 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
426 /// Returns true if the operation can trap for the value type.
428 /// VT must be a legal type. By default, we optimistically assume most
429 /// operations don't trap except for divide and remainder.
430 virtual bool canOpTrap(unsigned Op, EVT VT) const;
432 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
433 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
434 /// a VAND with a constant pool entry.
435 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
440 /// Return how this operation should be treated: either it is legal, needs to
441 /// be promoted to a larger size, needs to be expanded to some other code
442 /// sequence, or the target has a custom expander for it.
443 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
444 if (VT.isExtended()) return Expand;
445 // If a target-specific SDNode requires legalization, require the target
446 // to provide custom legalization for it.
447 if (Op > array_lengthof(OpActions[0])) return Custom;
448 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
449 return (LegalizeAction)OpActions[I][Op];
452 /// Return true if the specified operation is legal on this target or can be
453 /// made legal with custom lowering. This is used to help guide high-level
454 /// lowering decisions.
455 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
456 return (VT == MVT::Other || isTypeLegal(VT)) &&
457 (getOperationAction(Op, VT) == Legal ||
458 getOperationAction(Op, VT) == Custom);
461 /// Return true if the specified operation is legal on this target or can be
462 /// made legal using promotion. This is used to help guide high-level lowering
464 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
465 return (VT == MVT::Other || isTypeLegal(VT)) &&
466 (getOperationAction(Op, VT) == Legal ||
467 getOperationAction(Op, VT) == Promote);
470 /// Return true if the specified operation is illegal on this target or
471 /// unlikely to be made legal with custom lowering. This is used to help guide
472 /// high-level lowering decisions.
473 bool isOperationExpand(unsigned Op, EVT VT) const {
474 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
477 /// Return true if the specified operation is legal on this target.
478 bool isOperationLegal(unsigned Op, EVT VT) const {
479 return (VT == MVT::Other || isTypeLegal(VT)) &&
480 getOperationAction(Op, VT) == Legal;
483 /// Return how this load with extension should be treated: either it is legal,
484 /// needs to be promoted to a larger size, needs to be expanded to some other
485 /// code sequence, or the target has a custom expander for it.
486 LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const {
487 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
488 "Table isn't big enough!");
489 return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType];
492 /// Return true if the specified load with extension is legal on this target.
493 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
494 return VT.isSimple() &&
495 getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
498 /// Return how this store with truncation should be treated: either it is
499 /// legal, needs to be promoted to a larger size, needs to be expanded to some
500 /// other code sequence, or the target has a custom expander for it.
501 LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const {
502 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
503 "Table isn't big enough!");
504 return (LegalizeAction)TruncStoreActions[ValVT.SimpleTy]
508 /// Return true if the specified store with truncation is legal on this
510 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
511 return isTypeLegal(ValVT) && MemVT.isSimple() &&
512 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
515 /// Return how the indexed load should be treated: either it is legal, needs
516 /// to be promoted to a larger size, needs to be expanded to some other code
517 /// sequence, or the target has a custom expander for it.
519 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
520 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
521 "Table isn't big enough!");
522 unsigned Ty = (unsigned)VT.SimpleTy;
523 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
526 /// Return true if the specified indexed load is legal on this target.
527 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
528 return VT.isSimple() &&
529 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
530 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
533 /// Return how the indexed store should be treated: either it is legal, needs
534 /// to be promoted to a larger size, needs to be expanded to some other code
535 /// sequence, or the target has a custom expander for it.
537 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
538 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
539 "Table isn't big enough!");
540 unsigned Ty = (unsigned)VT.SimpleTy;
541 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
544 /// Return true if the specified indexed load is legal on this target.
545 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
546 return VT.isSimple() &&
547 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
548 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
551 /// Return how the condition code should be treated: either it is legal, needs
552 /// to be expanded to some other code sequence, or the target has a custom
555 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
556 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
557 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
558 "Table isn't big enough!");
559 // See setCondCodeAction for how this is encoded.
560 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
561 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
562 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
563 assert(Action != Promote && "Can't promote condition code!");
567 /// Return true if the specified condition code is legal on this target.
568 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
570 getCondCodeAction(CC, VT) == Legal ||
571 getCondCodeAction(CC, VT) == Custom;
575 /// If the action for this operation is to promote, this method returns the
576 /// ValueType to promote to.
577 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
578 assert(getOperationAction(Op, VT) == Promote &&
579 "This operation isn't promoted!");
581 // See if this has an explicit type specified.
582 std::map<std::pair<unsigned, MVT::SimpleValueType>,
583 MVT::SimpleValueType>::const_iterator PTTI =
584 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
585 if (PTTI != PromoteToType.end()) return PTTI->second;
587 assert((VT.isInteger() || VT.isFloatingPoint()) &&
588 "Cannot autopromote this type, add it with AddPromotedToType.");
592 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
593 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
594 "Didn't find type to promote to!");
595 } while (!isTypeLegal(NVT) ||
596 getOperationAction(Op, NVT) == Promote);
600 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
601 /// operations except for the pointer size. If AllowUnknown is true, this
602 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
603 /// otherwise it will assert.
604 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
605 // Lower scalar pointers to native pointer types.
606 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
607 return getPointerTy(PTy->getAddressSpace());
609 if (Ty->isVectorTy()) {
610 VectorType *VTy = cast<VectorType>(Ty);
611 Type *Elm = VTy->getElementType();
612 // Lower vectors of pointers to native pointer types.
613 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
614 EVT PointerTy(getPointerTy(PT->getAddressSpace()));
615 Elm = PointerTy.getTypeForEVT(Ty->getContext());
618 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
619 VTy->getNumElements());
621 return EVT::getEVT(Ty, AllowUnknown);
624 /// Return the MVT corresponding to this LLVM type. See getValueType.
625 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
626 return getValueType(Ty, AllowUnknown).getSimpleVT();
629 /// Return the desired alignment for ByVal or InAlloca aggregate function
630 /// arguments in the caller parameter area. This is the actual alignment, not
632 virtual unsigned getByValTypeAlignment(Type *Ty) const;
634 /// Return the type of registers that this ValueType will eventually require.
635 MVT getRegisterType(MVT VT) const {
636 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
637 return RegisterTypeForVT[VT.SimpleTy];
640 /// Return the type of registers that this ValueType will eventually require.
641 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
643 assert((unsigned)VT.getSimpleVT().SimpleTy <
644 array_lengthof(RegisterTypeForVT));
645 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
650 unsigned NumIntermediates;
651 (void)getVectorTypeBreakdown(Context, VT, VT1,
652 NumIntermediates, RegisterVT);
655 if (VT.isInteger()) {
656 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
658 llvm_unreachable("Unsupported extended type!");
661 /// Return the number of registers that this ValueType will eventually
664 /// This is one for any types promoted to live in larger registers, but may be
665 /// more than one for types (like i64) that are split into pieces. For types
666 /// like i140, which are first promoted then expanded, it is the number of
667 /// registers needed to hold all the bits of the original type. For an i140
668 /// on a 32 bit machine this means 5 registers.
669 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
671 assert((unsigned)VT.getSimpleVT().SimpleTy <
672 array_lengthof(NumRegistersForVT));
673 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
678 unsigned NumIntermediates;
679 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
681 if (VT.isInteger()) {
682 unsigned BitWidth = VT.getSizeInBits();
683 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
684 return (BitWidth + RegWidth - 1) / RegWidth;
686 llvm_unreachable("Unsupported extended type!");
689 /// If true, then instruction selection should seek to shrink the FP constant
690 /// of the specified type to a smaller type in order to save space and / or
692 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
694 /// If true, the target has custom DAG combine transformations that it can
695 /// perform for the specified node.
696 bool hasTargetDAGCombine(ISD::NodeType NT) const {
697 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
698 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
701 /// \brief Get maximum # of store operations permitted for llvm.memset
703 /// This function returns the maximum number of store operations permitted
704 /// to replace a call to llvm.memset. The value is set by the target at the
705 /// performance threshold for such a replacement. If OptSize is true,
706 /// return the limit for functions that have OptSize attribute.
707 unsigned getMaxStoresPerMemset(bool OptSize) const {
708 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
711 /// \brief Get maximum # of store operations permitted for llvm.memcpy
713 /// This function returns the maximum number of store operations permitted
714 /// to replace a call to llvm.memcpy. The value is set by the target at the
715 /// performance threshold for such a replacement. If OptSize is true,
716 /// return the limit for functions that have OptSize attribute.
717 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
718 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
721 /// \brief Get maximum # of store operations permitted for llvm.memmove
723 /// This function returns the maximum number of store operations permitted
724 /// to replace a call to llvm.memmove. The value is set by the target at the
725 /// performance threshold for such a replacement. If OptSize is true,
726 /// return the limit for functions that have OptSize attribute.
727 unsigned getMaxStoresPerMemmove(bool OptSize) const {
728 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
731 /// \brief Determine if the target supports unaligned memory accesses.
733 /// This function returns true if the target allows unaligned memory accesses
734 /// of the specified type in the given address space. If true, it also returns
735 /// whether the unaligned memory access is "fast" in the third argument by
736 /// reference. This is used, for example, in situations where an array
737 /// copy/move/set is converted to a sequence of store operations. Its use
738 /// helps to ensure that such replacements don't generate code that causes an
739 /// alignment error (trap) on the target machine.
740 virtual bool allowsUnalignedMemoryAccesses(EVT,
741 unsigned AddrSpace = 0,
742 bool * /*Fast*/ = 0) const {
746 /// Returns the target specific optimal type for load and store operations as
747 /// a result of memset, memcpy, and memmove lowering.
749 /// If DstAlign is zero that means it's safe to destination alignment can
750 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
751 /// a need to check it against alignment requirement, probably because the
752 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
753 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
754 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
755 /// does not need to be loaded. It returns EVT::Other if the type should be
756 /// determined using generic target-independent logic.
757 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
758 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
761 bool /*MemcpyStrSrc*/,
762 MachineFunction &/*MF*/) const {
766 /// Returns true if it's safe to use load / store of the specified type to
767 /// expand memcpy / memset inline.
769 /// This is mostly true for all types except for some special cases. For
770 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
771 /// fstpl which also does type conversion. Note the specified type doesn't
772 /// have to be legal as the hook is used before type legalization.
773 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
775 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
776 bool usesUnderscoreSetJmp() const {
777 return UseUnderscoreSetJmp;
780 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
781 bool usesUnderscoreLongJmp() const {
782 return UseUnderscoreLongJmp;
785 /// Return whether the target can generate code for jump tables.
786 bool supportJumpTables() const {
787 return SupportJumpTables;
790 /// Return integer threshold on number of blocks to use jump tables rather
791 /// than if sequence.
792 int getMinimumJumpTableEntries() const {
793 return MinimumJumpTableEntries;
796 /// If a physical register, this specifies the register that
797 /// llvm.savestack/llvm.restorestack should save and restore.
798 unsigned getStackPointerRegisterToSaveRestore() const {
799 return StackPointerRegisterToSaveRestore;
802 /// If a physical register, this returns the register that receives the
803 /// exception address on entry to a landing pad.
804 unsigned getExceptionPointerRegister() const {
805 return ExceptionPointerRegister;
808 /// If a physical register, this returns the register that receives the
809 /// exception typeid on entry to a landing pad.
810 unsigned getExceptionSelectorRegister() const {
811 return ExceptionSelectorRegister;
814 /// Returns the target's jmp_buf size in bytes (if never set, the default is
816 unsigned getJumpBufSize() const {
820 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
822 unsigned getJumpBufAlignment() const {
823 return JumpBufAlignment;
826 /// Return the minimum stack alignment of an argument.
827 unsigned getMinStackArgumentAlignment() const {
828 return MinStackArgumentAlignment;
831 /// Return the minimum function alignment.
832 unsigned getMinFunctionAlignment() const {
833 return MinFunctionAlignment;
836 /// Return the preferred function alignment.
837 unsigned getPrefFunctionAlignment() const {
838 return PrefFunctionAlignment;
841 /// Return the preferred loop alignment.
842 unsigned getPrefLoopAlignment() const {
843 return PrefLoopAlignment;
846 /// Return whether the DAG builder should automatically insert fences and
847 /// reduce ordering for atomics.
848 bool getInsertFencesForAtomic() const {
849 return InsertFencesForAtomic;
852 /// Return true if the target stores stack protector cookies at a fixed offset
853 /// in some non-standard address space, and populates the address space and
854 /// offset as appropriate.
855 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
856 unsigned &/*Offset*/) const {
860 /// Returns the maximal possible offset which can be used for loads / stores
862 virtual unsigned getMaximalGlobalOffset() const {
866 /// Returns true if a cast between SrcAS and DestAS is a noop.
867 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
871 //===--------------------------------------------------------------------===//
872 /// \name Helpers for TargetTransformInfo implementations
875 /// Get the ISD node that corresponds to the Instruction class opcode.
876 int InstructionOpcodeToISD(unsigned Opcode) const;
878 /// Estimate the cost of type-legalization and the legalized type.
879 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;
883 //===--------------------------------------------------------------------===//
884 // TargetLowering Configuration Methods - These methods should be invoked by
885 // the derived class constructor to configure this object for the target.
888 /// \brief Reset the operation actions based on target options.
889 virtual void resetOperationActions() {}
892 /// Specify how the target extends the result of a boolean value from i1 to a
893 /// wider type. See getBooleanContents.
894 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
896 /// Specify how the target extends the result of a vector boolean value from a
897 /// vector of i1 to a wider type. See getBooleanContents.
898 void setBooleanVectorContents(BooleanContent Ty) {
899 BooleanVectorContents = Ty;
902 /// Specify the target scheduling preference.
903 void setSchedulingPreference(Sched::Preference Pref) {
904 SchedPreferenceInfo = Pref;
907 /// Indicate whether this target prefers to use _setjmp to implement
908 /// llvm.setjmp or the version without _. Defaults to false.
909 void setUseUnderscoreSetJmp(bool Val) {
910 UseUnderscoreSetJmp = Val;
913 /// Indicate whether this target prefers to use _longjmp to implement
914 /// llvm.longjmp or the version without _. Defaults to false.
915 void setUseUnderscoreLongJmp(bool Val) {
916 UseUnderscoreLongJmp = Val;
919 /// Indicate whether the target can generate code for jump tables.
920 void setSupportJumpTables(bool Val) {
921 SupportJumpTables = Val;
924 /// Indicate the number of blocks to generate jump tables rather than if
926 void setMinimumJumpTableEntries(int Val) {
927 MinimumJumpTableEntries = Val;
930 /// If set to a physical register, this specifies the register that
931 /// llvm.savestack/llvm.restorestack should save and restore.
932 void setStackPointerRegisterToSaveRestore(unsigned R) {
933 StackPointerRegisterToSaveRestore = R;
936 /// If set to a physical register, this sets the register that receives the
937 /// exception address on entry to a landing pad.
938 void setExceptionPointerRegister(unsigned R) {
939 ExceptionPointerRegister = R;
942 /// If set to a physical register, this sets the register that receives the
943 /// exception typeid on entry to a landing pad.
944 void setExceptionSelectorRegister(unsigned R) {
945 ExceptionSelectorRegister = R;
948 /// Tells the code generator not to expand operations into sequences that use
949 /// the select operations if possible.
950 void setSelectIsExpensive(bool isExpensive = true) {
951 SelectIsExpensive = isExpensive;
954 /// Tells the code generator that the target has multiple (allocatable)
955 /// condition registers that can be used to store the results of comparisons
956 /// for use by selects and conditional branches. With multiple condition
957 /// registers, the code generator will not aggressively sink comparisons into
958 /// the blocks of their users.
959 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
960 HasMultipleConditionRegisters = hasManyRegs;
963 /// Tells the code generator not to expand sequence of operations into a
964 /// separate sequences that increases the amount of flow control.
965 void setJumpIsExpensive(bool isExpensive = true) {
966 JumpIsExpensive = isExpensive;
969 /// Tells the code generator that integer divide is expensive, and if
970 /// possible, should be replaced by an alternate sequence of instructions not
971 /// containing an integer divide.
972 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
974 /// Tells the code generator which bitwidths to bypass.
975 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
976 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
979 /// Tells the code generator that it shouldn't generate srl/add/sra for a
980 /// signed divide by power of two, and let the target handle it.
981 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
983 /// Add the specified register class as an available regclass for the
984 /// specified value type. This indicates the selector can handle values of
985 /// that class natively.
986 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
987 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
988 AvailableRegClasses.push_back(std::make_pair(VT, RC));
989 RegClassForVT[VT.SimpleTy] = RC;
992 /// Remove all register classes.
993 void clearRegisterClasses() {
994 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
996 AvailableRegClasses.clear();
999 /// \brief Remove all operation actions.
1000 void clearOperationActions() {
1003 /// Return the largest legal super-reg register class of the register class
1004 /// for the specified type and its associated "cost".
1005 virtual std::pair<const TargetRegisterClass*, uint8_t>
1006 findRepresentativeClass(MVT VT) const;
1008 /// Once all of the register classes are added, this allows us to compute
1009 /// derived properties we expose.
1010 void computeRegisterProperties();
1012 /// Indicate that the specified operation does not work with the specified
1013 /// type and indicate what to do about it.
1014 void setOperationAction(unsigned Op, MVT VT,
1015 LegalizeAction Action) {
1016 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1017 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1020 /// Indicate that the specified load with extension does not work with the
1021 /// specified type and indicate what to do about it.
1022 void setLoadExtAction(unsigned ExtType, MVT VT,
1023 LegalizeAction Action) {
1024 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
1025 "Table isn't big enough!");
1026 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1029 /// Indicate that the specified truncating store does not work with the
1030 /// specified type and indicate what to do about it.
1031 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1032 LegalizeAction Action) {
1033 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
1034 "Table isn't big enough!");
1035 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1038 /// Indicate that the specified indexed load does or does not work with the
1039 /// specified type and indicate what to do abort it.
1041 /// NOTE: All indexed mode loads are initialized to Expand in
1042 /// TargetLowering.cpp
1043 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1044 LegalizeAction Action) {
1045 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1046 (unsigned)Action < 0xf && "Table isn't big enough!");
1047 // Load action are kept in the upper half.
1048 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1049 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1052 /// Indicate that the specified indexed store does or does not work with the
1053 /// specified type and indicate what to do about it.
1055 /// NOTE: All indexed mode stores are initialized to Expand in
1056 /// TargetLowering.cpp
1057 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1058 LegalizeAction Action) {
1059 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1060 (unsigned)Action < 0xf && "Table isn't big enough!");
1061 // Store action are kept in the lower half.
1062 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1063 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1066 /// Indicate that the specified condition code is or isn't supported on the
1067 /// target and indicate what to do about it.
1068 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1069 LegalizeAction Action) {
1070 assert(VT < MVT::LAST_VALUETYPE &&
1071 (unsigned)CC < array_lengthof(CondCodeActions) &&
1072 "Table isn't big enough!");
1073 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1074 /// value and the upper 27 bits index into the second dimension of the array
1075 /// to select what 32-bit value to use.
1076 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1077 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1078 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1081 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1082 /// to trying a larger integer/fp until it can find one that works. If that
1083 /// default is insufficient, this method can be used by the target to override
1085 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1086 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1089 /// Targets should invoke this method for each target independent node that
1090 /// they want to provide a custom DAG combiner for by implementing the
1091 /// PerformDAGCombine virtual method.
1092 void setTargetDAGCombine(ISD::NodeType NT) {
1093 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1094 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1097 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1098 void setJumpBufSize(unsigned Size) {
1102 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1104 void setJumpBufAlignment(unsigned Align) {
1105 JumpBufAlignment = Align;
1108 /// Set the target's minimum function alignment (in log2(bytes))
1109 void setMinFunctionAlignment(unsigned Align) {
1110 MinFunctionAlignment = Align;
1113 /// Set the target's preferred function alignment. This should be set if
1114 /// there is a performance benefit to higher-than-minimum alignment (in
1116 void setPrefFunctionAlignment(unsigned Align) {
1117 PrefFunctionAlignment = Align;
1120 /// Set the target's preferred loop alignment. Default alignment is zero, it
1121 /// means the target does not care about loop alignment. The alignment is
1122 /// specified in log2(bytes).
1123 void setPrefLoopAlignment(unsigned Align) {
1124 PrefLoopAlignment = Align;
1127 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1128 void setMinStackArgumentAlignment(unsigned Align) {
1129 MinStackArgumentAlignment = Align;
1132 /// Set if the DAG builder should automatically insert fences and reduce the
1133 /// order of atomic memory operations to Monotonic.
1134 void setInsertFencesForAtomic(bool fence) {
1135 InsertFencesForAtomic = fence;
1139 //===--------------------------------------------------------------------===//
1140 // Addressing mode description hooks (used by LSR etc).
1143 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1144 /// instructions reading the address. This allows as much computation as
1145 /// possible to be done in the address mode for that operand. This hook lets
1146 /// targets also pass back when this should be done on intrinsics which
1148 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1149 SmallVectorImpl<Value*> &/*Ops*/,
1150 Type *&/*AccessTy*/) const {
1154 /// This represents an addressing mode of:
1155 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1156 /// If BaseGV is null, there is no BaseGV.
1157 /// If BaseOffs is zero, there is no base offset.
1158 /// If HasBaseReg is false, there is no base register.
1159 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1162 GlobalValue *BaseGV;
1166 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1169 /// Return true if the addressing mode represented by AM is legal for this
1170 /// target, for a load/store of the specified type.
1172 /// The type may be VoidTy, in which case only return true if the addressing
1173 /// mode is legal for a load/store of any legal type. TODO: Handle
1174 /// pre/postinc as well.
1175 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1177 /// \brief Return the cost of the scaling factor used in the addressing mode
1178 /// represented by AM for this target, for a load/store of the specified type.
1180 /// If the AM is supported, the return value must be >= 0.
1181 /// If the AM is not supported, it returns a negative value.
1182 /// TODO: Handle pre/postinc as well.
1183 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const {
1184 // Default: assume that any scaling factor used in a legal AM is free.
1185 if (isLegalAddressingMode(AM, Ty)) return 0;
1189 /// Return true if the specified immediate is legal icmp immediate, that is
1190 /// the target has icmp instructions which can compare a register against the
1191 /// immediate without having to materialize the immediate into a register.
1192 virtual bool isLegalICmpImmediate(int64_t) const {
1196 /// Return true if the specified immediate is legal add immediate, that is the
1197 /// target has add instructions which can add a register with the immediate
1198 /// without having to materialize the immediate into a register.
1199 virtual bool isLegalAddImmediate(int64_t) const {
1203 /// Return true if it's significantly cheaper to shift a vector by a uniform
1204 /// scalar than by an amount which will vary across each lane. On x86, for
1205 /// example, there is a "psllw" instruction for the former case, but no simple
1206 /// instruction for a general "a << b" operation on vectors.
1207 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1211 /// Return true if it's free to truncate a value of type Ty1 to type
1212 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1213 /// by referencing its sub-register AX.
1214 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1218 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding
1219 /// whether a call is in tail position. Typically this means that both results
1220 /// would be assigned to the same register or stack slot, but it could mean
1221 /// the target performs adequate checks of its own before proceeding with the
1223 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const {
1227 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1231 /// Return true if any actual instruction that defines a value of type Ty1
1232 /// implicitly zero-extends the value to Ty2 in the result register.
1234 /// This does not necessarily include registers defined in unknown ways, such
1235 /// as incoming arguments, or copies from unknown virtual registers. Also, if
1236 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
1237 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit
1238 /// values implicit zero-extend the result out to 64 bits.
1239 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1243 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1247 /// Return true if the target supplies and combines to a paired load
1248 /// two loaded values of type LoadedType next to each other in memory.
1249 /// RequiredAlignment gives the minimal alignment constraints that must be met
1250 /// to be able to select this paired load.
1252 /// This information is *not* used to generate actual paired loads, but it is
1253 /// used to generate a sequence of loads that is easier to combine into a
1255 /// For instance, something like this:
1256 /// a = load i64* addr
1257 /// b = trunc i64 a to i32
1258 /// c = lshr i64 a, 32
1259 /// d = trunc i64 c to i32
1260 /// will be optimized into:
1261 /// b = load i32* addr1
1262 /// d = load i32* addr2
1263 /// Where addr1 = addr2 +/- sizeof(i32).
1265 /// In other words, unless the target performs a post-isel load combining,
1266 /// this information should not be provided because it will generate more
1268 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1269 unsigned & /*RequiredAligment*/) const {
1273 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1274 unsigned & /*RequiredAligment*/) const {
1278 /// Return true if zero-extending the specific node Val to type VT2 is free
1279 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1280 /// because it's folded such as X86 zero-extending loads).
1281 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1282 return isZExtFree(Val.getValueType(), VT2);
1285 /// Return true if an fneg operation is free to the point where it is never
1286 /// worthwhile to replace it with a bitwise operation.
1287 virtual bool isFNegFree(EVT VT) const {
1288 assert(VT.isFloatingPoint());
1292 /// Return true if an fabs operation is free to the point where it is never
1293 /// worthwhile to replace it with a bitwise operation.
1294 virtual bool isFAbsFree(EVT VT) const {
1295 assert(VT.isFloatingPoint());
1299 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1300 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1301 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1303 /// NOTE: This may be called before legalization on types for which FMAs are
1304 /// not legal, but should return true if those types will eventually legalize
1305 /// to types that support FMAs. After legalization, it will only be called on
1306 /// types that support FMAs (via Legal or Custom actions)
1307 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1311 /// Return true if it's profitable to narrow operations of type VT1 to
1312 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1314 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1318 /// \brief Return true if it is beneficial to convert a load of a constant to
1319 /// just the constant itself.
1320 /// On some targets it might be more efficient to use a combination of
1321 /// arithmetic instructions to materialize the constant instead of loading it
1322 /// from a constant pool.
1323 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1327 //===--------------------------------------------------------------------===//
1328 // Runtime Library hooks
1331 /// Rename the default libcall routine name for the specified libcall.
1332 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1333 LibcallRoutineNames[Call] = Name;
1336 /// Get the libcall routine name for the specified libcall.
1337 const char *getLibcallName(RTLIB::Libcall Call) const {
1338 return LibcallRoutineNames[Call];
1341 /// Override the default CondCode to be used to test the result of the
1342 /// comparison libcall against zero.
1343 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1344 CmpLibcallCCs[Call] = CC;
1347 /// Get the CondCode that's to be used to test the result of the comparison
1348 /// libcall against zero.
1349 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1350 return CmpLibcallCCs[Call];
1353 /// Set the CallingConv that should be used for the specified libcall.
1354 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1355 LibcallCallingConvs[Call] = CC;
1358 /// Get the CallingConv that should be used for the specified libcall.
1359 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1360 return LibcallCallingConvs[Call];
1364 const TargetMachine &TM;
1365 const DataLayout *DL;
1366 const TargetLoweringObjectFile &TLOF;
1368 /// True if this is a little endian target.
1369 bool IsLittleEndian;
1371 /// Tells the code generator not to expand operations into sequences that use
1372 /// the select operations if possible.
1373 bool SelectIsExpensive;
1375 /// Tells the code generator that the target has multiple (allocatable)
1376 /// condition registers that can be used to store the results of comparisons
1377 /// for use by selects and conditional branches. With multiple condition
1378 /// registers, the code generator will not aggressively sink comparisons into
1379 /// the blocks of their users.
1380 bool HasMultipleConditionRegisters;
1382 /// Tells the code generator not to expand integer divides by constants into a
1383 /// sequence of muls, adds, and shifts. This is a hack until a real cost
1384 /// model is in place. If we ever optimize for size, this will be set to true
1385 /// unconditionally.
1388 /// Tells the code generator to bypass slow divide or remainder
1389 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1390 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1391 /// div/rem when the operands are positive and less than 256.
1392 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1394 /// Tells the code generator that it shouldn't generate srl/add/sra for a
1395 /// signed divide by power of two, and let the target handle it.
1396 bool Pow2DivIsCheap;
1398 /// Tells the code generator that it shouldn't generate extra flow control
1399 /// instructions and should attempt to combine flow control instructions via
1401 bool JumpIsExpensive;
1403 /// This target prefers to use _setjmp to implement llvm.setjmp.
1405 /// Defaults to false.
1406 bool UseUnderscoreSetJmp;
1408 /// This target prefers to use _longjmp to implement llvm.longjmp.
1410 /// Defaults to false.
1411 bool UseUnderscoreLongJmp;
1413 /// Whether the target can generate code for jumptables. If it's not true,
1414 /// then each jumptable must be lowered into if-then-else's.
1415 bool SupportJumpTables;
1417 /// Number of blocks threshold to use jump tables.
1418 int MinimumJumpTableEntries;
1420 /// Information about the contents of the high-bits in boolean values held in
1421 /// a type wider than i1. See getBooleanContents.
1422 BooleanContent BooleanContents;
1424 /// Information about the contents of the high-bits in boolean vector values
1425 /// when the element type is wider than i1. See getBooleanContents.
1426 BooleanContent BooleanVectorContents;
1428 /// The target scheduling preference: shortest possible total cycles or lowest
1430 Sched::Preference SchedPreferenceInfo;
1432 /// The size, in bytes, of the target's jmp_buf buffers
1433 unsigned JumpBufSize;
1435 /// The alignment, in bytes, of the target's jmp_buf buffers
1436 unsigned JumpBufAlignment;
1438 /// The minimum alignment that any argument on the stack needs to have.
1439 unsigned MinStackArgumentAlignment;
1441 /// The minimum function alignment (used when optimizing for size, and to
1442 /// prevent explicitly provided alignment from leading to incorrect code).
1443 unsigned MinFunctionAlignment;
1445 /// The preferred function alignment (used when alignment unspecified and
1446 /// optimizing for speed).
1447 unsigned PrefFunctionAlignment;
1449 /// The preferred loop alignment.
1450 unsigned PrefLoopAlignment;
1452 /// Whether the DAG builder should automatically insert fences and reduce
1453 /// ordering for atomics. (This will be set for for most architectures with
1454 /// weak memory ordering.)
1455 bool InsertFencesForAtomic;
1457 /// If set to a physical register, this specifies the register that
1458 /// llvm.savestack/llvm.restorestack should save and restore.
1459 unsigned StackPointerRegisterToSaveRestore;
1461 /// If set to a physical register, this specifies the register that receives
1462 /// the exception address on entry to a landing pad.
1463 unsigned ExceptionPointerRegister;
1465 /// If set to a physical register, this specifies the register that receives
1466 /// the exception typeid on entry to a landing pad.
1467 unsigned ExceptionSelectorRegister;
1469 /// This indicates the default register class to use for each ValueType the
1470 /// target supports natively.
1471 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1472 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1473 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1475 /// This indicates the "representative" register class to use for each
1476 /// ValueType the target supports natively. This information is used by the
1477 /// scheduler to track register pressure. By default, the representative
1478 /// register class is the largest legal super-reg register class of the
1479 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1480 /// representative class would be GR32.
1481 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1483 /// This indicates the "cost" of the "representative" register class for each
1484 /// ValueType. The cost is used by the scheduler to approximate register
1486 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1488 /// For any value types we are promoting or expanding, this contains the value
1489 /// type that we are changing to. For Expanded types, this contains one step
1490 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1491 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1492 /// the same type (e.g. i32 -> i32).
1493 MVT TransformToType[MVT::LAST_VALUETYPE];
1495 /// For each operation and each value type, keep a LegalizeAction that
1496 /// indicates how instruction selection should deal with the operation. Most
1497 /// operations are Legal (aka, supported natively by the target), but
1498 /// operations that are not should be described. Note that operations on
1499 /// non-legal value types are not described here.
1500 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1502 /// For each load extension type and each value type, keep a LegalizeAction
1503 /// that indicates how instruction selection should deal with a load of a
1504 /// specific value type and extension type.
1505 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1507 /// For each value type pair keep a LegalizeAction that indicates whether a
1508 /// truncating store of a specific value type and truncating type is legal.
1509 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1511 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1512 /// that indicates how instruction selection should deal with the load /
1515 /// The first dimension is the value_type for the reference. The second
1516 /// dimension represents the various modes for load store.
1517 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1519 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1520 /// indicates how instruction selection should deal with the condition code.
1522 /// Because each CC action takes up 2 bits, we need to have the array size be
1523 /// large enough to fit all of the value types. This can be done by rounding
1524 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1525 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1527 ValueTypeActionImpl ValueTypeActions;
1531 getTypeConversion(LLVMContext &Context, EVT VT) const {
1532 // If this is a simple type, use the ComputeRegisterProp mechanism.
1533 if (VT.isSimple()) {
1534 MVT SVT = VT.getSimpleVT();
1535 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1536 MVT NVT = TransformToType[SVT.SimpleTy];
1537 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1541 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)
1542 && "Promote may not follow Expand or Promote");
1544 if (LA == TypeSplitVector)
1545 return LegalizeKind(LA, EVT::getVectorVT(Context,
1546 SVT.getVectorElementType(),
1547 SVT.getVectorNumElements()/2));
1548 if (LA == TypeScalarizeVector)
1549 return LegalizeKind(LA, SVT.getVectorElementType());
1550 return LegalizeKind(LA, NVT);
1553 // Handle Extended Scalar Types.
1554 if (!VT.isVector()) {
1555 assert(VT.isInteger() && "Float types must be simple");
1556 unsigned BitSize = VT.getSizeInBits();
1557 // First promote to a power-of-two size, then expand if necessary.
1558 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1559 EVT NVT = VT.getRoundIntegerType(Context);
1560 assert(NVT != VT && "Unable to round integer VT");
1561 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1562 // Avoid multi-step promotion.
1563 if (NextStep.first == TypePromoteInteger) return NextStep;
1564 // Return rounded integer type.
1565 return LegalizeKind(TypePromoteInteger, NVT);
1568 return LegalizeKind(TypeExpandInteger,
1569 EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
1572 // Handle vector types.
1573 unsigned NumElts = VT.getVectorNumElements();
1574 EVT EltVT = VT.getVectorElementType();
1576 // Vectors with only one element are always scalarized.
1578 return LegalizeKind(TypeScalarizeVector, EltVT);
1580 // Try to widen vector elements until the element type is a power of two and
1581 // promote it to a legal type later on, for example:
1582 // <3 x i8> -> <4 x i8> -> <4 x i32>
1583 if (EltVT.isInteger()) {
1584 // Vectors with a number of elements that is not a power of two are always
1585 // widened, for example <3 x i8> -> <4 x i8>.
1586 if (!VT.isPow2VectorType()) {
1587 NumElts = (unsigned)NextPowerOf2(NumElts);
1588 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1589 return LegalizeKind(TypeWidenVector, NVT);
1592 // Examine the element type.
1593 LegalizeKind LK = getTypeConversion(Context, EltVT);
1595 // If type is to be expanded, split the vector.
1596 // <4 x i140> -> <2 x i140>
1597 if (LK.first == TypeExpandInteger)
1598 return LegalizeKind(TypeSplitVector,
1599 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1601 // Promote the integer element types until a legal vector type is found
1602 // or until the element integer type is too big. If a legal type was not
1603 // found, fallback to the usual mechanism of widening/splitting the
1605 EVT OldEltVT = EltVT;
1607 // Increase the bitwidth of the element to the next pow-of-two
1608 // (which is greater than 8 bits).
1609 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
1610 ).getRoundIntegerType(Context);
1612 // Stop trying when getting a non-simple element type.
1613 // Note that vector elements may be greater than legal vector element
1614 // types. Example: X86 XMM registers hold 64bit element on 32bit
1616 if (!EltVT.isSimple()) break;
1618 // Build a new vector type and check if it is legal.
1619 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1620 // Found a legal promoted vector type.
1621 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1622 return LegalizeKind(TypePromoteInteger,
1623 EVT::getVectorVT(Context, EltVT, NumElts));
1626 // Reset the type to the unexpanded type if we did not find a legal vector
1627 // type with a promoted vector element type.
1631 // Try to widen the vector until a legal type is found.
1632 // If there is no wider legal type, split the vector.
1634 // Round up to the next power of 2.
1635 NumElts = (unsigned)NextPowerOf2(NumElts);
1637 // If there is no simple vector type with this many elements then there
1638 // cannot be a larger legal vector type. Note that this assumes that
1639 // there are no skipped intermediate vector types in the simple types.
1640 if (!EltVT.isSimple()) break;
1641 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1642 if (LargerVector == MVT()) break;
1644 // If this type is legal then widen the vector.
1645 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1646 return LegalizeKind(TypeWidenVector, LargerVector);
1649 // Widen odd vectors to next power of two.
1650 if (!VT.isPow2VectorType()) {
1651 EVT NVT = VT.getPow2VectorType(Context);
1652 return LegalizeKind(TypeWidenVector, NVT);
1655 // Vectors with illegal element types are expanded.
1656 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1657 return LegalizeKind(TypeSplitVector, NVT);
1661 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1663 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1664 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1667 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1669 /// For operations that must be promoted to a specific type, this holds the
1670 /// destination type. This map should be sparse, so don't hold it as an
1673 /// Targets add entries to this map with AddPromotedToType(..), clients access
1674 /// this with getTypeToPromoteTo(..).
1675 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1678 /// Stores the name each libcall.
1679 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1681 /// The ISD::CondCode that should be used to test the result of each of the
1682 /// comparison libcall against zero.
1683 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1685 /// Stores the CallingConv that should be used for each libcall.
1686 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1689 /// \brief Specify maximum number of store instructions per memset call.
1691 /// When lowering \@llvm.memset this field specifies the maximum number of
1692 /// store operations that may be substituted for the call to memset. Targets
1693 /// must set this value based on the cost threshold for that target. Targets
1694 /// should assume that the memset will be done using as many of the largest
1695 /// store operations first, followed by smaller ones, if necessary, per
1696 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1697 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1698 /// store. This only applies to setting a constant array of a constant size.
1699 unsigned MaxStoresPerMemset;
1701 /// Maximum number of stores operations that may be substituted for the call
1702 /// to memset, used for functions with OptSize attribute.
1703 unsigned MaxStoresPerMemsetOptSize;
1705 /// \brief Specify maximum bytes of store instructions per memcpy call.
1707 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1708 /// store operations that may be substituted for a call to memcpy. Targets
1709 /// must set this value based on the cost threshold for that target. Targets
1710 /// should assume that the memcpy will be done using as many of the largest
1711 /// store operations first, followed by smaller ones, if necessary, per
1712 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1713 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1714 /// and one 1-byte store. This only applies to copying a constant array of
1716 unsigned MaxStoresPerMemcpy;
1718 /// Maximum number of store operations that may be substituted for a call to
1719 /// memcpy, used for functions with OptSize attribute.
1720 unsigned MaxStoresPerMemcpyOptSize;
1722 /// \brief Specify maximum bytes of store instructions per memmove call.
1724 /// When lowering \@llvm.memmove this field specifies the maximum number of
1725 /// store instructions that may be substituted for a call to memmove. Targets
1726 /// must set this value based on the cost threshold for that target. Targets
1727 /// should assume that the memmove will be done using as many of the largest
1728 /// store operations first, followed by smaller ones, if necessary, per
1729 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1730 /// with 8-bit alignment would result in nine 1-byte stores. This only
1731 /// applies to copying a constant array of constant size.
1732 unsigned MaxStoresPerMemmove;
1734 /// Maximum number of store instructions that may be substituted for a call to
1735 /// memmove, used for functions with OpSize attribute.
1736 unsigned MaxStoresPerMemmoveOptSize;
1738 /// Tells the code generator that select is more expensive than a branch if
1739 /// the branch is usually predicted right.
1740 bool PredictableSelectIsExpensive;
1742 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
1743 /// a mask of a single bit, a compare, and a branch into a single instruction.
1744 bool MaskAndBranchFoldingIsLegal;
1747 /// Return true if the value types that can be represented by the specified
1748 /// register class are all legal.
1749 bool isLegalRC(const TargetRegisterClass *RC) const;
1751 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1752 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1753 MachineBasicBlock *emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const;
1756 /// This class defines information used to lower LLVM code to legal SelectionDAG
1757 /// operators that the target instruction selector can accept natively.
1759 /// This class also defines callbacks that targets must implement to lower
1760 /// target-specific constructs to SelectionDAG operators.
1761 class TargetLowering : public TargetLoweringBase {
1762 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
1763 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
1766 /// NOTE: The constructor takes ownership of TLOF.
1767 explicit TargetLowering(const TargetMachine &TM,
1768 const TargetLoweringObjectFile *TLOF);
1770 /// Returns true by value, base pointer and offset pointer and addressing mode
1771 /// by reference if the node's address can be legally represented as
1772 /// pre-indexed load / store address.
1773 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
1774 SDValue &/*Offset*/,
1775 ISD::MemIndexedMode &/*AM*/,
1776 SelectionDAG &/*DAG*/) const {
1780 /// Returns true by value, base pointer and offset pointer and addressing mode
1781 /// by reference if this node can be combined with a load / store to form a
1782 /// post-indexed load / store.
1783 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
1785 SDValue &/*Offset*/,
1786 ISD::MemIndexedMode &/*AM*/,
1787 SelectionDAG &/*DAG*/) const {
1791 /// Return the entry encoding for a jump table in the current function. The
1792 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
1793 virtual unsigned getJumpTableEncoding() const;
1795 virtual const MCExpr *
1796 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
1797 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
1798 MCContext &/*Ctx*/) const {
1799 llvm_unreachable("Need to implement this hook if target has custom JTIs");
1802 /// Returns relocation base for the given PIC jumptable.
1803 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
1804 SelectionDAG &DAG) const;
1806 /// This returns the relocation base for the given PIC jumptable, the same as
1807 /// getPICJumpTableRelocBase, but as an MCExpr.
1808 virtual const MCExpr *
1809 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1810 unsigned JTI, MCContext &Ctx) const;
1812 /// Return true if folding a constant offset with the given GlobalAddress is
1813 /// legal. It is frequently not legal in PIC relocation models.
1814 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
1816 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
1817 SDValue &Chain) const;
1819 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
1820 SDValue &NewLHS, SDValue &NewRHS,
1821 ISD::CondCode &CCCode, SDLoc DL) const;
1823 /// Returns a pair of (return value, chain).
1824 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
1825 EVT RetVT, const SDValue *Ops,
1826 unsigned NumOps, bool isSigned,
1827 SDLoc dl, bool doesNotReturn = false,
1828 bool isReturnValueUsed = true) const;
1830 //===--------------------------------------------------------------------===//
1831 // TargetLowering Optimization Methods
1834 /// A convenience struct that encapsulates a DAG, and two SDValues for
1835 /// returning information from TargetLowering to its clients that want to
1837 struct TargetLoweringOpt {
1844 explicit TargetLoweringOpt(SelectionDAG &InDAG,
1846 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
1848 bool LegalTypes() const { return LegalTys; }
1849 bool LegalOperations() const { return LegalOps; }
1851 bool CombineTo(SDValue O, SDValue N) {
1857 /// Check to see if the specified operand of the specified instruction is a
1858 /// constant integer. If so, check to see if there are any bits set in the
1859 /// constant that are not demanded. If so, shrink the constant and return
1861 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
1863 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
1864 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
1865 /// generalized for targets with other types of implicit widening casts.
1866 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
1870 /// Look at Op. At this point, we know that only the DemandedMask bits of the
1871 /// result of Op are ever used downstream. If we can use this information to
1872 /// simplify Op, create a new simplified DAG node and return true, returning
1873 /// the original and new nodes in Old and New. Otherwise, analyze the
1874 /// expression and return a mask of KnownOne and KnownZero bits for the
1875 /// expression (used to simplify the caller). The KnownZero/One bits may only
1876 /// be accurate for those bits in the DemandedMask.
1877 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
1878 APInt &KnownZero, APInt &KnownOne,
1879 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
1881 /// Determine which of the bits specified in Mask are known to be either zero
1882 /// or one and return them in the KnownZero/KnownOne bitsets.
1883 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
1886 const SelectionDAG &DAG,
1887 unsigned Depth = 0) const;
1889 /// This method can be implemented by targets that want to expose additional
1890 /// information about sign bits to the DAG Combiner.
1891 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
1892 unsigned Depth = 0) const;
1894 struct DAGCombinerInfo {
1895 void *DC; // The DAG Combiner object.
1897 bool CalledByLegalizer;
1901 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
1902 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
1904 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
1905 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
1906 bool isAfterLegalizeVectorOps() const {
1907 return Level == AfterLegalizeDAG;
1909 CombineLevel getDAGCombineLevel() { return Level; }
1910 bool isCalledByLegalizer() const { return CalledByLegalizer; }
1912 void AddToWorklist(SDNode *N);
1913 void RemoveFromWorklist(SDNode *N);
1914 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
1916 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
1917 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
1919 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
1922 /// Try to simplify a setcc built with the specified operands and cc. If it is
1923 /// unable to simplify it, return a null SDValue.
1924 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1925 ISD::CondCode Cond, bool foldBooleans,
1926 DAGCombinerInfo &DCI, SDLoc dl) const;
1928 /// Returns true (and the GlobalValue and the offset) if the node is a
1929 /// GlobalAddress + offset.
1931 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
1933 /// This method will be invoked for all target nodes and for any
1934 /// target-independent nodes that the target has registered with invoke it
1937 /// The semantics are as follows:
1939 /// SDValue.Val == 0 - No change was made
1940 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
1941 /// otherwise - N should be replaced by the returned Operand.
1943 /// In addition, methods provided by DAGCombinerInfo may be used to perform
1944 /// more complex transformations.
1946 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
1948 /// Return true if the target has native support for the specified value type
1949 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
1950 /// i16 is legal, but undesirable since i16 instruction encodings are longer
1951 /// and some i16 instructions are slow.
1952 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
1953 // By default, assume all legal types are desirable.
1954 return isTypeLegal(VT);
1957 /// Return true if it is profitable for dag combiner to transform a floating
1958 /// point op of specified opcode to a equivalent op of an integer
1959 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
1960 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
1965 /// This method query the target whether it is beneficial for dag combiner to
1966 /// promote the specified node. If true, it should return the desired
1967 /// promotion type by reference.
1968 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
1972 //===--------------------------------------------------------------------===//
1973 // Lowering methods - These methods must be implemented by targets so that
1974 // the SelectionDAGBuilder code knows how to lower these.
1977 /// This hook must be implemented to lower the incoming (formal) arguments,
1978 /// described by the Ins array, into the specified DAG. The implementation
1979 /// should fill in the InVals array with legal-type argument values, and
1980 /// return the resulting token chain value.
1983 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
1985 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
1986 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
1987 SmallVectorImpl<SDValue> &/*InVals*/) const {
1988 llvm_unreachable("Not Implemented");
1991 struct ArgListEntry {
2000 bool isInAlloca : 1;
2001 bool isReturned : 1;
2004 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2005 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2006 isReturned(false), Alignment(0) { }
2008 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2010 typedef std::vector<ArgListEntry> ArgListTy;
2012 /// This structure contains all information that is necessary for lowering
2013 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2014 /// needs to lower a call, and targets will see this struct in their LowerCall
2016 struct CallLoweringInfo {
2023 bool DoesNotReturn : 1;
2024 bool IsReturnValueUsed : 1;
2026 // IsTailCall should be modified by implementations of
2027 // TargetLowering::LowerCall that perform tail call conversions.
2030 unsigned NumFixedArgs;
2031 CallingConv::ID CallConv;
2036 ImmutableCallSite *CS;
2037 SmallVector<ISD::OutputArg, 32> Outs;
2038 SmallVector<SDValue, 32> OutVals;
2039 SmallVector<ISD::InputArg, 32> Ins;
2042 /// Constructs a call lowering context based on the ImmutableCallSite \p cs.
2043 CallLoweringInfo(SDValue chain, Type *retTy,
2044 FunctionType *FTy, bool isTailCall, SDValue callee,
2045 ArgListTy &args, SelectionDAG &dag, SDLoc dl,
2046 ImmutableCallSite &cs)
2047 : Chain(chain), RetTy(retTy), RetSExt(cs.paramHasAttr(0, Attribute::SExt)),
2048 RetZExt(cs.paramHasAttr(0, Attribute::ZExt)), IsVarArg(FTy->isVarArg()),
2049 IsInReg(cs.paramHasAttr(0, Attribute::InReg)),
2050 DoesNotReturn(cs.doesNotReturn()),
2051 IsReturnValueUsed(!cs.getInstruction()->use_empty()),
2052 IsTailCall(isTailCall), NumFixedArgs(FTy->getNumParams()),
2053 CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag),
2056 /// Constructs a call lowering context based on the provided call
2058 CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt,
2059 bool isVarArg, bool isInReg, unsigned numFixedArgs,
2060 CallingConv::ID callConv, bool isTailCall,
2061 bool doesNotReturn, bool isReturnValueUsed, SDValue callee,
2062 ArgListTy &args, SelectionDAG &dag, SDLoc dl)
2063 : Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt),
2064 IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn),
2065 IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall),
2066 NumFixedArgs(numFixedArgs), CallConv(callConv), Callee(callee),
2067 Args(args), DAG(dag), DL(dl), CS(NULL) {}
2070 /// This function lowers an abstract call to a function into an actual call.
2071 /// This returns a pair of operands. The first element is the return value
2072 /// for the function (if RetTy is not VoidTy). The second element is the
2073 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2074 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2076 /// This hook must be implemented to lower calls into the the specified
2077 /// DAG. The outgoing arguments to the call are described by the Outs array,
2078 /// and the values to be returned by the call are described by the Ins
2079 /// array. The implementation should fill in the InVals array with legal-type
2080 /// return values from the call, and return the resulting token chain value.
2082 LowerCall(CallLoweringInfo &/*CLI*/,
2083 SmallVectorImpl<SDValue> &/*InVals*/) const {
2084 llvm_unreachable("Not Implemented");
2087 /// Target-specific cleanup for formal ByVal parameters.
2088 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2090 /// This hook should be implemented to check whether the return values
2091 /// described by the Outs array can fit into the return registers. If false
2092 /// is returned, an sret-demotion is performed.
2093 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2094 MachineFunction &/*MF*/, bool /*isVarArg*/,
2095 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2096 LLVMContext &/*Context*/) const
2098 // Return true by default to get preexisting behavior.
2102 /// This hook must be implemented to lower outgoing return values, described
2103 /// by the Outs array, into the specified DAG. The implementation should
2104 /// return the resulting token chain value.
2106 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2108 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2109 const SmallVectorImpl<SDValue> &/*OutVals*/,
2110 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2111 llvm_unreachable("Not Implemented");
2114 /// Return true if result of the specified node is used by a return node
2115 /// only. It also compute and return the input chain for the tail call.
2117 /// This is used to determine whether it is possible to codegen a libcall as
2118 /// tail call at legalization time.
2119 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2123 /// Return true if the target may be able emit the call instruction as a tail
2124 /// call. This is used by optimization passes to determine if it's profitable
2125 /// to duplicate return instructions to enable tailcall optimization.
2126 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2130 /// Return the builtin name for the __builtin___clear_cache intrinsic
2131 /// Default is to invoke the clear cache library call
2132 virtual const char * getClearCacheBuiltinName() const {
2133 return "__clear_cache";
2136 /// Return the type that should be used to zero or sign extend a
2137 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2138 /// convention requires the return type to be promoted, but this is not true
2139 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2140 /// calling conventions. The frontend should handle this and include all of
2141 /// the necessary information.
2142 virtual MVT getTypeForExtArgOrReturn(MVT VT,
2143 ISD::NodeType /*ExtendKind*/) const {
2144 MVT MinVT = getRegisterType(MVT::i32);
2145 return VT.bitsLT(MinVT) ? MinVT : VT;
2148 /// Returns a 0 terminated array of registers that can be safely used as
2149 /// scratch registers.
2150 virtual const uint16_t *getScratchRegisters(CallingConv::ID CC) const {
2154 /// This callback is used to prepare for a volatile or atomic load.
2155 /// It takes a chain node as input and returns the chain for the load itself.
2157 /// Having a callback like this is necessary for targets like SystemZ,
2158 /// which allows a CPU to reuse the result of a previous load indefinitely,
2159 /// even if a cache-coherent store is performed by another CPU. The default
2160 /// implementation does nothing.
2161 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2162 SelectionDAG &DAG) const {
2166 /// This callback is invoked by the type legalizer to legalize nodes with an
2167 /// illegal operand type but legal result types. It replaces the
2168 /// LowerOperation callback in the type Legalizer. The reason we can not do
2169 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2170 /// use this callback.
2172 /// TODO: Consider merging with ReplaceNodeResults.
2174 /// The target places new result values for the node in Results (their number
2175 /// and types must exactly match those of the original return values of
2176 /// the node), or leaves Results empty, which indicates that the node is not
2177 /// to be custom lowered after all.
2178 /// The default implementation calls LowerOperation.
2179 virtual void LowerOperationWrapper(SDNode *N,
2180 SmallVectorImpl<SDValue> &Results,
2181 SelectionDAG &DAG) const;
2183 /// This callback is invoked for operations that are unsupported by the
2184 /// target, which are registered to use 'custom' lowering, and whose defined
2185 /// values are all legal. If the target has no operations that require custom
2186 /// lowering, it need not implement this. The default implementation of this
2188 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2190 /// This callback is invoked when a node result type is illegal for the
2191 /// target, and the operation was registered to use 'custom' lowering for that
2192 /// result type. The target places new result values for the node in Results
2193 /// (their number and types must exactly match those of the original return
2194 /// values of the node), or leaves Results empty, which indicates that the
2195 /// node is not to be custom lowered after all.
2197 /// If the target has no operations that require custom lowering, it need not
2198 /// implement this. The default implementation aborts.
2199 virtual void ReplaceNodeResults(SDNode * /*N*/,
2200 SmallVectorImpl<SDValue> &/*Results*/,
2201 SelectionDAG &/*DAG*/) const {
2202 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2205 /// This method returns the name of a target specific DAG node.
2206 virtual const char *getTargetNodeName(unsigned Opcode) const;
2208 /// This method returns a target specific FastISel object, or null if the
2209 /// target does not support "fast" ISel.
2210 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2211 const TargetLibraryInfo *) const {
2216 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2217 SelectionDAG &DAG) const;
2219 //===--------------------------------------------------------------------===//
2220 // Inline Asm Support hooks
2223 /// This hook allows the target to expand an inline asm call to be explicit
2224 /// llvm code if it wants to. This is useful for turning simple inline asms
2225 /// into LLVM intrinsics, which gives the compiler more information about the
2226 /// behavior of the code.
2227 virtual bool ExpandInlineAsm(CallInst *) const {
2231 enum ConstraintType {
2232 C_Register, // Constraint represents specific register(s).
2233 C_RegisterClass, // Constraint represents any of register(s) in class.
2234 C_Memory, // Memory constraint.
2235 C_Other, // Something else.
2236 C_Unknown // Unsupported constraint.
2239 enum ConstraintWeight {
2241 CW_Invalid = -1, // No match.
2242 CW_Okay = 0, // Acceptable.
2243 CW_Good = 1, // Good weight.
2244 CW_Better = 2, // Better weight.
2245 CW_Best = 3, // Best weight.
2247 // Well-known weights.
2248 CW_SpecificReg = CW_Okay, // Specific register operands.
2249 CW_Register = CW_Good, // Register operands.
2250 CW_Memory = CW_Better, // Memory operands.
2251 CW_Constant = CW_Best, // Constant operand.
2252 CW_Default = CW_Okay // Default or don't know type.
2255 /// This contains information for each constraint that we are lowering.
2256 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2257 /// This contains the actual string for the code, like "m". TargetLowering
2258 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2259 /// matches the operand.
2260 std::string ConstraintCode;
2262 /// Information about the constraint code, e.g. Register, RegisterClass,
2263 /// Memory, Other, Unknown.
2264 TargetLowering::ConstraintType ConstraintType;
2266 /// If this is the result output operand or a clobber, this is null,
2267 /// otherwise it is the incoming operand to the CallInst. This gets
2268 /// modified as the asm is processed.
2269 Value *CallOperandVal;
2271 /// The ValueType for the operand value.
2274 /// Return true of this is an input operand that is a matching constraint
2276 bool isMatchingInputConstraint() const;
2278 /// If this is an input matching constraint, this method returns the output
2279 /// operand it matches.
2280 unsigned getMatchedOperand() const;
2282 /// Copy constructor for copying from a ConstraintInfo.
2283 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
2284 : InlineAsm::ConstraintInfo(info),
2285 ConstraintType(TargetLowering::C_Unknown),
2286 CallOperandVal(0), ConstraintVT(MVT::Other) {
2290 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2292 /// Split up the constraint string from the inline assembly value into the
2293 /// specific constraints and their prefixes, and also tie in the associated
2294 /// operand values. If this returns an empty vector, and if the constraint
2295 /// string itself isn't empty, there was an error parsing.
2296 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
2298 /// Examine constraint type and operand type and determine a weight value.
2299 /// The operand object must already have been set up with the operand type.
2300 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2301 AsmOperandInfo &info, int maIndex) const;
2303 /// Examine constraint string and operand type and determine a weight value.
2304 /// The operand object must already have been set up with the operand type.
2305 virtual ConstraintWeight getSingleConstraintMatchWeight(
2306 AsmOperandInfo &info, const char *constraint) const;
2308 /// Determines the constraint code and constraint type to use for the specific
2309 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2310 /// If the actual operand being passed in is available, it can be passed in as
2311 /// Op, otherwise an empty SDValue can be passed.
2312 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2314 SelectionDAG *DAG = 0) const;
2316 /// Given a constraint, return the type of constraint it is for this target.
2317 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
2319 /// Given a physical register constraint (e.g. {edx}), return the register
2320 /// number and the register class for the register.
2322 /// Given a register class constraint, like 'r', if this corresponds directly
2323 /// to an LLVM register class, return a register of 0 and the register class
2326 /// This should only be used for C_Register constraints. On error, this
2327 /// returns a register number of 0 and a null register class pointer..
2328 virtual std::pair<unsigned, const TargetRegisterClass*>
2329 getRegForInlineAsmConstraint(const std::string &Constraint,
2332 /// Try to replace an X constraint, which matches anything, with another that
2333 /// has more specific requirements based on the type of the corresponding
2334 /// operand. This returns null if there is no replacement to make.
2335 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2337 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2338 /// add anything to Ops.
2339 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2340 std::vector<SDValue> &Ops,
2341 SelectionDAG &DAG) const;
2343 //===--------------------------------------------------------------------===//
2344 // Div utility functions
2346 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2347 SelectionDAG &DAG) const;
2348 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
2349 std::vector<SDNode*> *Created) const;
2350 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
2351 std::vector<SDNode*> *Created) const;
2353 //===--------------------------------------------------------------------===//
2354 // Instruction Emitting Hooks
2357 /// This method should be implemented by targets that mark instructions with
2358 /// the 'usesCustomInserter' flag. These instructions are special in various
2359 /// ways, which require special support to insert. The specified MachineInstr
2360 /// is created but not inserted into any basic blocks, and this method is
2361 /// called to expand it into a sequence of instructions, potentially also
2362 /// creating new basic blocks and control flow.
2363 virtual MachineBasicBlock *
2364 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2366 /// This method should be implemented by targets that mark instructions with
2367 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2368 /// instruction selection by target hooks. e.g. To fill in optional defs for
2369 /// ARM 's' setting instructions.
2371 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2374 /// Given an LLVM IR type and return type attributes, compute the return value
2375 /// EVTs and flags, and optionally also the offsets, if the return value is
2376 /// being lowered to memory.
2377 void GetReturnInfo(Type* ReturnType, AttributeSet attr,
2378 SmallVectorImpl<ISD::OutputArg> &Outs,
2379 const TargetLowering &TLI);
2381 } // end llvm namespace