1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/IR/Instructions.h"
35 #include "llvm/IR/IRBuilder.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/Target/TargetCallingConv.h"
38 #include "llvm/Target/TargetMachine.h"
47 class FunctionLoweringInfo;
48 class ImmutableCallSite;
50 class MachineBasicBlock;
51 class MachineFunction;
53 class MachineJumpTableInfo;
58 template<typename T> class SmallVectorImpl;
60 class TargetRegisterClass;
61 class TargetLibraryInfo;
62 class TargetLoweringObjectFile;
67 None, // No preference
68 Source, // Follow source order.
69 RegPressure, // Scheduling for lowest register pressure.
70 Hybrid, // Scheduling for both latency and register pressure.
71 ILP, // Scheduling for ILP in low register pressure mode.
72 VLIW // Scheduling for VLIW targets.
76 /// This base class for TargetLowering contains the SelectionDAG-independent
77 /// parts that can be used from the rest of CodeGen.
78 class TargetLoweringBase {
79 TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
80 void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
83 /// This enum indicates whether operations are valid for a target, and if not,
84 /// what action should be used to make them valid.
86 Legal, // The target natively supports this operation.
87 Promote, // This operation should be executed in a larger type.
88 Expand, // Try to expand this to other ops, otherwise use a libcall.
89 Custom // Use the LowerOperation hook to implement custom lowering.
92 /// This enum indicates whether a types are legal for a target, and if not,
93 /// what action should be used to make them valid.
94 enum LegalizeTypeAction {
95 TypeLegal, // The target natively supports this type.
96 TypePromoteInteger, // Replace this integer with a larger one.
97 TypeExpandInteger, // Split this integer into two of half the size.
98 TypeSoftenFloat, // Convert this float to a same size integer type.
99 TypeExpandFloat, // Split this float into two of half the size.
100 TypeScalarizeVector, // Replace this one-element vector with its element.
101 TypeSplitVector, // Split this vector into two of half the size.
102 TypeWidenVector // This vector should be widened into a larger vector.
105 /// LegalizeKind holds the legalization kind that needs to happen to EVT
106 /// in order to type-legalize it.
107 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
109 /// Enum that describes how the target represents true/false values.
110 enum BooleanContent {
111 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
112 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
113 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
116 /// Enum that describes what type of support for selects the target has.
117 enum SelectSupportKind {
118 ScalarValSelect, // The target supports scalar selects (ex: cmov).
119 ScalarCondVectorVal, // The target supports selects with a scalar condition
120 // and vector values (ex: cmov).
121 VectorMaskSelect // The target supports vector selects with a vector
122 // mask (ex: x86 blends).
125 static ISD::NodeType getExtendForContent(BooleanContent Content) {
127 case UndefinedBooleanContent:
128 // Extend by adding rubbish bits.
129 return ISD::ANY_EXTEND;
130 case ZeroOrOneBooleanContent:
131 // Extend by adding zero bits.
132 return ISD::ZERO_EXTEND;
133 case ZeroOrNegativeOneBooleanContent:
134 // Extend by copying the sign bit.
135 return ISD::SIGN_EXTEND;
137 llvm_unreachable("Invalid content kind");
140 /// NOTE: The constructor takes ownership of TLOF.
141 explicit TargetLoweringBase(const TargetMachine &TM,
142 const TargetLoweringObjectFile *TLOF);
143 virtual ~TargetLoweringBase();
146 /// \brief Initialize all of the actions to default values.
150 const TargetMachine &getTargetMachine() const { return TM; }
151 const DataLayout *getDataLayout() const { return DL; }
152 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
154 bool isBigEndian() const { return !IsLittleEndian; }
155 bool isLittleEndian() const { return IsLittleEndian; }
157 /// Return the pointer type for the given address space, defaults to
158 /// the pointer type from the data layout.
159 /// FIXME: The default needs to be removed once all the code is updated.
160 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const;
161 unsigned getPointerSizeInBits(uint32_t AS = 0) const;
162 unsigned getPointerTypeSizeInBits(Type *Ty) const;
163 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
165 EVT getShiftAmountTy(EVT LHSTy) const;
167 /// Returns the type to be used for the index operand of:
168 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
169 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
170 virtual MVT getVectorIdxTy() const {
171 return getPointerTy();
174 /// Return true if the select operation is expensive for this target.
175 bool isSelectExpensive() const { return SelectIsExpensive; }
177 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
181 /// Return true if multiple condition registers are available.
182 bool hasMultipleConditionRegisters() const {
183 return HasMultipleConditionRegisters;
186 /// Return true if the target has BitExtract instructions.
187 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
189 /// Return the preferred vector type legalization action.
190 virtual TargetLoweringBase::LegalizeTypeAction
191 getPreferredVectorAction(EVT VT) const {
192 // The default action for one element vectors is to scalarize
193 if (VT.getVectorNumElements() == 1)
194 return TypeScalarizeVector;
195 // The default action for other vectors is to promote
196 return TypePromoteInteger;
199 // There are two general methods for expanding a BUILD_VECTOR node:
200 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
202 // 2. Build the vector on the stack and then load it.
203 // If this function returns true, then method (1) will be used, subject to
204 // the constraint that all of the necessary shuffles are legal (as determined
205 // by isShuffleMaskLegal). If this function returns false, then method (2) is
206 // always used. The vector type, and the number of defined values, are
209 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
210 unsigned DefinedValues) const {
211 return DefinedValues < 3;
214 /// Return true if integer divide is usually cheaper than a sequence of
215 /// several shifts, adds, and multiplies for this target.
216 bool isIntDivCheap() const { return IntDivIsCheap; }
218 /// Returns true if target has indicated at least one type should be bypassed.
219 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
221 /// Returns map of slow types for division or remainder with corresponding
223 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
224 return BypassSlowDivWidths;
227 /// Return true if pow2 sdiv is cheaper than a chain of sra/srl/add/sra.
228 bool isPow2SDivCheap() const { return Pow2SDivIsCheap; }
230 /// Return true if Flow Control is an expensive operation that should be
232 bool isJumpExpensive() const { return JumpIsExpensive; }
234 /// Return true if selects are only cheaper than branches if the branch is
235 /// unlikely to be predicted right.
236 bool isPredictableSelectExpensive() const {
237 return PredictableSelectIsExpensive;
240 /// isLoadBitCastBeneficial() - Return true if the following transform
242 /// fold (conv (load x)) -> (load (conv*)x)
243 /// On architectures that don't natively support some vector loads efficiently,
244 /// casting the load to a smaller vector of larger types and loading
245 /// is more efficient, however, this can be undone by optimizations in
247 virtual bool isLoadBitCastBeneficial(EVT /* Load */, EVT /* Bitcast */) const {
251 /// \brief Return if the target supports combining a
254 /// %andResult = and %val1, #imm-with-one-bit-set;
255 /// %icmpResult = icmp %andResult, 0
256 /// br i1 %icmpResult, label %dest1, label %dest2
258 /// into a single machine instruction of a form like:
260 /// brOnBitSet %register, #bitNumber, dest
262 bool isMaskAndBranchFoldingLegal() const {
263 return MaskAndBranchFoldingIsLegal;
266 /// Return true if target supports floating point exceptions.
267 bool hasFloatingPointExceptions() const {
268 return HasFloatingPointExceptions;
271 /// Return true if target always beneficiates from combining into FMA for a
272 /// given value type. This must typically return false on targets where FMA
273 /// takes more cycles to execute than FADD.
274 virtual bool enableAggressiveFMAFusion(EVT VT) const {
278 /// Return the ValueType of the result of SETCC operations. Also used to
279 /// obtain the target's preferred type for the condition operand of SELECT and
280 /// BRCOND nodes. In the case of BRCOND the argument passed is MVT::Other
281 /// since there are no other operands to get a type hint from.
282 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
284 /// Return the ValueType for comparison libcalls. Comparions libcalls include
285 /// floating point comparion calls, and Ordered/Unordered check calls on
286 /// floating point numbers.
288 MVT::SimpleValueType getCmpLibcallReturnType() const;
290 /// For targets without i1 registers, this gives the nature of the high-bits
291 /// of boolean values held in types wider than i1.
293 /// "Boolean values" are special true/false values produced by nodes like
294 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
295 /// Not to be confused with general values promoted from i1. Some cpus
296 /// distinguish between vectors of boolean and scalars; the isVec parameter
297 /// selects between the two kinds. For example on X86 a scalar boolean should
298 /// be zero extended from i1, while the elements of a vector of booleans
299 /// should be sign extended from i1.
301 /// Some cpus also treat floating point types the same way as they treat
302 /// vectors instead of the way they treat scalars.
303 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
305 return BooleanVectorContents;
306 return isFloat ? BooleanFloatContents : BooleanContents;
309 BooleanContent getBooleanContents(EVT Type) const {
310 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
313 /// Return target scheduling preference.
314 Sched::Preference getSchedulingPreference() const {
315 return SchedPreferenceInfo;
318 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
319 /// for different nodes. This function returns the preference (or none) for
321 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
325 /// Return the register class that should be used for the specified value
327 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
328 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
329 assert(RC && "This value type is not natively supported!");
333 /// Return the 'representative' register class for the specified value
336 /// The 'representative' register class is the largest legal super-reg
337 /// register class for the register class of the value type. For example, on
338 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
339 /// register class is GR64 on x86_64.
340 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
341 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
345 /// Return the cost of the 'representative' register class for the specified
347 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
348 return RepRegClassCostForVT[VT.SimpleTy];
351 /// Return true if the target has native support for the specified value type.
352 /// This means that it has a register that directly holds it without
353 /// promotions or expansions.
354 bool isTypeLegal(EVT VT) const {
355 assert(!VT.isSimple() ||
356 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
357 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
360 class ValueTypeActionImpl {
361 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
362 /// that indicates how instruction selection should deal with the type.
363 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
366 ValueTypeActionImpl() {
367 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions), 0);
370 LegalizeTypeAction getTypeAction(MVT VT) const {
371 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
374 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
375 unsigned I = VT.SimpleTy;
376 ValueTypeActions[I] = Action;
380 const ValueTypeActionImpl &getValueTypeActions() const {
381 return ValueTypeActions;
384 /// Return how we should legalize values of this type, either it is already
385 /// legal (return 'Legal') or we need to promote it to a larger type (return
386 /// 'Promote'), or we need to expand it into multiple registers of smaller
387 /// integer type (return 'Expand'). 'Custom' is not an option.
388 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
389 return getTypeConversion(Context, VT).first;
391 LegalizeTypeAction getTypeAction(MVT VT) const {
392 return ValueTypeActions.getTypeAction(VT);
395 /// For types supported by the target, this is an identity function. For
396 /// types that must be promoted to larger types, this returns the larger type
397 /// to promote to. For integer types that are larger than the largest integer
398 /// register, this contains one step in the expansion to get to the smaller
399 /// register. For illegal floating point types, this returns the integer type
401 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
402 return getTypeConversion(Context, VT).second;
405 /// For types supported by the target, this is an identity function. For
406 /// types that must be expanded (i.e. integer types that are larger than the
407 /// largest integer register or illegal floating point types), this returns
408 /// the largest legal type it will be expanded to.
409 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
410 assert(!VT.isVector());
412 switch (getTypeAction(Context, VT)) {
415 case TypeExpandInteger:
416 VT = getTypeToTransformTo(Context, VT);
419 llvm_unreachable("Type is not legal nor is it to be expanded!");
424 /// Vector types are broken down into some number of legal first class types.
425 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
426 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
427 /// turns into 4 EVT::i32 values with both PPC and X86.
429 /// This method returns the number of registers needed, and the VT for each
430 /// register. It also returns the VT and quantity of the intermediate values
431 /// before they are promoted/expanded.
432 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
434 unsigned &NumIntermediates,
435 MVT &RegisterVT) const;
437 struct IntrinsicInfo {
438 unsigned opc; // target opcode
439 EVT memVT; // memory VT
440 const Value* ptrVal; // value representing memory location
441 int offset; // offset off of ptrVal
442 unsigned size; // the size of the memory location
443 // (taken from memVT if zero)
444 unsigned align; // alignment
445 bool vol; // is volatile?
446 bool readMem; // reads memory?
447 bool writeMem; // writes memory?
449 IntrinsicInfo() : opc(0), ptrVal(nullptr), offset(0), size(0), align(1),
450 vol(false), readMem(false), writeMem(false) {}
453 /// Given an intrinsic, checks if on the target the intrinsic will need to map
454 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
455 /// true and store the intrinsic information into the IntrinsicInfo that was
456 /// passed to the function.
457 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
458 unsigned /*Intrinsic*/) const {
462 /// Returns true if the target can instruction select the specified FP
463 /// immediate natively. If false, the legalizer will materialize the FP
464 /// immediate as a load from a constant pool.
465 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
469 /// Targets can use this to indicate that they only support *some*
470 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
471 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
473 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
478 /// Returns true if the operation can trap for the value type.
480 /// VT must be a legal type. By default, we optimistically assume most
481 /// operations don't trap except for divide and remainder.
482 virtual bool canOpTrap(unsigned Op, EVT VT) const;
484 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
485 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
486 /// a VAND with a constant pool entry.
487 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
492 /// Return how this operation should be treated: either it is legal, needs to
493 /// be promoted to a larger size, needs to be expanded to some other code
494 /// sequence, or the target has a custom expander for it.
495 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
496 if (VT.isExtended()) return Expand;
497 // If a target-specific SDNode requires legalization, require the target
498 // to provide custom legalization for it.
499 if (Op > array_lengthof(OpActions[0])) return Custom;
500 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
501 return (LegalizeAction)OpActions[I][Op];
504 /// Return true if the specified operation is legal on this target or can be
505 /// made legal with custom lowering. This is used to help guide high-level
506 /// lowering decisions.
507 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
508 return (VT == MVT::Other || isTypeLegal(VT)) &&
509 (getOperationAction(Op, VT) == Legal ||
510 getOperationAction(Op, VT) == Custom);
513 /// Return true if the specified operation is legal on this target or can be
514 /// made legal using promotion. This is used to help guide high-level lowering
516 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
517 return (VT == MVT::Other || isTypeLegal(VT)) &&
518 (getOperationAction(Op, VT) == Legal ||
519 getOperationAction(Op, VT) == Promote);
522 /// Return true if the specified operation is illegal on this target or
523 /// unlikely to be made legal with custom lowering. This is used to help guide
524 /// high-level lowering decisions.
525 bool isOperationExpand(unsigned Op, EVT VT) const {
526 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
529 /// Return true if the specified operation is legal on this target.
530 bool isOperationLegal(unsigned Op, EVT VT) const {
531 return (VT == MVT::Other || isTypeLegal(VT)) &&
532 getOperationAction(Op, VT) == Legal;
535 /// Return how this load with extension should be treated: either it is legal,
536 /// needs to be promoted to a larger size, needs to be expanded to some other
537 /// code sequence, or the target has a custom expander for it.
538 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const {
539 if (VT.isExtended()) return Expand;
540 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
541 assert(ExtType < ISD::LAST_LOADEXT_TYPE && I < MVT::LAST_VALUETYPE &&
542 "Table isn't big enough!");
543 return (LegalizeAction)LoadExtActions[I][ExtType];
546 /// Return true if the specified load with extension is legal on this target.
547 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
548 return VT.isSimple() &&
549 getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
552 /// Return how this store with truncation should be treated: either it is
553 /// legal, needs to be promoted to a larger size, needs to be expanded to some
554 /// other code sequence, or the target has a custom expander for it.
555 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
556 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
557 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
558 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
559 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
560 "Table isn't big enough!");
561 return (LegalizeAction)TruncStoreActions[ValI][MemI];
564 /// Return true if the specified store with truncation is legal on this
566 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
567 return isTypeLegal(ValVT) && MemVT.isSimple() &&
568 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
571 /// Return how the indexed load should be treated: either it is legal, needs
572 /// to be promoted to a larger size, needs to be expanded to some other code
573 /// sequence, or the target has a custom expander for it.
575 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
576 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
577 "Table isn't big enough!");
578 unsigned Ty = (unsigned)VT.SimpleTy;
579 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
582 /// Return true if the specified indexed load is legal on this target.
583 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
584 return VT.isSimple() &&
585 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
586 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
589 /// Return how the indexed store should be treated: either it is legal, needs
590 /// to be promoted to a larger size, needs to be expanded to some other code
591 /// sequence, or the target has a custom expander for it.
593 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
594 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
595 "Table isn't big enough!");
596 unsigned Ty = (unsigned)VT.SimpleTy;
597 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
600 /// Return true if the specified indexed load is legal on this target.
601 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
602 return VT.isSimple() &&
603 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
604 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
607 /// Return how the condition code should be treated: either it is legal, needs
608 /// to be expanded to some other code sequence, or the target has a custom
611 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
612 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
613 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
614 "Table isn't big enough!");
615 // See setCondCodeAction for how this is encoded.
616 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
617 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
618 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
619 assert(Action != Promote && "Can't promote condition code!");
623 /// Return true if the specified condition code is legal on this target.
624 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
626 getCondCodeAction(CC, VT) == Legal ||
627 getCondCodeAction(CC, VT) == Custom;
631 /// If the action for this operation is to promote, this method returns the
632 /// ValueType to promote to.
633 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
634 assert(getOperationAction(Op, VT) == Promote &&
635 "This operation isn't promoted!");
637 // See if this has an explicit type specified.
638 std::map<std::pair<unsigned, MVT::SimpleValueType>,
639 MVT::SimpleValueType>::const_iterator PTTI =
640 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
641 if (PTTI != PromoteToType.end()) return PTTI->second;
643 assert((VT.isInteger() || VT.isFloatingPoint()) &&
644 "Cannot autopromote this type, add it with AddPromotedToType.");
648 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
649 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
650 "Didn't find type to promote to!");
651 } while (!isTypeLegal(NVT) ||
652 getOperationAction(Op, NVT) == Promote);
656 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
657 /// operations except for the pointer size. If AllowUnknown is true, this
658 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
659 /// otherwise it will assert.
660 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
661 // Lower scalar pointers to native pointer types.
662 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
663 return getPointerTy(PTy->getAddressSpace());
665 if (Ty->isVectorTy()) {
666 VectorType *VTy = cast<VectorType>(Ty);
667 Type *Elm = VTy->getElementType();
668 // Lower vectors of pointers to native pointer types.
669 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
670 EVT PointerTy(getPointerTy(PT->getAddressSpace()));
671 Elm = PointerTy.getTypeForEVT(Ty->getContext());
674 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
675 VTy->getNumElements());
677 return EVT::getEVT(Ty, AllowUnknown);
680 /// Return the MVT corresponding to this LLVM type. See getValueType.
681 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
682 return getValueType(Ty, AllowUnknown).getSimpleVT();
685 /// Return the desired alignment for ByVal or InAlloca aggregate function
686 /// arguments in the caller parameter area. This is the actual alignment, not
688 virtual unsigned getByValTypeAlignment(Type *Ty) const;
690 /// Return the type of registers that this ValueType will eventually require.
691 MVT getRegisterType(MVT VT) const {
692 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
693 return RegisterTypeForVT[VT.SimpleTy];
696 /// Return the type of registers that this ValueType will eventually require.
697 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
699 assert((unsigned)VT.getSimpleVT().SimpleTy <
700 array_lengthof(RegisterTypeForVT));
701 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
706 unsigned NumIntermediates;
707 (void)getVectorTypeBreakdown(Context, VT, VT1,
708 NumIntermediates, RegisterVT);
711 if (VT.isInteger()) {
712 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
714 llvm_unreachable("Unsupported extended type!");
717 /// Return the number of registers that this ValueType will eventually
720 /// This is one for any types promoted to live in larger registers, but may be
721 /// more than one for types (like i64) that are split into pieces. For types
722 /// like i140, which are first promoted then expanded, it is the number of
723 /// registers needed to hold all the bits of the original type. For an i140
724 /// on a 32 bit machine this means 5 registers.
725 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
727 assert((unsigned)VT.getSimpleVT().SimpleTy <
728 array_lengthof(NumRegistersForVT));
729 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
734 unsigned NumIntermediates;
735 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
737 if (VT.isInteger()) {
738 unsigned BitWidth = VT.getSizeInBits();
739 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
740 return (BitWidth + RegWidth - 1) / RegWidth;
742 llvm_unreachable("Unsupported extended type!");
745 /// If true, then instruction selection should seek to shrink the FP constant
746 /// of the specified type to a smaller type in order to save space and / or
748 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
750 /// When splitting a value of the specified type into parts, does the Lo
751 /// or Hi part come first? This usually follows the endianness, except
752 /// for ppcf128, where the Hi part always comes first.
753 bool hasBigEndianPartOrdering(EVT VT) const {
754 return isBigEndian() || VT == MVT::ppcf128;
757 /// If true, the target has custom DAG combine transformations that it can
758 /// perform for the specified node.
759 bool hasTargetDAGCombine(ISD::NodeType NT) const {
760 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
761 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
764 /// \brief Get maximum # of store operations permitted for llvm.memset
766 /// This function returns the maximum number of store operations permitted
767 /// to replace a call to llvm.memset. The value is set by the target at the
768 /// performance threshold for such a replacement. If OptSize is true,
769 /// return the limit for functions that have OptSize attribute.
770 unsigned getMaxStoresPerMemset(bool OptSize) const {
771 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
774 /// \brief Get maximum # of store operations permitted for llvm.memcpy
776 /// This function returns the maximum number of store operations permitted
777 /// to replace a call to llvm.memcpy. The value is set by the target at the
778 /// performance threshold for such a replacement. If OptSize is true,
779 /// return the limit for functions that have OptSize attribute.
780 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
781 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
784 /// \brief Get maximum # of store operations permitted for llvm.memmove
786 /// This function returns the maximum number of store operations permitted
787 /// to replace a call to llvm.memmove. The value is set by the target at the
788 /// performance threshold for such a replacement. If OptSize is true,
789 /// return the limit for functions that have OptSize attribute.
790 unsigned getMaxStoresPerMemmove(bool OptSize) const {
791 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
794 /// \brief Determine if the target supports unaligned memory accesses.
796 /// This function returns true if the target allows unaligned memory accesses
797 /// of the specified type in the given address space. If true, it also returns
798 /// whether the unaligned memory access is "fast" in the last argument by
799 /// reference. This is used, for example, in situations where an array
800 /// copy/move/set is converted to a sequence of store operations. Its use
801 /// helps to ensure that such replacements don't generate code that causes an
802 /// alignment error (trap) on the target machine.
803 virtual bool allowsMisalignedMemoryAccesses(EVT,
804 unsigned AddrSpace = 0,
806 bool * /*Fast*/ = nullptr) const {
810 /// Returns the target specific optimal type for load and store operations as
811 /// a result of memset, memcpy, and memmove lowering.
813 /// If DstAlign is zero that means it's safe to destination alignment can
814 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
815 /// a need to check it against alignment requirement, probably because the
816 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
817 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
818 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
819 /// does not need to be loaded. It returns EVT::Other if the type should be
820 /// determined using generic target-independent logic.
821 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
822 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
825 bool /*MemcpyStrSrc*/,
826 MachineFunction &/*MF*/) const {
830 /// Returns true if it's safe to use load / store of the specified type to
831 /// expand memcpy / memset inline.
833 /// This is mostly true for all types except for some special cases. For
834 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
835 /// fstpl which also does type conversion. Note the specified type doesn't
836 /// have to be legal as the hook is used before type legalization.
837 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
839 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
840 bool usesUnderscoreSetJmp() const {
841 return UseUnderscoreSetJmp;
844 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
845 bool usesUnderscoreLongJmp() const {
846 return UseUnderscoreLongJmp;
849 /// Return integer threshold on number of blocks to use jump tables rather
850 /// than if sequence.
851 int getMinimumJumpTableEntries() const {
852 return MinimumJumpTableEntries;
855 /// If a physical register, this specifies the register that
856 /// llvm.savestack/llvm.restorestack should save and restore.
857 unsigned getStackPointerRegisterToSaveRestore() const {
858 return StackPointerRegisterToSaveRestore;
861 /// If a physical register, this returns the register that receives the
862 /// exception address on entry to a landing pad.
863 unsigned getExceptionPointerRegister() const {
864 return ExceptionPointerRegister;
867 /// If a physical register, this returns the register that receives the
868 /// exception typeid on entry to a landing pad.
869 unsigned getExceptionSelectorRegister() const {
870 return ExceptionSelectorRegister;
873 /// Returns the target's jmp_buf size in bytes (if never set, the default is
875 unsigned getJumpBufSize() const {
879 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
881 unsigned getJumpBufAlignment() const {
882 return JumpBufAlignment;
885 /// Return the minimum stack alignment of an argument.
886 unsigned getMinStackArgumentAlignment() const {
887 return MinStackArgumentAlignment;
890 /// Return the minimum function alignment.
891 unsigned getMinFunctionAlignment() const {
892 return MinFunctionAlignment;
895 /// Return the preferred function alignment.
896 unsigned getPrefFunctionAlignment() const {
897 return PrefFunctionAlignment;
900 /// Return the preferred loop alignment.
901 unsigned getPrefLoopAlignment() const {
902 return PrefLoopAlignment;
905 /// Return whether the DAG builder should automatically insert fences and
906 /// reduce ordering for atomics.
907 bool getInsertFencesForAtomic() const {
908 return InsertFencesForAtomic;
911 /// Return true if the target stores stack protector cookies at a fixed offset
912 /// in some non-standard address space, and populates the address space and
913 /// offset as appropriate.
914 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
915 unsigned &/*Offset*/) const {
919 /// Returns the maximal possible offset which can be used for loads / stores
921 virtual unsigned getMaximalGlobalOffset() const {
925 /// Returns true if a cast between SrcAS and DestAS is a noop.
926 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
930 //===--------------------------------------------------------------------===//
931 /// \name Helpers for TargetTransformInfo implementations
934 /// Get the ISD node that corresponds to the Instruction class opcode.
935 int InstructionOpcodeToISD(unsigned Opcode) const;
937 /// Estimate the cost of type-legalization and the legalized type.
938 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;
942 //===--------------------------------------------------------------------===//
943 /// \name Helpers for atomic expansion.
946 /// True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional
947 /// and expand AtomicCmpXchgInst.
948 virtual bool hasLoadLinkedStoreConditional() const { return false; }
950 /// Perform a load-linked operation on Addr, returning a "Value *" with the
951 /// corresponding pointee type. This may entail some non-trivial operations to
952 /// truncate or reconstruct types that will be illegal in the backend. See
953 /// ARMISelLowering for an example implementation.
954 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
955 AtomicOrdering Ord) const {
956 llvm_unreachable("Load linked unimplemented on this target");
959 /// Perform a store-conditional operation to Addr. Return the status of the
960 /// store. This should be 0 if the store succeeded, non-zero otherwise.
961 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
962 Value *Addr, AtomicOrdering Ord) const {
963 llvm_unreachable("Store conditional unimplemented on this target");
966 /// Inserts in the IR a target-specific intrinsic specifying a fence.
967 /// It is called by AtomicExpandPass before expanding an
968 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad.
969 /// RMW and CmpXchg set both IsStore and IsLoad to true.
970 /// Backends with !getInsertFencesForAtomic() should keep a no-op here.
971 /// This function should either return a nullptr, or a pointer to an IR-level
972 /// Instruction*. Even complex fence sequences can be represented by a
973 /// single Instruction* through an intrinsic to be lowered later.
974 virtual Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
975 bool IsStore, bool IsLoad) const {
976 assert(!getInsertFencesForAtomic());
980 /// Inserts in the IR a target-specific intrinsic specifying a fence.
981 /// It is called by AtomicExpandPass after expanding an
982 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad.
983 /// RMW and CmpXchg set both IsStore and IsLoad to true.
984 /// Backends with !getInsertFencesForAtomic() should keep a no-op here.
985 /// This function should either return a nullptr, or a pointer to an IR-level
986 /// Instruction*. Even complex fence sequences can be represented by a
987 /// single Instruction* through an intrinsic to be lowered later.
988 virtual Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
989 bool IsStore, bool IsLoad) const {
990 assert(!getInsertFencesForAtomic());
994 /// Returns true if the given (atomic) store should be expanded by the
995 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
996 virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1000 /// Returns true if the given (atomic) load should be expanded by the
1001 /// IR-level AtomicExpand pass into a load-linked instruction
1002 /// (through emitLoadLinked()).
1003 virtual bool shouldExpandAtomicLoadInIR(LoadInst *LI) const { return false; }
1005 /// Returns true if the given AtomicRMW should be expanded by the
1006 /// IR-level AtomicExpand pass into a loop using LoadLinked/StoreConditional.
1007 virtual bool shouldExpandAtomicRMWInIR(AtomicRMWInst *RMWI) const {
1011 //===--------------------------------------------------------------------===//
1012 // TargetLowering Configuration Methods - These methods should be invoked by
1013 // the derived class constructor to configure this object for the target.
1016 /// \brief Reset the operation actions based on target options.
1017 virtual void resetOperationActions() {}
1020 /// Specify how the target extends the result of integer and floating point
1021 /// boolean values from i1 to a wider type. See getBooleanContents.
1022 void setBooleanContents(BooleanContent Ty) {
1023 BooleanContents = Ty;
1024 BooleanFloatContents = Ty;
1027 /// Specify how the target extends the result of integer and floating point
1028 /// boolean values from i1 to a wider type. See getBooleanContents.
1029 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1030 BooleanContents = IntTy;
1031 BooleanFloatContents = FloatTy;
1034 /// Specify how the target extends the result of a vector boolean value from a
1035 /// vector of i1 to a wider type. See getBooleanContents.
1036 void setBooleanVectorContents(BooleanContent Ty) {
1037 BooleanVectorContents = Ty;
1040 /// Specify the target scheduling preference.
1041 void setSchedulingPreference(Sched::Preference Pref) {
1042 SchedPreferenceInfo = Pref;
1045 /// Indicate whether this target prefers to use _setjmp to implement
1046 /// llvm.setjmp or the version without _. Defaults to false.
1047 void setUseUnderscoreSetJmp(bool Val) {
1048 UseUnderscoreSetJmp = Val;
1051 /// Indicate whether this target prefers to use _longjmp to implement
1052 /// llvm.longjmp or the version without _. Defaults to false.
1053 void setUseUnderscoreLongJmp(bool Val) {
1054 UseUnderscoreLongJmp = Val;
1057 /// Indicate the number of blocks to generate jump tables rather than if
1059 void setMinimumJumpTableEntries(int Val) {
1060 MinimumJumpTableEntries = Val;
1063 /// If set to a physical register, this specifies the register that
1064 /// llvm.savestack/llvm.restorestack should save and restore.
1065 void setStackPointerRegisterToSaveRestore(unsigned R) {
1066 StackPointerRegisterToSaveRestore = R;
1069 /// If set to a physical register, this sets the register that receives the
1070 /// exception address on entry to a landing pad.
1071 void setExceptionPointerRegister(unsigned R) {
1072 ExceptionPointerRegister = R;
1075 /// If set to a physical register, this sets the register that receives the
1076 /// exception typeid on entry to a landing pad.
1077 void setExceptionSelectorRegister(unsigned R) {
1078 ExceptionSelectorRegister = R;
1081 /// Tells the code generator not to expand operations into sequences that use
1082 /// the select operations if possible.
1083 void setSelectIsExpensive(bool isExpensive = true) {
1084 SelectIsExpensive = isExpensive;
1087 /// Tells the code generator that the target has multiple (allocatable)
1088 /// condition registers that can be used to store the results of comparisons
1089 /// for use by selects and conditional branches. With multiple condition
1090 /// registers, the code generator will not aggressively sink comparisons into
1091 /// the blocks of their users.
1092 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1093 HasMultipleConditionRegisters = hasManyRegs;
1096 /// Tells the code generator that the target has BitExtract instructions.
1097 /// The code generator will aggressively sink "shift"s into the blocks of
1098 /// their users if the users will generate "and" instructions which can be
1099 /// combined with "shift" to BitExtract instructions.
1100 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1101 HasExtractBitsInsn = hasExtractInsn;
1104 /// Tells the code generator not to expand sequence of operations into a
1105 /// separate sequences that increases the amount of flow control.
1106 void setJumpIsExpensive(bool isExpensive = true) {
1107 JumpIsExpensive = isExpensive;
1110 /// Tells the code generator that integer divide is expensive, and if
1111 /// possible, should be replaced by an alternate sequence of instructions not
1112 /// containing an integer divide.
1113 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1115 /// Tells the code generator that this target supports floating point
1116 /// exceptions and cares about preserving floating point exception behavior.
1117 void setHasFloatingPointExceptions(bool FPExceptions = true) {
1118 HasFloatingPointExceptions = FPExceptions;
1121 /// Tells the code generator which bitwidths to bypass.
1122 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1123 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1126 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1127 /// signed divide by power of two; let the target handle it.
1128 void setPow2SDivIsCheap(bool isCheap = true) { Pow2SDivIsCheap = isCheap; }
1130 /// Add the specified register class as an available regclass for the
1131 /// specified value type. This indicates the selector can handle values of
1132 /// that class natively.
1133 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1134 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1135 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1136 RegClassForVT[VT.SimpleTy] = RC;
1139 /// Remove all register classes.
1140 void clearRegisterClasses() {
1141 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1143 AvailableRegClasses.clear();
1146 /// \brief Remove all operation actions.
1147 void clearOperationActions() {
1150 /// Return the largest legal super-reg register class of the register class
1151 /// for the specified type and its associated "cost".
1152 virtual std::pair<const TargetRegisterClass*, uint8_t>
1153 findRepresentativeClass(MVT VT) const;
1155 /// Once all of the register classes are added, this allows us to compute
1156 /// derived properties we expose.
1157 void computeRegisterProperties();
1159 /// Indicate that the specified operation does not work with the specified
1160 /// type and indicate what to do about it.
1161 void setOperationAction(unsigned Op, MVT VT,
1162 LegalizeAction Action) {
1163 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1164 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1167 /// Indicate that the specified load with extension does not work with the
1168 /// specified type and indicate what to do about it.
1169 void setLoadExtAction(unsigned ExtType, MVT VT,
1170 LegalizeAction Action) {
1171 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
1172 "Table isn't big enough!");
1173 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1176 /// Indicate that the specified truncating store does not work with the
1177 /// specified type and indicate what to do about it.
1178 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1179 LegalizeAction Action) {
1180 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
1181 "Table isn't big enough!");
1182 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1185 /// Indicate that the specified indexed load does or does not work with the
1186 /// specified type and indicate what to do abort it.
1188 /// NOTE: All indexed mode loads are initialized to Expand in
1189 /// TargetLowering.cpp
1190 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1191 LegalizeAction Action) {
1192 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1193 (unsigned)Action < 0xf && "Table isn't big enough!");
1194 // Load action are kept in the upper half.
1195 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1196 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1199 /// Indicate that the specified indexed store does or does not work with the
1200 /// specified type and indicate what to do about it.
1202 /// NOTE: All indexed mode stores are initialized to Expand in
1203 /// TargetLowering.cpp
1204 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1205 LegalizeAction Action) {
1206 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1207 (unsigned)Action < 0xf && "Table isn't big enough!");
1208 // Store action are kept in the lower half.
1209 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1210 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1213 /// Indicate that the specified condition code is or isn't supported on the
1214 /// target and indicate what to do about it.
1215 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1216 LegalizeAction Action) {
1217 assert(VT < MVT::LAST_VALUETYPE &&
1218 (unsigned)CC < array_lengthof(CondCodeActions) &&
1219 "Table isn't big enough!");
1220 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1221 /// value and the upper 27 bits index into the second dimension of the array
1222 /// to select what 32-bit value to use.
1223 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1224 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1225 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1228 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1229 /// to trying a larger integer/fp until it can find one that works. If that
1230 /// default is insufficient, this method can be used by the target to override
1232 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1233 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1236 /// Targets should invoke this method for each target independent node that
1237 /// they want to provide a custom DAG combiner for by implementing the
1238 /// PerformDAGCombine virtual method.
1239 void setTargetDAGCombine(ISD::NodeType NT) {
1240 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1241 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1244 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1245 void setJumpBufSize(unsigned Size) {
1249 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1251 void setJumpBufAlignment(unsigned Align) {
1252 JumpBufAlignment = Align;
1255 /// Set the target's minimum function alignment (in log2(bytes))
1256 void setMinFunctionAlignment(unsigned Align) {
1257 MinFunctionAlignment = Align;
1260 /// Set the target's preferred function alignment. This should be set if
1261 /// there is a performance benefit to higher-than-minimum alignment (in
1263 void setPrefFunctionAlignment(unsigned Align) {
1264 PrefFunctionAlignment = Align;
1267 /// Set the target's preferred loop alignment. Default alignment is zero, it
1268 /// means the target does not care about loop alignment. The alignment is
1269 /// specified in log2(bytes).
1270 void setPrefLoopAlignment(unsigned Align) {
1271 PrefLoopAlignment = Align;
1274 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1275 void setMinStackArgumentAlignment(unsigned Align) {
1276 MinStackArgumentAlignment = Align;
1279 /// Set if the DAG builder should automatically insert fences and reduce the
1280 /// order of atomic memory operations to Monotonic.
1281 void setInsertFencesForAtomic(bool fence) {
1282 InsertFencesForAtomic = fence;
1286 //===--------------------------------------------------------------------===//
1287 // Addressing mode description hooks (used by LSR etc).
1290 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1291 /// instructions reading the address. This allows as much computation as
1292 /// possible to be done in the address mode for that operand. This hook lets
1293 /// targets also pass back when this should be done on intrinsics which
1295 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1296 SmallVectorImpl<Value*> &/*Ops*/,
1297 Type *&/*AccessTy*/) const {
1301 /// This represents an addressing mode of:
1302 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1303 /// If BaseGV is null, there is no BaseGV.
1304 /// If BaseOffs is zero, there is no base offset.
1305 /// If HasBaseReg is false, there is no base register.
1306 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1309 GlobalValue *BaseGV;
1313 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1316 /// Return true if the addressing mode represented by AM is legal for this
1317 /// target, for a load/store of the specified type.
1319 /// The type may be VoidTy, in which case only return true if the addressing
1320 /// mode is legal for a load/store of any legal type. TODO: Handle
1321 /// pre/postinc as well.
1322 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1324 /// \brief Return the cost of the scaling factor used in the addressing mode
1325 /// represented by AM for this target, for a load/store of the specified type.
1327 /// If the AM is supported, the return value must be >= 0.
1328 /// If the AM is not supported, it returns a negative value.
1329 /// TODO: Handle pre/postinc as well.
1330 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const {
1331 // Default: assume that any scaling factor used in a legal AM is free.
1332 if (isLegalAddressingMode(AM, Ty)) return 0;
1336 /// Return true if the specified immediate is legal icmp immediate, that is
1337 /// the target has icmp instructions which can compare a register against the
1338 /// immediate without having to materialize the immediate into a register.
1339 virtual bool isLegalICmpImmediate(int64_t) const {
1343 /// Return true if the specified immediate is legal add immediate, that is the
1344 /// target has add instructions which can add a register with the immediate
1345 /// without having to materialize the immediate into a register.
1346 virtual bool isLegalAddImmediate(int64_t) const {
1350 /// Return true if it's significantly cheaper to shift a vector by a uniform
1351 /// scalar than by an amount which will vary across each lane. On x86, for
1352 /// example, there is a "psllw" instruction for the former case, but no simple
1353 /// instruction for a general "a << b" operation on vectors.
1354 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1358 /// Return true if it's free to truncate a value of type Ty1 to type
1359 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1360 /// by referencing its sub-register AX.
1361 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1365 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding
1366 /// whether a call is in tail position. Typically this means that both results
1367 /// would be assigned to the same register or stack slot, but it could mean
1368 /// the target performs adequate checks of its own before proceeding with the
1370 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const {
1374 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1378 /// Return true if any actual instruction that defines a value of type Ty1
1379 /// implicitly zero-extends the value to Ty2 in the result register.
1381 /// This does not necessarily include registers defined in unknown ways, such
1382 /// as incoming arguments, or copies from unknown virtual registers. Also, if
1383 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
1384 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit
1385 /// values implicit zero-extend the result out to 64 bits.
1386 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1390 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1394 /// Return true if the target supplies and combines to a paired load
1395 /// two loaded values of type LoadedType next to each other in memory.
1396 /// RequiredAlignment gives the minimal alignment constraints that must be met
1397 /// to be able to select this paired load.
1399 /// This information is *not* used to generate actual paired loads, but it is
1400 /// used to generate a sequence of loads that is easier to combine into a
1402 /// For instance, something like this:
1403 /// a = load i64* addr
1404 /// b = trunc i64 a to i32
1405 /// c = lshr i64 a, 32
1406 /// d = trunc i64 c to i32
1407 /// will be optimized into:
1408 /// b = load i32* addr1
1409 /// d = load i32* addr2
1410 /// Where addr1 = addr2 +/- sizeof(i32).
1412 /// In other words, unless the target performs a post-isel load combining,
1413 /// this information should not be provided because it will generate more
1415 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1416 unsigned & /*RequiredAligment*/) const {
1420 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1421 unsigned & /*RequiredAligment*/) const {
1425 /// Return true if zero-extending the specific node Val to type VT2 is free
1426 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1427 /// because it's folded such as X86 zero-extending loads).
1428 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1429 return isZExtFree(Val.getValueType(), VT2);
1432 /// Return true if an fneg operation is free to the point where it is never
1433 /// worthwhile to replace it with a bitwise operation.
1434 virtual bool isFNegFree(EVT VT) const {
1435 assert(VT.isFloatingPoint());
1439 /// Return true if an fabs operation is free to the point where it is never
1440 /// worthwhile to replace it with a bitwise operation.
1441 virtual bool isFAbsFree(EVT VT) const {
1442 assert(VT.isFloatingPoint());
1446 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1447 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1448 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1450 /// NOTE: This may be called before legalization on types for which FMAs are
1451 /// not legal, but should return true if those types will eventually legalize
1452 /// to types that support FMAs. After legalization, it will only be called on
1453 /// types that support FMAs (via Legal or Custom actions)
1454 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1458 /// Return true if it's profitable to narrow operations of type VT1 to
1459 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1461 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1465 /// \brief Return true if it is beneficial to convert a load of a constant to
1466 /// just the constant itself.
1467 /// On some targets it might be more efficient to use a combination of
1468 /// arithmetic instructions to materialize the constant instead of loading it
1469 /// from a constant pool.
1470 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1474 //===--------------------------------------------------------------------===//
1475 // Runtime Library hooks
1478 /// Rename the default libcall routine name for the specified libcall.
1479 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1480 LibcallRoutineNames[Call] = Name;
1483 /// Get the libcall routine name for the specified libcall.
1484 const char *getLibcallName(RTLIB::Libcall Call) const {
1485 return LibcallRoutineNames[Call];
1488 /// Override the default CondCode to be used to test the result of the
1489 /// comparison libcall against zero.
1490 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1491 CmpLibcallCCs[Call] = CC;
1494 /// Get the CondCode that's to be used to test the result of the comparison
1495 /// libcall against zero.
1496 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1497 return CmpLibcallCCs[Call];
1500 /// Set the CallingConv that should be used for the specified libcall.
1501 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1502 LibcallCallingConvs[Call] = CC;
1505 /// Get the CallingConv that should be used for the specified libcall.
1506 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1507 return LibcallCallingConvs[Call];
1511 const TargetMachine &TM;
1512 const DataLayout *DL;
1513 const TargetLoweringObjectFile &TLOF;
1515 /// True if this is a little endian target.
1516 bool IsLittleEndian;
1518 /// Tells the code generator not to expand operations into sequences that use
1519 /// the select operations if possible.
1520 bool SelectIsExpensive;
1522 /// Tells the code generator that the target has multiple (allocatable)
1523 /// condition registers that can be used to store the results of comparisons
1524 /// for use by selects and conditional branches. With multiple condition
1525 /// registers, the code generator will not aggressively sink comparisons into
1526 /// the blocks of their users.
1527 bool HasMultipleConditionRegisters;
1529 /// Tells the code generator that the target has BitExtract instructions.
1530 /// The code generator will aggressively sink "shift"s into the blocks of
1531 /// their users if the users will generate "and" instructions which can be
1532 /// combined with "shift" to BitExtract instructions.
1533 bool HasExtractBitsInsn;
1535 /// Tells the code generator not to expand integer divides by constants into a
1536 /// sequence of muls, adds, and shifts. This is a hack until a real cost
1537 /// model is in place. If we ever optimize for size, this will be set to true
1538 /// unconditionally.
1541 /// Tells the code generator to bypass slow divide or remainder
1542 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1543 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1544 /// div/rem when the operands are positive and less than 256.
1545 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1547 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1548 /// signed divide by power of two; let the target handle it.
1549 bool Pow2SDivIsCheap;
1551 /// Tells the code generator that it shouldn't generate extra flow control
1552 /// instructions and should attempt to combine flow control instructions via
1554 bool JumpIsExpensive;
1556 /// Whether the target supports or cares about preserving floating point
1557 /// exception behavior.
1558 bool HasFloatingPointExceptions;
1560 /// This target prefers to use _setjmp to implement llvm.setjmp.
1562 /// Defaults to false.
1563 bool UseUnderscoreSetJmp;
1565 /// This target prefers to use _longjmp to implement llvm.longjmp.
1567 /// Defaults to false.
1568 bool UseUnderscoreLongJmp;
1570 /// Number of blocks threshold to use jump tables.
1571 int MinimumJumpTableEntries;
1573 /// Information about the contents of the high-bits in boolean values held in
1574 /// a type wider than i1. See getBooleanContents.
1575 BooleanContent BooleanContents;
1577 /// Information about the contents of the high-bits in boolean values held in
1578 /// a type wider than i1. See getBooleanContents.
1579 BooleanContent BooleanFloatContents;
1581 /// Information about the contents of the high-bits in boolean vector values
1582 /// when the element type is wider than i1. See getBooleanContents.
1583 BooleanContent BooleanVectorContents;
1585 /// The target scheduling preference: shortest possible total cycles or lowest
1587 Sched::Preference SchedPreferenceInfo;
1589 /// The size, in bytes, of the target's jmp_buf buffers
1590 unsigned JumpBufSize;
1592 /// The alignment, in bytes, of the target's jmp_buf buffers
1593 unsigned JumpBufAlignment;
1595 /// The minimum alignment that any argument on the stack needs to have.
1596 unsigned MinStackArgumentAlignment;
1598 /// The minimum function alignment (used when optimizing for size, and to
1599 /// prevent explicitly provided alignment from leading to incorrect code).
1600 unsigned MinFunctionAlignment;
1602 /// The preferred function alignment (used when alignment unspecified and
1603 /// optimizing for speed).
1604 unsigned PrefFunctionAlignment;
1606 /// The preferred loop alignment.
1607 unsigned PrefLoopAlignment;
1609 /// Whether the DAG builder should automatically insert fences and reduce
1610 /// ordering for atomics. (This will be set for for most architectures with
1611 /// weak memory ordering.)
1612 bool InsertFencesForAtomic;
1614 /// If set to a physical register, this specifies the register that
1615 /// llvm.savestack/llvm.restorestack should save and restore.
1616 unsigned StackPointerRegisterToSaveRestore;
1618 /// If set to a physical register, this specifies the register that receives
1619 /// the exception address on entry to a landing pad.
1620 unsigned ExceptionPointerRegister;
1622 /// If set to a physical register, this specifies the register that receives
1623 /// the exception typeid on entry to a landing pad.
1624 unsigned ExceptionSelectorRegister;
1626 /// This indicates the default register class to use for each ValueType the
1627 /// target supports natively.
1628 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1629 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1630 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1632 /// This indicates the "representative" register class to use for each
1633 /// ValueType the target supports natively. This information is used by the
1634 /// scheduler to track register pressure. By default, the representative
1635 /// register class is the largest legal super-reg register class of the
1636 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1637 /// representative class would be GR32.
1638 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1640 /// This indicates the "cost" of the "representative" register class for each
1641 /// ValueType. The cost is used by the scheduler to approximate register
1643 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1645 /// For any value types we are promoting or expanding, this contains the value
1646 /// type that we are changing to. For Expanded types, this contains one step
1647 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1648 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1649 /// the same type (e.g. i32 -> i32).
1650 MVT TransformToType[MVT::LAST_VALUETYPE];
1652 /// For each operation and each value type, keep a LegalizeAction that
1653 /// indicates how instruction selection should deal with the operation. Most
1654 /// operations are Legal (aka, supported natively by the target), but
1655 /// operations that are not should be described. Note that operations on
1656 /// non-legal value types are not described here.
1657 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1659 /// For each load extension type and each value type, keep a LegalizeAction
1660 /// that indicates how instruction selection should deal with a load of a
1661 /// specific value type and extension type.
1662 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1664 /// For each value type pair keep a LegalizeAction that indicates whether a
1665 /// truncating store of a specific value type and truncating type is legal.
1666 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1668 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1669 /// that indicates how instruction selection should deal with the load /
1672 /// The first dimension is the value_type for the reference. The second
1673 /// dimension represents the various modes for load store.
1674 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1676 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1677 /// indicates how instruction selection should deal with the condition code.
1679 /// Because each CC action takes up 2 bits, we need to have the array size be
1680 /// large enough to fit all of the value types. This can be done by rounding
1681 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1682 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1684 ValueTypeActionImpl ValueTypeActions;
1688 getTypeConversion(LLVMContext &Context, EVT VT) const {
1689 // If this is a simple type, use the ComputeRegisterProp mechanism.
1690 if (VT.isSimple()) {
1691 MVT SVT = VT.getSimpleVT();
1692 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1693 MVT NVT = TransformToType[SVT.SimpleTy];
1694 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1697 (LA == TypeLegal || LA == TypeSoftenFloat ||
1698 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)
1699 && "Promote may not follow Expand or Promote");
1701 if (LA == TypeSplitVector)
1702 return LegalizeKind(LA, EVT::getVectorVT(Context,
1703 SVT.getVectorElementType(),
1704 SVT.getVectorNumElements()/2));
1705 if (LA == TypeScalarizeVector)
1706 return LegalizeKind(LA, SVT.getVectorElementType());
1707 return LegalizeKind(LA, NVT);
1710 // Handle Extended Scalar Types.
1711 if (!VT.isVector()) {
1712 assert(VT.isInteger() && "Float types must be simple");
1713 unsigned BitSize = VT.getSizeInBits();
1714 // First promote to a power-of-two size, then expand if necessary.
1715 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1716 EVT NVT = VT.getRoundIntegerType(Context);
1717 assert(NVT != VT && "Unable to round integer VT");
1718 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1719 // Avoid multi-step promotion.
1720 if (NextStep.first == TypePromoteInteger) return NextStep;
1721 // Return rounded integer type.
1722 return LegalizeKind(TypePromoteInteger, NVT);
1725 return LegalizeKind(TypeExpandInteger,
1726 EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
1729 // Handle vector types.
1730 unsigned NumElts = VT.getVectorNumElements();
1731 EVT EltVT = VT.getVectorElementType();
1733 // Vectors with only one element are always scalarized.
1735 return LegalizeKind(TypeScalarizeVector, EltVT);
1737 // Try to widen vector elements until the element type is a power of two and
1738 // promote it to a legal type later on, for example:
1739 // <3 x i8> -> <4 x i8> -> <4 x i32>
1740 if (EltVT.isInteger()) {
1741 // Vectors with a number of elements that is not a power of two are always
1742 // widened, for example <3 x i8> -> <4 x i8>.
1743 if (!VT.isPow2VectorType()) {
1744 NumElts = (unsigned)NextPowerOf2(NumElts);
1745 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1746 return LegalizeKind(TypeWidenVector, NVT);
1749 // Examine the element type.
1750 LegalizeKind LK = getTypeConversion(Context, EltVT);
1752 // If type is to be expanded, split the vector.
1753 // <4 x i140> -> <2 x i140>
1754 if (LK.first == TypeExpandInteger)
1755 return LegalizeKind(TypeSplitVector,
1756 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1758 // Promote the integer element types until a legal vector type is found
1759 // or until the element integer type is too big. If a legal type was not
1760 // found, fallback to the usual mechanism of widening/splitting the
1762 EVT OldEltVT = EltVT;
1764 // Increase the bitwidth of the element to the next pow-of-two
1765 // (which is greater than 8 bits).
1766 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
1767 ).getRoundIntegerType(Context);
1769 // Stop trying when getting a non-simple element type.
1770 // Note that vector elements may be greater than legal vector element
1771 // types. Example: X86 XMM registers hold 64bit element on 32bit
1773 if (!EltVT.isSimple()) break;
1775 // Build a new vector type and check if it is legal.
1776 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1777 // Found a legal promoted vector type.
1778 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1779 return LegalizeKind(TypePromoteInteger,
1780 EVT::getVectorVT(Context, EltVT, NumElts));
1783 // Reset the type to the unexpanded type if we did not find a legal vector
1784 // type with a promoted vector element type.
1788 // Try to widen the vector until a legal type is found.
1789 // If there is no wider legal type, split the vector.
1791 // Round up to the next power of 2.
1792 NumElts = (unsigned)NextPowerOf2(NumElts);
1794 // If there is no simple vector type with this many elements then there
1795 // cannot be a larger legal vector type. Note that this assumes that
1796 // there are no skipped intermediate vector types in the simple types.
1797 if (!EltVT.isSimple()) break;
1798 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1799 if (LargerVector == MVT()) break;
1801 // If this type is legal then widen the vector.
1802 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1803 return LegalizeKind(TypeWidenVector, LargerVector);
1806 // Widen odd vectors to next power of two.
1807 if (!VT.isPow2VectorType()) {
1808 EVT NVT = VT.getPow2VectorType(Context);
1809 return LegalizeKind(TypeWidenVector, NVT);
1812 // Vectors with illegal element types are expanded.
1813 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1814 return LegalizeKind(TypeSplitVector, NVT);
1818 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1820 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1821 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1824 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1826 /// For operations that must be promoted to a specific type, this holds the
1827 /// destination type. This map should be sparse, so don't hold it as an
1830 /// Targets add entries to this map with AddPromotedToType(..), clients access
1831 /// this with getTypeToPromoteTo(..).
1832 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1835 /// Stores the name each libcall.
1836 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1838 /// The ISD::CondCode that should be used to test the result of each of the
1839 /// comparison libcall against zero.
1840 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1842 /// Stores the CallingConv that should be used for each libcall.
1843 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1846 /// \brief Specify maximum number of store instructions per memset call.
1848 /// When lowering \@llvm.memset this field specifies the maximum number of
1849 /// store operations that may be substituted for the call to memset. Targets
1850 /// must set this value based on the cost threshold for that target. Targets
1851 /// should assume that the memset will be done using as many of the largest
1852 /// store operations first, followed by smaller ones, if necessary, per
1853 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1854 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1855 /// store. This only applies to setting a constant array of a constant size.
1856 unsigned MaxStoresPerMemset;
1858 /// Maximum number of stores operations that may be substituted for the call
1859 /// to memset, used for functions with OptSize attribute.
1860 unsigned MaxStoresPerMemsetOptSize;
1862 /// \brief Specify maximum bytes of store instructions per memcpy call.
1864 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1865 /// store operations that may be substituted for a call to memcpy. Targets
1866 /// must set this value based on the cost threshold for that target. Targets
1867 /// should assume that the memcpy will be done using as many of the largest
1868 /// store operations first, followed by smaller ones, if necessary, per
1869 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1870 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1871 /// and one 1-byte store. This only applies to copying a constant array of
1873 unsigned MaxStoresPerMemcpy;
1875 /// Maximum number of store operations that may be substituted for a call to
1876 /// memcpy, used for functions with OptSize attribute.
1877 unsigned MaxStoresPerMemcpyOptSize;
1879 /// \brief Specify maximum bytes of store instructions per memmove call.
1881 /// When lowering \@llvm.memmove this field specifies the maximum number of
1882 /// store instructions that may be substituted for a call to memmove. Targets
1883 /// must set this value based on the cost threshold for that target. Targets
1884 /// should assume that the memmove will be done using as many of the largest
1885 /// store operations first, followed by smaller ones, if necessary, per
1886 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1887 /// with 8-bit alignment would result in nine 1-byte stores. This only
1888 /// applies to copying a constant array of constant size.
1889 unsigned MaxStoresPerMemmove;
1891 /// Maximum number of store instructions that may be substituted for a call to
1892 /// memmove, used for functions with OpSize attribute.
1893 unsigned MaxStoresPerMemmoveOptSize;
1895 /// Tells the code generator that select is more expensive than a branch if
1896 /// the branch is usually predicted right.
1897 bool PredictableSelectIsExpensive;
1899 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
1900 /// a mask of a single bit, a compare, and a branch into a single instruction.
1901 bool MaskAndBranchFoldingIsLegal;
1904 /// Return true if the value types that can be represented by the specified
1905 /// register class are all legal.
1906 bool isLegalRC(const TargetRegisterClass *RC) const;
1908 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1909 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1910 MachineBasicBlock *emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const;
1913 /// This class defines information used to lower LLVM code to legal SelectionDAG
1914 /// operators that the target instruction selector can accept natively.
1916 /// This class also defines callbacks that targets must implement to lower
1917 /// target-specific constructs to SelectionDAG operators.
1918 class TargetLowering : public TargetLoweringBase {
1919 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
1920 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
1923 /// NOTE: The constructor takes ownership of TLOF.
1924 explicit TargetLowering(const TargetMachine &TM,
1925 const TargetLoweringObjectFile *TLOF);
1927 /// Returns true by value, base pointer and offset pointer and addressing mode
1928 /// by reference if the node's address can be legally represented as
1929 /// pre-indexed load / store address.
1930 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
1931 SDValue &/*Offset*/,
1932 ISD::MemIndexedMode &/*AM*/,
1933 SelectionDAG &/*DAG*/) const {
1937 /// Returns true by value, base pointer and offset pointer and addressing mode
1938 /// by reference if this node can be combined with a load / store to form a
1939 /// post-indexed load / store.
1940 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
1942 SDValue &/*Offset*/,
1943 ISD::MemIndexedMode &/*AM*/,
1944 SelectionDAG &/*DAG*/) const {
1948 /// Return the entry encoding for a jump table in the current function. The
1949 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
1950 virtual unsigned getJumpTableEncoding() const;
1952 virtual const MCExpr *
1953 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
1954 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
1955 MCContext &/*Ctx*/) const {
1956 llvm_unreachable("Need to implement this hook if target has custom JTIs");
1959 /// Returns relocation base for the given PIC jumptable.
1960 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
1961 SelectionDAG &DAG) const;
1963 /// This returns the relocation base for the given PIC jumptable, the same as
1964 /// getPICJumpTableRelocBase, but as an MCExpr.
1965 virtual const MCExpr *
1966 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1967 unsigned JTI, MCContext &Ctx) const;
1969 /// Return true if folding a constant offset with the given GlobalAddress is
1970 /// legal. It is frequently not legal in PIC relocation models.
1971 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
1973 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
1974 SDValue &Chain) const;
1976 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
1977 SDValue &NewLHS, SDValue &NewRHS,
1978 ISD::CondCode &CCCode, SDLoc DL) const;
1980 /// Returns a pair of (return value, chain).
1981 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
1982 EVT RetVT, const SDValue *Ops,
1983 unsigned NumOps, bool isSigned,
1984 SDLoc dl, bool doesNotReturn = false,
1985 bool isReturnValueUsed = true) const;
1987 //===--------------------------------------------------------------------===//
1988 // TargetLowering Optimization Methods
1991 /// A convenience struct that encapsulates a DAG, and two SDValues for
1992 /// returning information from TargetLowering to its clients that want to
1994 struct TargetLoweringOpt {
2001 explicit TargetLoweringOpt(SelectionDAG &InDAG,
2003 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2005 bool LegalTypes() const { return LegalTys; }
2006 bool LegalOperations() const { return LegalOps; }
2008 bool CombineTo(SDValue O, SDValue N) {
2014 /// Check to see if the specified operand of the specified instruction is a
2015 /// constant integer. If so, check to see if there are any bits set in the
2016 /// constant that are not demanded. If so, shrink the constant and return
2018 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
2020 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2021 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2022 /// generalized for targets with other types of implicit widening casts.
2023 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2027 /// Look at Op. At this point, we know that only the DemandedMask bits of the
2028 /// result of Op are ever used downstream. If we can use this information to
2029 /// simplify Op, create a new simplified DAG node and return true, returning
2030 /// the original and new nodes in Old and New. Otherwise, analyze the
2031 /// expression and return a mask of KnownOne and KnownZero bits for the
2032 /// expression (used to simplify the caller). The KnownZero/One bits may only
2033 /// be accurate for those bits in the DemandedMask.
2034 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2035 APInt &KnownZero, APInt &KnownOne,
2036 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2038 /// Determine which of the bits specified in Mask are known to be either zero
2039 /// or one and return them in the KnownZero/KnownOne bitsets.
2040 virtual void computeKnownBitsForTargetNode(const SDValue Op,
2043 const SelectionDAG &DAG,
2044 unsigned Depth = 0) const;
2046 /// This method can be implemented by targets that want to expose additional
2047 /// information about sign bits to the DAG Combiner.
2048 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2049 const SelectionDAG &DAG,
2050 unsigned Depth = 0) const;
2052 struct DAGCombinerInfo {
2053 void *DC; // The DAG Combiner object.
2055 bool CalledByLegalizer;
2059 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2060 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2062 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2063 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2064 bool isAfterLegalizeVectorOps() const {
2065 return Level == AfterLegalizeDAG;
2067 CombineLevel getDAGCombineLevel() { return Level; }
2068 bool isCalledByLegalizer() const { return CalledByLegalizer; }
2070 void AddToWorklist(SDNode *N);
2071 void RemoveFromWorklist(SDNode *N);
2072 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
2074 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2075 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2077 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2080 /// Return if the N is a constant or constant vector equal to the true value
2081 /// from getBooleanContents().
2082 bool isConstTrueVal(const SDNode *N) const;
2084 /// Return if the N is a constant or constant vector equal to the false value
2085 /// from getBooleanContents().
2086 bool isConstFalseVal(const SDNode *N) const;
2088 /// Try to simplify a setcc built with the specified operands and cc. If it is
2089 /// unable to simplify it, return a null SDValue.
2090 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2091 ISD::CondCode Cond, bool foldBooleans,
2092 DAGCombinerInfo &DCI, SDLoc dl) const;
2094 /// Returns true (and the GlobalValue and the offset) if the node is a
2095 /// GlobalAddress + offset.
2097 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2099 /// This method will be invoked for all target nodes and for any
2100 /// target-independent nodes that the target has registered with invoke it
2103 /// The semantics are as follows:
2105 /// SDValue.Val == 0 - No change was made
2106 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2107 /// otherwise - N should be replaced by the returned Operand.
2109 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2110 /// more complex transformations.
2112 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2114 /// Return true if it is profitable to move a following shift through this
2115 // node, adjusting any immediate operands as necessary to preserve semantics.
2116 // This transformation may not be desirable if it disrupts a particularly
2117 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2118 // By default, it returns true.
2119 virtual bool isDesirableToCommuteWithShift(const SDNode *N /*Op*/) const {
2123 /// Return true if the target has native support for the specified value type
2124 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2125 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2126 /// and some i16 instructions are slow.
2127 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2128 // By default, assume all legal types are desirable.
2129 return isTypeLegal(VT);
2132 /// Return true if it is profitable for dag combiner to transform a floating
2133 /// point op of specified opcode to a equivalent op of an integer
2134 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2135 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2140 /// This method query the target whether it is beneficial for dag combiner to
2141 /// promote the specified node. If true, it should return the desired
2142 /// promotion type by reference.
2143 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2147 //===--------------------------------------------------------------------===//
2148 // Lowering methods - These methods must be implemented by targets so that
2149 // the SelectionDAGBuilder code knows how to lower these.
2152 /// This hook must be implemented to lower the incoming (formal) arguments,
2153 /// described by the Ins array, into the specified DAG. The implementation
2154 /// should fill in the InVals array with legal-type argument values, and
2155 /// return the resulting token chain value.
2158 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2160 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
2161 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
2162 SmallVectorImpl<SDValue> &/*InVals*/) const {
2163 llvm_unreachable("Not Implemented");
2166 struct ArgListEntry {
2175 bool isInAlloca : 1;
2176 bool isReturned : 1;
2179 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2180 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2181 isReturned(false), Alignment(0) { }
2183 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2185 typedef std::vector<ArgListEntry> ArgListTy;
2187 /// This structure contains all information that is necessary for lowering
2188 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2189 /// needs to lower a call, and targets will see this struct in their LowerCall
2191 struct CallLoweringInfo {
2198 bool DoesNotReturn : 1;
2199 bool IsReturnValueUsed : 1;
2201 // IsTailCall should be modified by implementations of
2202 // TargetLowering::LowerCall that perform tail call conversions.
2205 unsigned NumFixedArgs;
2206 CallingConv::ID CallConv;
2211 ImmutableCallSite *CS;
2212 SmallVector<ISD::OutputArg, 32> Outs;
2213 SmallVector<SDValue, 32> OutVals;
2214 SmallVector<ISD::InputArg, 32> Ins;
2216 CallLoweringInfo(SelectionDAG &DAG)
2217 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
2218 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
2219 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
2220 DAG(DAG), CS(nullptr) {}
2222 CallLoweringInfo &setDebugLoc(SDLoc dl) {
2227 CallLoweringInfo &setChain(SDValue InChain) {
2232 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
2233 SDValue Target, ArgListTy &&ArgsList,
2234 unsigned FixedArgs = -1) {
2239 (FixedArgs == static_cast<unsigned>(-1) ? Args.size() : FixedArgs);
2240 Args = std::move(ArgsList);
2244 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
2245 SDValue Target, ArgListTy &&ArgsList,
2246 ImmutableCallSite &Call) {
2249 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
2250 DoesNotReturn = Call.doesNotReturn();
2251 IsVarArg = FTy->isVarArg();
2252 IsReturnValueUsed = !Call.getInstruction()->use_empty();
2253 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
2254 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
2258 CallConv = Call.getCallingConv();
2259 NumFixedArgs = FTy->getNumParams();
2260 Args = std::move(ArgsList);
2267 CallLoweringInfo &setInRegister(bool Value = true) {
2272 CallLoweringInfo &setNoReturn(bool Value = true) {
2273 DoesNotReturn = Value;
2277 CallLoweringInfo &setVarArg(bool Value = true) {
2282 CallLoweringInfo &setTailCall(bool Value = true) {
2287 CallLoweringInfo &setDiscardResult(bool Value = true) {
2288 IsReturnValueUsed = !Value;
2292 CallLoweringInfo &setSExtResult(bool Value = true) {
2297 CallLoweringInfo &setZExtResult(bool Value = true) {
2302 ArgListTy &getArgs() {
2307 /// This function lowers an abstract call to a function into an actual call.
2308 /// This returns a pair of operands. The first element is the return value
2309 /// for the function (if RetTy is not VoidTy). The second element is the
2310 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2311 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2313 /// This hook must be implemented to lower calls into the the specified
2314 /// DAG. The outgoing arguments to the call are described by the Outs array,
2315 /// and the values to be returned by the call are described by the Ins
2316 /// array. The implementation should fill in the InVals array with legal-type
2317 /// return values from the call, and return the resulting token chain value.
2319 LowerCall(CallLoweringInfo &/*CLI*/,
2320 SmallVectorImpl<SDValue> &/*InVals*/) const {
2321 llvm_unreachable("Not Implemented");
2324 /// Target-specific cleanup for formal ByVal parameters.
2325 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2327 /// This hook should be implemented to check whether the return values
2328 /// described by the Outs array can fit into the return registers. If false
2329 /// is returned, an sret-demotion is performed.
2330 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2331 MachineFunction &/*MF*/, bool /*isVarArg*/,
2332 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2333 LLVMContext &/*Context*/) const
2335 // Return true by default to get preexisting behavior.
2339 /// This hook must be implemented to lower outgoing return values, described
2340 /// by the Outs array, into the specified DAG. The implementation should
2341 /// return the resulting token chain value.
2343 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2345 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2346 const SmallVectorImpl<SDValue> &/*OutVals*/,
2347 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2348 llvm_unreachable("Not Implemented");
2351 /// Return true if result of the specified node is used by a return node
2352 /// only. It also compute and return the input chain for the tail call.
2354 /// This is used to determine whether it is possible to codegen a libcall as
2355 /// tail call at legalization time.
2356 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2360 /// Return true if the target may be able emit the call instruction as a tail
2361 /// call. This is used by optimization passes to determine if it's profitable
2362 /// to duplicate return instructions to enable tailcall optimization.
2363 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2367 /// Return the builtin name for the __builtin___clear_cache intrinsic
2368 /// Default is to invoke the clear cache library call
2369 virtual const char * getClearCacheBuiltinName() const {
2370 return "__clear_cache";
2373 /// Return the register ID of the name passed in. Used by named register
2374 /// global variables extension. There is no target-independent behaviour
2375 /// so the default action is to bail.
2376 virtual unsigned getRegisterByName(const char* RegName, EVT VT) const {
2377 report_fatal_error("Named registers not implemented for this target");
2380 /// Return the type that should be used to zero or sign extend a
2381 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2382 /// convention requires the return type to be promoted, but this is not true
2383 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2384 /// calling conventions. The frontend should handle this and include all of
2385 /// the necessary information.
2386 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2387 ISD::NodeType /*ExtendKind*/) const {
2388 EVT MinVT = getRegisterType(Context, MVT::i32);
2389 return VT.bitsLT(MinVT) ? MinVT : VT;
2392 /// For some targets, an LLVM struct type must be broken down into multiple
2393 /// simple types, but the calling convention specifies that the entire struct
2394 /// must be passed in a block of consecutive registers.
2396 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
2397 bool isVarArg) const {
2401 /// Returns a 0 terminated array of registers that can be safely used as
2402 /// scratch registers.
2403 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
2407 /// This callback is used to prepare for a volatile or atomic load.
2408 /// It takes a chain node as input and returns the chain for the load itself.
2410 /// Having a callback like this is necessary for targets like SystemZ,
2411 /// which allows a CPU to reuse the result of a previous load indefinitely,
2412 /// even if a cache-coherent store is performed by another CPU. The default
2413 /// implementation does nothing.
2414 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2415 SelectionDAG &DAG) const {
2419 /// This callback is invoked by the type legalizer to legalize nodes with an
2420 /// illegal operand type but legal result types. It replaces the
2421 /// LowerOperation callback in the type Legalizer. The reason we can not do
2422 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2423 /// use this callback.
2425 /// TODO: Consider merging with ReplaceNodeResults.
2427 /// The target places new result values for the node in Results (their number
2428 /// and types must exactly match those of the original return values of
2429 /// the node), or leaves Results empty, which indicates that the node is not
2430 /// to be custom lowered after all.
2431 /// The default implementation calls LowerOperation.
2432 virtual void LowerOperationWrapper(SDNode *N,
2433 SmallVectorImpl<SDValue> &Results,
2434 SelectionDAG &DAG) const;
2436 /// This callback is invoked for operations that are unsupported by the
2437 /// target, which are registered to use 'custom' lowering, and whose defined
2438 /// values are all legal. If the target has no operations that require custom
2439 /// lowering, it need not implement this. The default implementation of this
2441 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2443 /// This callback is invoked when a node result type is illegal for the
2444 /// target, and the operation was registered to use 'custom' lowering for that
2445 /// result type. The target places new result values for the node in Results
2446 /// (their number and types must exactly match those of the original return
2447 /// values of the node), or leaves Results empty, which indicates that the
2448 /// node is not to be custom lowered after all.
2450 /// If the target has no operations that require custom lowering, it need not
2451 /// implement this. The default implementation aborts.
2452 virtual void ReplaceNodeResults(SDNode * /*N*/,
2453 SmallVectorImpl<SDValue> &/*Results*/,
2454 SelectionDAG &/*DAG*/) const {
2455 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2458 /// This method returns the name of a target specific DAG node.
2459 virtual const char *getTargetNodeName(unsigned Opcode) const;
2461 /// This method returns a target specific FastISel object, or null if the
2462 /// target does not support "fast" ISel.
2463 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2464 const TargetLibraryInfo *) const {
2469 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2470 SelectionDAG &DAG) const;
2472 //===--------------------------------------------------------------------===//
2473 // Inline Asm Support hooks
2476 /// This hook allows the target to expand an inline asm call to be explicit
2477 /// llvm code if it wants to. This is useful for turning simple inline asms
2478 /// into LLVM intrinsics, which gives the compiler more information about the
2479 /// behavior of the code.
2480 virtual bool ExpandInlineAsm(CallInst *) const {
2484 enum ConstraintType {
2485 C_Register, // Constraint represents specific register(s).
2486 C_RegisterClass, // Constraint represents any of register(s) in class.
2487 C_Memory, // Memory constraint.
2488 C_Other, // Something else.
2489 C_Unknown // Unsupported constraint.
2492 enum ConstraintWeight {
2494 CW_Invalid = -1, // No match.
2495 CW_Okay = 0, // Acceptable.
2496 CW_Good = 1, // Good weight.
2497 CW_Better = 2, // Better weight.
2498 CW_Best = 3, // Best weight.
2500 // Well-known weights.
2501 CW_SpecificReg = CW_Okay, // Specific register operands.
2502 CW_Register = CW_Good, // Register operands.
2503 CW_Memory = CW_Better, // Memory operands.
2504 CW_Constant = CW_Best, // Constant operand.
2505 CW_Default = CW_Okay // Default or don't know type.
2508 /// This contains information for each constraint that we are lowering.
2509 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2510 /// This contains the actual string for the code, like "m". TargetLowering
2511 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2512 /// matches the operand.
2513 std::string ConstraintCode;
2515 /// Information about the constraint code, e.g. Register, RegisterClass,
2516 /// Memory, Other, Unknown.
2517 TargetLowering::ConstraintType ConstraintType;
2519 /// If this is the result output operand or a clobber, this is null,
2520 /// otherwise it is the incoming operand to the CallInst. This gets
2521 /// modified as the asm is processed.
2522 Value *CallOperandVal;
2524 /// The ValueType for the operand value.
2527 /// Return true of this is an input operand that is a matching constraint
2529 bool isMatchingInputConstraint() const;
2531 /// If this is an input matching constraint, this method returns the output
2532 /// operand it matches.
2533 unsigned getMatchedOperand() const;
2535 /// Copy constructor for copying from a ConstraintInfo.
2536 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
2537 : InlineAsm::ConstraintInfo(info),
2538 ConstraintType(TargetLowering::C_Unknown),
2539 CallOperandVal(nullptr), ConstraintVT(MVT::Other) {
2543 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2545 /// Split up the constraint string from the inline assembly value into the
2546 /// specific constraints and their prefixes, and also tie in the associated
2547 /// operand values. If this returns an empty vector, and if the constraint
2548 /// string itself isn't empty, there was an error parsing.
2549 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
2551 /// Examine constraint type and operand type and determine a weight value.
2552 /// The operand object must already have been set up with the operand type.
2553 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2554 AsmOperandInfo &info, int maIndex) const;
2556 /// Examine constraint string and operand type and determine a weight value.
2557 /// The operand object must already have been set up with the operand type.
2558 virtual ConstraintWeight getSingleConstraintMatchWeight(
2559 AsmOperandInfo &info, const char *constraint) const;
2561 /// Determines the constraint code and constraint type to use for the specific
2562 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2563 /// If the actual operand being passed in is available, it can be passed in as
2564 /// Op, otherwise an empty SDValue can be passed.
2565 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2567 SelectionDAG *DAG = nullptr) const;
2569 /// Given a constraint, return the type of constraint it is for this target.
2570 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
2572 /// Given a physical register constraint (e.g. {edx}), return the register
2573 /// number and the register class for the register.
2575 /// Given a register class constraint, like 'r', if this corresponds directly
2576 /// to an LLVM register class, return a register of 0 and the register class
2579 /// This should only be used for C_Register constraints. On error, this
2580 /// returns a register number of 0 and a null register class pointer..
2581 virtual std::pair<unsigned, const TargetRegisterClass*>
2582 getRegForInlineAsmConstraint(const std::string &Constraint,
2585 /// Try to replace an X constraint, which matches anything, with another that
2586 /// has more specific requirements based on the type of the corresponding
2587 /// operand. This returns null if there is no replacement to make.
2588 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2590 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2591 /// add anything to Ops.
2592 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2593 std::vector<SDValue> &Ops,
2594 SelectionDAG &DAG) const;
2596 //===--------------------------------------------------------------------===//
2597 // Div utility functions
2599 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2600 SelectionDAG &DAG) const;
2601 SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2602 bool IsAfterLegalization,
2603 std::vector<SDNode *> *Created) const;
2604 SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2605 bool IsAfterLegalization,
2606 std::vector<SDNode *> *Created) const;
2607 virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
2609 std::vector<SDNode *> *Created) const {
2613 virtual SDValue BuildRSQRTE(SDValue Op, DAGCombinerInfo &DCI) const {
2617 //===--------------------------------------------------------------------===//
2618 // Legalization utility functions
2621 /// Expand a MUL into two nodes. One that computes the high bits of
2622 /// the result and one that computes the low bits.
2623 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
2624 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
2625 /// if you want to control how low bits are extracted from the LHS.
2626 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
2627 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
2628 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
2629 /// \returns true if the node has been expanded. false if it has not
2630 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2631 SelectionDAG &DAG, SDValue LL = SDValue(),
2632 SDValue LH = SDValue(), SDValue RL = SDValue(),
2633 SDValue RH = SDValue()) const;
2635 /// Expand float(f32) to SINT(i64) conversion
2636 /// \param N Node to expand
2637 /// \param Result output after conversion
2638 /// \returns True, if the expansion was successful, false otherwise
2639 bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
2641 //===--------------------------------------------------------------------===//
2642 // Instruction Emitting Hooks
2645 /// This method should be implemented by targets that mark instructions with
2646 /// the 'usesCustomInserter' flag. These instructions are special in various
2647 /// ways, which require special support to insert. The specified MachineInstr
2648 /// is created but not inserted into any basic blocks, and this method is
2649 /// called to expand it into a sequence of instructions, potentially also
2650 /// creating new basic blocks and control flow.
2651 virtual MachineBasicBlock *
2652 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2654 /// This method should be implemented by targets that mark instructions with
2655 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2656 /// instruction selection by target hooks. e.g. To fill in optional defs for
2657 /// ARM 's' setting instructions.
2659 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2661 /// If this function returns true, SelectionDAGBuilder emits a
2662 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
2663 virtual bool useLoadStackGuardNode() const {
2668 /// Given an LLVM IR type and return type attributes, compute the return value
2669 /// EVTs and flags, and optionally also the offsets, if the return value is
2670 /// being lowered to memory.
2671 void GetReturnInfo(Type* ReturnType, AttributeSet attr,
2672 SmallVectorImpl<ISD::OutputArg> &Outs,
2673 const TargetLowering &TLI);
2675 } // end llvm namespace