1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CallingConv.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Attributes.h"
28 #include "llvm/ADT/SmallPtrSet.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/CodeGen/RuntimeLibcalls.h"
31 #include "llvm/Support/DebugLoc.h"
32 #include "llvm/Target/TargetCallingConv.h"
33 #include "llvm/Target/TargetMachine.h"
44 class FunctionLoweringInfo;
45 class ImmutableCallSite;
46 class MachineBasicBlock;
47 class MachineFunction;
48 class MachineFrameInfo;
50 class MachineJumpTableInfo;
56 template<typename T> class SmallVectorImpl;
59 class TargetRegisterClass;
60 class TargetLoweringObjectFile;
63 // FIXME: should this be here?
72 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
75 //===----------------------------------------------------------------------===//
76 /// TargetLowering - This class defines information used to lower LLVM code to
77 /// legal SelectionDAG operators that the target instruction selector can accept
80 /// This class also defines callbacks that targets must implement to lower
81 /// target-specific constructs to SelectionDAG operators.
83 class TargetLowering {
84 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT
85 void operator=(const TargetLowering&); // DO NOT IMPLEMENT
87 /// LegalizeAction - This enum indicates whether operations are valid for a
88 /// target, and if not, what action should be used to make them valid.
90 Legal, // The target natively supports this operation.
91 Promote, // This operation should be executed in a larger type.
92 Expand, // Try to expand this to other ops, otherwise use a libcall.
93 Custom // Use the LowerOperation hook to implement custom lowering.
96 enum BooleanContent { // How the target represents true/false values.
97 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
98 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
99 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
102 /// NOTE: The constructor takes ownership of TLOF.
103 explicit TargetLowering(const TargetMachine &TM,
104 const TargetLoweringObjectFile *TLOF);
105 virtual ~TargetLowering();
107 const TargetMachine &getTargetMachine() const { return TM; }
108 const TargetData *getTargetData() const { return TD; }
109 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
111 bool isBigEndian() const { return !IsLittleEndian; }
112 bool isLittleEndian() const { return IsLittleEndian; }
113 MVT getPointerTy() const { return PointerTy; }
114 MVT getShiftAmountTy() const { return ShiftAmountTy; }
116 /// isSelectExpensive - Return true if the select operation is expensive for
118 bool isSelectExpensive() const { return SelectIsExpensive; }
120 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
121 /// a sequence of several shifts, adds, and multiplies for this target.
122 bool isIntDivCheap() const { return IntDivIsCheap; }
124 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
126 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
128 /// isJumpExpensive() - Return true if Flow Control is an expensive operation
129 /// that should be avoided.
130 bool isJumpExpensive() const { return JumpIsExpensive; }
132 /// getSetCCResultType - Return the ValueType of the result of SETCC
133 /// operations. Also used to obtain the target's preferred type for
134 /// the condition operand of SELECT and BRCOND nodes. In the case of
135 /// BRCOND the argument passed is MVT::Other since there are no other
136 /// operands to get a type hint from.
138 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
140 /// getCmpLibcallReturnType - Return the ValueType for comparison
141 /// libcalls. Comparions libcalls include floating point comparion calls,
142 /// and Ordered/Unordered check calls on floating point numbers.
144 MVT::SimpleValueType getCmpLibcallReturnType() const;
146 /// getBooleanContents - For targets without i1 registers, this gives the
147 /// nature of the high-bits of boolean values held in types wider than i1.
148 /// "Boolean values" are special true/false values produced by nodes like
149 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
150 /// Not to be confused with general values promoted from i1.
151 BooleanContent getBooleanContents() const { return BooleanContents;}
153 /// getSchedulingPreference - Return target scheduling preference.
154 Sched::Preference getSchedulingPreference() const {
155 return SchedPreferenceInfo;
158 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to
159 /// different scheduling heuristics for different nodes. This function returns
160 /// the preference (or none) for the given node.
161 virtual Sched::Preference getSchedulingPreference(SDNode *N) const {
165 /// getRegClassFor - Return the register class that should be used for the
166 /// specified value type.
167 virtual TargetRegisterClass *getRegClassFor(EVT VT) const {
168 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
169 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
170 assert(RC && "This value type is not natively supported!");
174 /// getRepRegClassFor - Return the 'representative' register class for the
175 /// specified value type. The 'representative' register class is the largest
176 /// legal super-reg register class for the register class of the value type.
177 /// For example, on i386 the rep register class for i8, i16, and i32 are GR32;
178 /// while the rep register class is GR64 on x86_64.
179 virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const {
180 assert(VT.isSimple() && "getRepRegClassFor called on illegal type!");
181 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy];
185 /// getRepRegClassCostFor - Return the cost of the 'representative' register
186 /// class for the specified value type.
187 virtual uint8_t getRepRegClassCostFor(EVT VT) const {
188 assert(VT.isSimple() && "getRepRegClassCostFor called on illegal type!");
189 return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy];
192 /// getRegPressureLimit - Return the register pressure "high water mark" for
193 /// the specific register class. The scheduler is in high register pressure
194 /// mode (for the specific register class) if it goes over the limit.
195 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
196 MachineFunction &MF) const {
200 /// isTypeLegal - Return true if the target has native support for the
201 /// specified value type. This means that it has a register that directly
202 /// holds it without promotions or expansions.
203 bool isTypeLegal(EVT VT) const {
204 assert(!VT.isSimple() ||
205 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
206 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
209 class ValueTypeActionImpl {
210 /// ValueTypeActions - For each value type, keep a LegalizeAction enum
211 /// that indicates how instruction selection should deal with the type.
212 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
214 LegalizeAction getExtendedTypeAction(EVT VT) const {
215 // Handle non-vector integers.
216 if (!VT.isVector()) {
217 assert(VT.isInteger() && "Unsupported extended type!");
218 unsigned BitSize = VT.getSizeInBits();
219 // First promote to a power-of-two size, then expand if necessary.
220 if (BitSize < 8 || !isPowerOf2_32(BitSize))
225 // If this is a type smaller than a legal vector type, promote to that
226 // type, e.g. <2 x float> -> <4 x float>.
227 if (VT.getVectorElementType().isSimple() &&
228 VT.getVectorNumElements() != 1) {
229 MVT EltType = VT.getVectorElementType().getSimpleVT();
230 unsigned NumElts = VT.getVectorNumElements();
232 // Round up to the nearest power of 2.
233 NumElts = (unsigned)NextPowerOf2(NumElts);
235 MVT LargerVector = MVT::getVectorVT(EltType, NumElts);
236 if (LargerVector == MVT()) break;
238 // If this the larger type is legal, promote to it.
239 if (getTypeAction(LargerVector) == Legal) return Promote;
243 return VT.isPow2VectorType() ? Expand : Promote;
246 ValueTypeActionImpl() {
247 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0);
250 LegalizeAction getTypeAction(EVT VT) const {
251 if (!VT.isExtended())
252 return getTypeAction(VT.getSimpleVT());
253 return getExtendedTypeAction(VT);
256 LegalizeAction getTypeAction(MVT VT) const {
257 return (LegalizeAction)ValueTypeActions[VT.SimpleTy];
260 void setTypeAction(EVT VT, LegalizeAction Action) {
261 unsigned I = VT.getSimpleVT().SimpleTy;
262 ValueTypeActions[I] = Action;
266 const ValueTypeActionImpl &getValueTypeActions() const {
267 return ValueTypeActions;
270 /// getTypeAction - Return how we should legalize values of this type, either
271 /// it is already legal (return 'Legal') or we need to promote it to a larger
272 /// type (return 'Promote'), or we need to expand it into multiple registers
273 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
274 LegalizeAction getTypeAction(EVT VT) const {
275 return ValueTypeActions.getTypeAction(VT);
277 LegalizeAction getTypeAction(MVT VT) const {
278 return ValueTypeActions.getTypeAction(VT);
281 /// getTypeToTransformTo - For types supported by the target, this is an
282 /// identity function. For types that must be promoted to larger types, this
283 /// returns the larger type to promote to. For integer types that are larger
284 /// than the largest integer register, this contains one step in the expansion
285 /// to get to the smaller register. For illegal floating point types, this
286 /// returns the integer type to transform to.
287 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
289 assert((unsigned)VT.getSimpleVT().SimpleTy <
290 array_lengthof(TransformToType));
291 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
292 assert(getTypeAction(NVT) != Promote &&
293 "Promote may not follow Expand or Promote");
298 EVT NVT = VT.getPow2VectorType(Context);
300 // Vector length is a power of 2 - split to half the size.
301 unsigned NumElts = VT.getVectorNumElements();
302 EVT EltVT = VT.getVectorElementType();
303 return (NumElts == 1) ?
304 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2);
306 // Promote to a power of two size, avoiding multi-step promotion.
307 return getTypeAction(NVT) == Promote ?
308 getTypeToTransformTo(Context, NVT) : NVT;
309 } else if (VT.isInteger()) {
310 EVT NVT = VT.getRoundIntegerType(Context);
311 if (NVT == VT) // Size is a power of two - expand to half the size.
312 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2);
314 // Promote to a power of two size, avoiding multi-step promotion.
315 return getTypeAction(NVT) == Promote ?
316 getTypeToTransformTo(Context, NVT) : NVT;
318 assert(0 && "Unsupported extended type!");
319 return MVT(MVT::Other); // Not reached
322 /// getTypeToExpandTo - For types supported by the target, this is an
323 /// identity function. For types that must be expanded (i.e. integer types
324 /// that are larger than the largest integer register or illegal floating
325 /// point types), this returns the largest legal type it will be expanded to.
326 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
327 assert(!VT.isVector());
329 switch (getTypeAction(VT)) {
333 VT = getTypeToTransformTo(Context, VT);
336 assert(false && "Type is not legal nor is it to be expanded!");
343 /// getVectorTypeBreakdown - Vector types are broken down into some number of
344 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
345 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
346 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
348 /// This method returns the number of registers needed, and the VT for each
349 /// register. It also returns the VT and quantity of the intermediate values
350 /// before they are promoted/expanded.
352 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
354 unsigned &NumIntermediates,
355 EVT &RegisterVT) const;
357 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
358 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
359 /// this is the case, it returns true and store the intrinsic
360 /// information into the IntrinsicInfo that was passed to the function.
361 struct IntrinsicInfo {
362 unsigned opc; // target opcode
363 EVT memVT; // memory VT
364 const Value* ptrVal; // value representing memory location
365 int offset; // offset off of ptrVal
366 unsigned align; // alignment
367 bool vol; // is volatile?
368 bool readMem; // reads memory?
369 bool writeMem; // writes memory?
372 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
373 const CallInst &I, unsigned Intrinsic) const {
377 /// isFPImmLegal - Returns true if the target can instruction select the
378 /// specified FP immediate natively. If false, the legalizer will materialize
379 /// the FP immediate as a load from a constant pool.
380 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const {
384 /// isShuffleMaskLegal - Targets can use this to indicate that they only
385 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
386 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
387 /// are assumed to be legal.
388 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
393 /// canOpTrap - Returns true if the operation can trap for the value type.
394 /// VT must be a legal type. By default, we optimistically assume most
395 /// operations don't trap except for divide and remainder.
396 virtual bool canOpTrap(unsigned Op, EVT VT) const;
398 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
399 /// used by Targets can use this to indicate if there is a suitable
400 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
402 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
407 /// getOperationAction - Return how this operation should be treated: either
408 /// it is legal, needs to be promoted to a larger size, needs to be
409 /// expanded to some other code sequence, or the target has a custom expander
411 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
412 if (VT.isExtended()) return Expand;
413 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
414 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
415 return (LegalizeAction)OpActions[I][Op];
418 /// isOperationLegalOrCustom - Return true if the specified operation is
419 /// legal on this target or can be made legal with custom lowering. This
420 /// is used to help guide high-level lowering decisions.
421 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
422 return (VT == MVT::Other || isTypeLegal(VT)) &&
423 (getOperationAction(Op, VT) == Legal ||
424 getOperationAction(Op, VT) == Custom);
427 /// isOperationLegal - Return true if the specified operation is legal on this
429 bool isOperationLegal(unsigned Op, EVT VT) const {
430 return (VT == MVT::Other || isTypeLegal(VT)) &&
431 getOperationAction(Op, VT) == Legal;
434 /// getLoadExtAction - Return how this load with extension should be treated:
435 /// either it is legal, needs to be promoted to a larger size, needs to be
436 /// expanded to some other code sequence, or the target has a custom expander
438 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const {
439 assert(ExtType < ISD::LAST_LOADEXT_TYPE &&
440 VT.getSimpleVT() < MVT::LAST_VALUETYPE &&
441 "Table isn't big enough!");
442 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType];
445 /// isLoadExtLegal - Return true if the specified load with extension is legal
447 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
448 return VT.isSimple() &&
449 (getLoadExtAction(ExtType, VT) == Legal ||
450 getLoadExtAction(ExtType, VT) == Custom);
453 /// getTruncStoreAction - Return how this store with truncation should be
454 /// treated: either it is legal, needs to be promoted to a larger size, needs
455 /// to be expanded to some other code sequence, or the target has a custom
457 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
458 assert(ValVT.getSimpleVT() < MVT::LAST_VALUETYPE &&
459 MemVT.getSimpleVT() < MVT::LAST_VALUETYPE &&
460 "Table isn't big enough!");
461 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy]
462 [MemVT.getSimpleVT().SimpleTy];
465 /// isTruncStoreLegal - Return true if the specified store with truncation is
466 /// legal on this target.
467 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
468 return isTypeLegal(ValVT) && MemVT.isSimple() &&
469 (getTruncStoreAction(ValVT, MemVT) == Legal ||
470 getTruncStoreAction(ValVT, MemVT) == Custom);
473 /// getIndexedLoadAction - Return how the indexed load should be treated:
474 /// either it is legal, needs to be promoted to a larger size, needs to be
475 /// expanded to some other code sequence, or the target has a custom expander
478 getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
479 assert(IdxMode < ISD::LAST_INDEXED_MODE &&
480 VT.getSimpleVT() < MVT::LAST_VALUETYPE &&
481 "Table isn't big enough!");
482 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy;
483 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
486 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
488 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
489 return VT.isSimple() &&
490 (getIndexedLoadAction(IdxMode, VT) == Legal ||
491 getIndexedLoadAction(IdxMode, VT) == Custom);
494 /// getIndexedStoreAction - Return how the indexed store should be treated:
495 /// either it is legal, needs to be promoted to a larger size, needs to be
496 /// expanded to some other code sequence, or the target has a custom expander
499 getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
500 assert(IdxMode < ISD::LAST_INDEXED_MODE &&
501 VT.getSimpleVT() < MVT::LAST_VALUETYPE &&
502 "Table isn't big enough!");
503 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy;
504 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
507 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
509 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
510 return VT.isSimple() &&
511 (getIndexedStoreAction(IdxMode, VT) == Legal ||
512 getIndexedStoreAction(IdxMode, VT) == Custom);
515 /// getCondCodeAction - Return how the condition code should be treated:
516 /// either it is legal, needs to be expanded to some other code sequence,
517 /// or the target has a custom expander for it.
519 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
520 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
521 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
522 "Table isn't big enough!");
523 LegalizeAction Action = (LegalizeAction)
524 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);
525 assert(Action != Promote && "Can't promote condition code!");
529 /// isCondCodeLegal - Return true if the specified condition code is legal
531 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
532 return getCondCodeAction(CC, VT) == Legal ||
533 getCondCodeAction(CC, VT) == Custom;
537 /// getTypeToPromoteTo - If the action for this operation is to promote, this
538 /// method returns the ValueType to promote to.
539 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const {
540 assert(getOperationAction(Op, VT) == Promote &&
541 "This operation isn't promoted!");
543 // See if this has an explicit type specified.
544 std::map<std::pair<unsigned, MVT::SimpleValueType>,
545 MVT::SimpleValueType>::const_iterator PTTI =
546 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
547 if (PTTI != PromoteToType.end()) return PTTI->second;
549 assert((VT.isInteger() || VT.isFloatingPoint()) &&
550 "Cannot autopromote this type, add it with AddPromotedToType.");
554 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
555 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
556 "Didn't find type to promote to!");
557 } while (!isTypeLegal(NVT) ||
558 getOperationAction(Op, NVT) == Promote);
562 /// getValueType - Return the EVT corresponding to this LLVM type.
563 /// This is fixed by the LLVM operations except for the pointer size. If
564 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
565 /// counterpart (e.g. structs), otherwise it will assert.
566 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
567 EVT VT = EVT::getEVT(Ty, AllowUnknown);
568 return VT == MVT::iPTR ? PointerTy : VT;
571 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
572 /// function arguments in the caller parameter area. This is the actual
573 /// alignment, not its logarithm.
574 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
576 /// getRegisterType - Return the type of registers that this ValueType will
577 /// eventually require.
578 EVT getRegisterType(MVT VT) const {
579 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
580 return RegisterTypeForVT[VT.SimpleTy];
583 /// getRegisterType - Return the type of registers that this ValueType will
584 /// eventually require.
585 EVT getRegisterType(LLVMContext &Context, EVT VT) const {
587 assert((unsigned)VT.getSimpleVT().SimpleTy <
588 array_lengthof(RegisterTypeForVT));
589 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
593 unsigned NumIntermediates;
594 (void)getVectorTypeBreakdown(Context, VT, VT1,
595 NumIntermediates, RegisterVT);
598 if (VT.isInteger()) {
599 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
601 assert(0 && "Unsupported extended type!");
602 return EVT(MVT::Other); // Not reached
605 /// getNumRegisters - Return the number of registers that this ValueType will
606 /// eventually require. This is one for any types promoted to live in larger
607 /// registers, but may be more than one for types (like i64) that are split
608 /// into pieces. For types like i140, which are first promoted then expanded,
609 /// it is the number of registers needed to hold all the bits of the original
610 /// type. For an i140 on a 32 bit machine this means 5 registers.
611 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
613 assert((unsigned)VT.getSimpleVT().SimpleTy <
614 array_lengthof(NumRegistersForVT));
615 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
619 unsigned NumIntermediates;
620 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
622 if (VT.isInteger()) {
623 unsigned BitWidth = VT.getSizeInBits();
624 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
625 return (BitWidth + RegWidth - 1) / RegWidth;
627 assert(0 && "Unsupported extended type!");
628 return 0; // Not reached
631 /// ShouldShrinkFPConstant - If true, then instruction selection should
632 /// seek to shrink the FP constant of the specified type to a smaller type
633 /// in order to save space and / or reduce runtime.
634 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; }
636 /// hasTargetDAGCombine - If true, the target has custom DAG combine
637 /// transformations that it can perform for the specified node.
638 bool hasTargetDAGCombine(ISD::NodeType NT) const {
639 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
640 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
643 /// This function returns the maximum number of store operations permitted
644 /// to replace a call to llvm.memset. The value is set by the target at the
645 /// performance threshold for such a replacement.
646 /// @brief Get maximum # of store operations permitted for llvm.memset
647 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
649 /// This function returns the maximum number of store operations permitted
650 /// to replace a call to llvm.memcpy. The value is set by the target at the
651 /// performance threshold for such a replacement.
652 /// @brief Get maximum # of store operations permitted for llvm.memcpy
653 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
655 /// This function returns the maximum number of store operations permitted
656 /// to replace a call to llvm.memmove. The value is set by the target at the
657 /// performance threshold for such a replacement.
658 /// @brief Get maximum # of store operations permitted for llvm.memmove
659 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
661 /// This function returns true if the target allows unaligned memory accesses.
662 /// of the specified type. This is used, for example, in situations where an
663 /// array copy/move/set is converted to a sequence of store operations. It's
664 /// use helps to ensure that such replacements don't generate code that causes
665 /// an alignment error (trap) on the target machine.
666 /// @brief Determine if the target supports unaligned memory accesses.
667 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
671 /// This function returns true if the target would benefit from code placement
673 /// @brief Determine if the target should perform code placement optimization.
674 bool shouldOptimizeCodePlacement() const {
675 return benefitFromCodePlacementOpt;
678 /// getOptimalMemOpType - Returns the target specific optimal type for load
679 /// and store operations as a result of memset, memcpy, and memmove
680 /// lowering. If DstAlign is zero that means it's safe to destination
681 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
682 /// means there isn't a need to check it against alignment requirement,
683 /// probably because the source does not need to be loaded. If
684 /// 'NonScalarIntSafe' is true, that means it's safe to return a
685 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
686 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
687 /// constant so it does not need to be loaded.
688 /// It returns EVT::Other if the type should be determined using generic
689 /// target-independent logic.
690 virtual EVT getOptimalMemOpType(uint64_t Size,
691 unsigned DstAlign, unsigned SrcAlign,
692 bool NonScalarIntSafe, bool MemcpyStrSrc,
693 MachineFunction &MF) const {
697 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
698 /// to implement llvm.setjmp.
699 bool usesUnderscoreSetJmp() const {
700 return UseUnderscoreSetJmp;
703 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
704 /// to implement llvm.longjmp.
705 bool usesUnderscoreLongJmp() const {
706 return UseUnderscoreLongJmp;
709 /// getStackPointerRegisterToSaveRestore - If a physical register, this
710 /// specifies the register that llvm.savestack/llvm.restorestack should save
712 unsigned getStackPointerRegisterToSaveRestore() const {
713 return StackPointerRegisterToSaveRestore;
716 /// getExceptionAddressRegister - If a physical register, this returns
717 /// the register that receives the exception address on entry to a landing
719 unsigned getExceptionAddressRegister() const {
720 return ExceptionPointerRegister;
723 /// getExceptionSelectorRegister - If a physical register, this returns
724 /// the register that receives the exception typeid on entry to a landing
726 unsigned getExceptionSelectorRegister() const {
727 return ExceptionSelectorRegister;
730 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
731 /// set, the default is 200)
732 unsigned getJumpBufSize() const {
736 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
737 /// (if never set, the default is 0)
738 unsigned getJumpBufAlignment() const {
739 return JumpBufAlignment;
742 /// getMinStackArgumentAlignment - return the minimum stack alignment of an
744 unsigned getMinStackArgumentAlignment() const {
745 return MinStackArgumentAlignment;
748 /// getPrefLoopAlignment - return the preferred loop alignment.
750 unsigned getPrefLoopAlignment() const {
751 return PrefLoopAlignment;
754 /// getShouldFoldAtomicFences - return whether the combiner should fold
755 /// fence MEMBARRIER instructions into the atomic intrinsic instructions.
757 bool getShouldFoldAtomicFences() const {
758 return ShouldFoldAtomicFences;
761 /// getPreIndexedAddressParts - returns true by value, base pointer and
762 /// offset pointer and addressing mode by reference if the node's address
763 /// can be legally represented as pre-indexed load / store address.
764 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
766 ISD::MemIndexedMode &AM,
767 SelectionDAG &DAG) const {
771 /// getPostIndexedAddressParts - returns true by value, base pointer and
772 /// offset pointer and addressing mode by reference if this node can be
773 /// combined with a load / store to form a post-indexed load / store.
774 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
775 SDValue &Base, SDValue &Offset,
776 ISD::MemIndexedMode &AM,
777 SelectionDAG &DAG) const {
781 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
782 /// current function. The returned value is a member of the
783 /// MachineJumpTableInfo::JTEntryKind enum.
784 virtual unsigned getJumpTableEncoding() const;
786 virtual const MCExpr *
787 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
788 const MachineBasicBlock *MBB, unsigned uid,
789 MCContext &Ctx) const {
790 assert(0 && "Need to implement this hook if target has custom JTIs");
794 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
796 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
797 SelectionDAG &DAG) const;
799 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
800 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
802 virtual const MCExpr *
803 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
804 unsigned JTI, MCContext &Ctx) const;
806 /// isOffsetFoldingLegal - Return true if folding a constant offset
807 /// with the given GlobalAddress is legal. It is frequently not legal in
808 /// PIC relocation models.
809 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
811 /// getFunctionAlignment - Return the Log2 alignment of this function.
812 virtual unsigned getFunctionAlignment(const Function *) const = 0;
814 /// getStackCookieLocation - Return true if the target stores stack
815 /// protector cookies at a fixed offset in some non-standard address
816 /// space, and populates the address space and offset as
818 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const {
822 /// getMaximalGlobalOffset - Returns the maximal possible offset which can be
823 /// used for loads / stores from the global.
824 virtual unsigned getMaximalGlobalOffset() const {
828 //===--------------------------------------------------------------------===//
829 // TargetLowering Optimization Methods
832 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
833 /// SDValues for returning information from TargetLowering to its clients
834 /// that want to combine
835 struct TargetLoweringOpt {
842 explicit TargetLoweringOpt(SelectionDAG &InDAG,
844 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
846 bool LegalTypes() const { return LegalTys; }
847 bool LegalOperations() const { return LegalOps; }
849 bool CombineTo(SDValue O, SDValue N) {
855 /// ShrinkDemandedConstant - Check to see if the specified operand of the
856 /// specified instruction is a constant integer. If so, check to see if
857 /// there are any bits set in the constant that are not demanded. If so,
858 /// shrink the constant and return true.
859 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
861 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
862 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
863 /// cast, but it could be generalized for targets with other types of
864 /// implicit widening casts.
865 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
869 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
870 /// DemandedMask bits of the result of Op are ever used downstream. If we can
871 /// use this information to simplify Op, create a new simplified DAG node and
872 /// return true, returning the original and new nodes in Old and New.
873 /// Otherwise, analyze the expression and return a mask of KnownOne and
874 /// KnownZero bits for the expression (used to simplify the caller).
875 /// The KnownZero/One bits may only be accurate for those bits in the
877 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
878 APInt &KnownZero, APInt &KnownOne,
879 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
881 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
882 /// Mask are known to be either zero or one and return them in the
883 /// KnownZero/KnownOne bitsets.
884 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
888 const SelectionDAG &DAG,
889 unsigned Depth = 0) const;
891 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
892 /// targets that want to expose additional information about sign bits to the
894 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
895 unsigned Depth = 0) const;
897 struct DAGCombinerInfo {
898 void *DC; // The DAG Combiner object.
900 bool BeforeLegalizeOps;
901 bool CalledByLegalizer;
905 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc)
906 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo),
907 CalledByLegalizer(cl), DAG(dag) {}
909 bool isBeforeLegalize() const { return BeforeLegalize; }
910 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; }
911 bool isCalledByLegalizer() const { return CalledByLegalizer; }
913 void AddToWorklist(SDNode *N);
914 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
916 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
917 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
919 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
922 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
923 /// and cc. If it is unable to simplify it, return a null SDValue.
924 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
925 ISD::CondCode Cond, bool foldBooleans,
926 DAGCombinerInfo &DCI, DebugLoc dl) const;
928 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
929 /// node is a GlobalAddress + offset.
931 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
933 /// PerformDAGCombine - This method will be invoked for all target nodes and
934 /// for any target-independent nodes that the target has registered with
937 /// The semantics are as follows:
939 /// SDValue.Val == 0 - No change was made
940 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
941 /// otherwise - N should be replaced by the returned Operand.
943 /// In addition, methods provided by DAGCombinerInfo may be used to perform
944 /// more complex transformations.
946 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
948 /// isTypeDesirableForOp - Return true if the target has native support for
949 /// the specified value type and it is 'desirable' to use the type for the
950 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
951 /// instruction encodings are longer and some i16 instructions are slow.
952 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const {
953 // By default, assume all legal types are desirable.
954 return isTypeLegal(VT);
957 /// IsDesirableToPromoteOp - This method query the target whether it is
958 /// beneficial for dag combiner to promote the specified node. If true, it
959 /// should return the desired promotion type by reference.
960 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
964 //===--------------------------------------------------------------------===//
965 // TargetLowering Configuration Methods - These methods should be invoked by
966 // the derived class constructor to configure this object for the target.
970 /// setShiftAmountType - Describe the type that should be used for shift
971 /// amounts. This type defaults to the pointer type.
972 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
974 /// setBooleanContents - Specify how the target extends the result of a
975 /// boolean value from i1 to a wider type. See getBooleanContents.
976 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
978 /// setSchedulingPreference - Specify the target scheduling preference.
979 void setSchedulingPreference(Sched::Preference Pref) {
980 SchedPreferenceInfo = Pref;
983 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
984 /// use _setjmp to implement llvm.setjmp or the non _ version.
985 /// Defaults to false.
986 void setUseUnderscoreSetJmp(bool Val) {
987 UseUnderscoreSetJmp = Val;
990 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
991 /// use _longjmp to implement llvm.longjmp or the non _ version.
992 /// Defaults to false.
993 void setUseUnderscoreLongJmp(bool Val) {
994 UseUnderscoreLongJmp = Val;
997 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
998 /// specifies the register that llvm.savestack/llvm.restorestack should save
1000 void setStackPointerRegisterToSaveRestore(unsigned R) {
1001 StackPointerRegisterToSaveRestore = R;
1004 /// setExceptionPointerRegister - If set to a physical register, this sets
1005 /// the register that receives the exception address on entry to a landing
1007 void setExceptionPointerRegister(unsigned R) {
1008 ExceptionPointerRegister = R;
1011 /// setExceptionSelectorRegister - If set to a physical register, this sets
1012 /// the register that receives the exception typeid on entry to a landing
1014 void setExceptionSelectorRegister(unsigned R) {
1015 ExceptionSelectorRegister = R;
1018 /// SelectIsExpensive - Tells the code generator not to expand operations
1019 /// into sequences that use the select operations if possible.
1020 void setSelectIsExpensive(bool isExpensive = true) {
1021 SelectIsExpensive = isExpensive;
1024 /// JumpIsExpensive - Tells the code generator not to expand sequence of
1025 /// operations into a seperate sequences that increases the amount of
1027 void setJumpIsExpensive(bool isExpensive = true) {
1028 JumpIsExpensive = isExpensive;
1031 /// setIntDivIsCheap - Tells the code generator that integer divide is
1032 /// expensive, and if possible, should be replaced by an alternate sequence
1033 /// of instructions not containing an integer divide.
1034 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1036 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
1037 /// srl/add/sra for a signed divide by power of two, and let the target handle
1039 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
1041 /// addRegisterClass - Add the specified register class as an available
1042 /// regclass for the specified value type. This indicates the selector can
1043 /// handle values of that class natively.
1044 void addRegisterClass(EVT VT, TargetRegisterClass *RC) {
1045 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
1046 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1047 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
1050 /// findRepresentativeClass - Return the largest legal super-reg register class
1051 /// of the register class for the specified type and its associated "cost".
1052 virtual std::pair<const TargetRegisterClass*, uint8_t>
1053 findRepresentativeClass(EVT VT) const;
1055 /// computeRegisterProperties - Once all of the register classes are added,
1056 /// this allows us to compute derived properties we expose.
1057 void computeRegisterProperties();
1059 /// setOperationAction - Indicate that the specified operation does not work
1060 /// with the specified type and indicate what to do about it.
1061 void setOperationAction(unsigned Op, MVT VT,
1062 LegalizeAction Action) {
1063 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1064 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1067 /// setLoadExtAction - Indicate that the specified load with extension does
1068 /// not work with the specified type and indicate what to do about it.
1069 void setLoadExtAction(unsigned ExtType, MVT VT,
1070 LegalizeAction Action) {
1071 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
1072 "Table isn't big enough!");
1073 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1076 /// setTruncStoreAction - Indicate that the specified truncating store does
1077 /// not work with the specified type and indicate what to do about it.
1078 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1079 LegalizeAction Action) {
1080 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
1081 "Table isn't big enough!");
1082 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1085 /// setIndexedLoadAction - Indicate that the specified indexed load does or
1086 /// does not work with the specified type and indicate what to do abort
1087 /// it. NOTE: All indexed mode loads are initialized to Expand in
1088 /// TargetLowering.cpp
1089 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1090 LegalizeAction Action) {
1091 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1092 (unsigned)Action < 0xf && "Table isn't big enough!");
1093 // Load action are kept in the upper half.
1094 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1095 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1098 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1099 /// does not work with the specified type and indicate what to do about
1100 /// it. NOTE: All indexed mode stores are initialized to Expand in
1101 /// TargetLowering.cpp
1102 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1103 LegalizeAction Action) {
1104 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1105 (unsigned)Action < 0xf && "Table isn't big enough!");
1106 // Store action are kept in the lower half.
1107 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1108 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1111 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1112 /// supported on the target and indicate what to do about it.
1113 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1114 LegalizeAction Action) {
1115 assert(VT < MVT::LAST_VALUETYPE &&
1116 (unsigned)CC < array_lengthof(CondCodeActions) &&
1117 "Table isn't big enough!");
1118 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1119 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2;
1122 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1123 /// promotion code defaults to trying a larger integer/fp until it can find
1124 /// one that works. If that default is insufficient, this method can be used
1125 /// by the target to override the default.
1126 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1127 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1130 /// setTargetDAGCombine - Targets should invoke this method for each target
1131 /// independent node that they want to provide a custom DAG combiner for by
1132 /// implementing the PerformDAGCombine virtual method.
1133 void setTargetDAGCombine(ISD::NodeType NT) {
1134 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1135 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1138 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1139 /// bytes); default is 200
1140 void setJumpBufSize(unsigned Size) {
1144 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1145 /// alignment (in bytes); default is 0
1146 void setJumpBufAlignment(unsigned Align) {
1147 JumpBufAlignment = Align;
1150 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1151 /// alignment is zero, it means the target does not care about loop alignment.
1152 void setPrefLoopAlignment(unsigned Align) {
1153 PrefLoopAlignment = Align;
1156 /// setMinStackArgumentAlignment - Set the minimum stack alignment of an
1158 void setMinStackArgumentAlignment(unsigned Align) {
1159 MinStackArgumentAlignment = Align;
1162 /// setShouldFoldAtomicFences - Set if the target's implementation of the
1163 /// atomic operation intrinsics includes locking. Default is false.
1164 void setShouldFoldAtomicFences(bool fold) {
1165 ShouldFoldAtomicFences = fold;
1169 //===--------------------------------------------------------------------===//
1170 // Lowering methods - These methods must be implemented by targets so that
1171 // the SelectionDAGLowering code knows how to lower these.
1174 /// LowerFormalArguments - This hook must be implemented to lower the
1175 /// incoming (formal) arguments, described by the Ins array, into the
1176 /// specified DAG. The implementation should fill in the InVals array
1177 /// with legal-type argument values, and return the resulting token
1181 LowerFormalArguments(SDValue Chain,
1182 CallingConv::ID CallConv, bool isVarArg,
1183 const SmallVectorImpl<ISD::InputArg> &Ins,
1184 DebugLoc dl, SelectionDAG &DAG,
1185 SmallVectorImpl<SDValue> &InVals) const {
1186 assert(0 && "Not Implemented");
1187 return SDValue(); // this is here to silence compiler errors
1190 /// LowerCallTo - This function lowers an abstract call to a function into an
1191 /// actual call. This returns a pair of operands. The first element is the
1192 /// return value for the function (if RetTy is not VoidTy). The second
1193 /// element is the outgoing token chain. It calls LowerCall to do the actual
1195 struct ArgListEntry {
1206 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1207 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1209 typedef std::vector<ArgListEntry> ArgListTy;
1210 std::pair<SDValue, SDValue>
1211 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1212 bool isVarArg, bool isInreg, unsigned NumFixedArgs,
1213 CallingConv::ID CallConv, bool isTailCall,
1214 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
1215 SelectionDAG &DAG, DebugLoc dl) const;
1217 /// LowerCall - This hook must be implemented to lower calls into the
1218 /// the specified DAG. The outgoing arguments to the call are described
1219 /// by the Outs array, and the values to be returned by the call are
1220 /// described by the Ins array. The implementation should fill in the
1221 /// InVals array with legal-type return values from the call, and return
1222 /// the resulting token chain value.
1224 LowerCall(SDValue Chain, SDValue Callee,
1225 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
1226 const SmallVectorImpl<ISD::OutputArg> &Outs,
1227 const SmallVectorImpl<SDValue> &OutVals,
1228 const SmallVectorImpl<ISD::InputArg> &Ins,
1229 DebugLoc dl, SelectionDAG &DAG,
1230 SmallVectorImpl<SDValue> &InVals) const {
1231 assert(0 && "Not Implemented");
1232 return SDValue(); // this is here to silence compiler errors
1235 /// CanLowerReturn - This hook should be implemented to check whether the
1236 /// return values described by the Outs array can fit into the return
1237 /// registers. If false is returned, an sret-demotion is performed.
1239 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1240 const SmallVectorImpl<ISD::OutputArg> &Outs,
1241 LLVMContext &Context) const
1243 // Return true by default to get preexisting behavior.
1247 /// LowerReturn - This hook must be implemented to lower outgoing
1248 /// return values, described by the Outs array, into the specified
1249 /// DAG. The implementation should return the resulting token chain
1253 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1254 const SmallVectorImpl<ISD::OutputArg> &Outs,
1255 const SmallVectorImpl<SDValue> &OutVals,
1256 DebugLoc dl, SelectionDAG &DAG) const {
1257 assert(0 && "Not Implemented");
1258 return SDValue(); // this is here to silence compiler errors
1261 /// isUsedByReturnOnly - Return true if result of the specified node is used
1262 /// by a return node only. This is used to determine whether it is possible
1263 /// to codegen a libcall as tail call at legalization time.
1264 virtual bool isUsedByReturnOnly(SDNode *N) const {
1268 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1269 /// to legalize nodes with an illegal operand type but legal result types.
1270 /// It replaces the LowerOperation callback in the type Legalizer.
1271 /// The reason we can not do away with LowerOperation entirely is that
1272 /// LegalizeDAG isn't yet ready to use this callback.
1273 /// TODO: Consider merging with ReplaceNodeResults.
1275 /// The target places new result values for the node in Results (their number
1276 /// and types must exactly match those of the original return values of
1277 /// the node), or leaves Results empty, which indicates that the node is not
1278 /// to be custom lowered after all.
1279 /// The default implementation calls LowerOperation.
1280 virtual void LowerOperationWrapper(SDNode *N,
1281 SmallVectorImpl<SDValue> &Results,
1282 SelectionDAG &DAG) const;
1284 /// LowerOperation - This callback is invoked for operations that are
1285 /// unsupported by the target, which are registered to use 'custom' lowering,
1286 /// and whose defined values are all legal.
1287 /// If the target has no operations that require custom lowering, it need not
1288 /// implement this. The default implementation of this aborts.
1289 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
1291 /// ReplaceNodeResults - This callback is invoked when a node result type is
1292 /// illegal for the target, and the operation was registered to use 'custom'
1293 /// lowering for that result type. The target places new result values for
1294 /// the node in Results (their number and types must exactly match those of
1295 /// the original return values of the node), or leaves Results empty, which
1296 /// indicates that the node is not to be custom lowered after all.
1298 /// If the target has no operations that require custom lowering, it need not
1299 /// implement this. The default implementation aborts.
1300 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1301 SelectionDAG &DAG) const {
1302 assert(0 && "ReplaceNodeResults not implemented for this target!");
1305 /// getTargetNodeName() - This method returns the name of a target specific
1307 virtual const char *getTargetNodeName(unsigned Opcode) const;
1309 /// createFastISel - This method returns a target specific FastISel object,
1310 /// or null if the target does not support "fast" ISel.
1311 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const {
1315 //===--------------------------------------------------------------------===//
1316 // Inline Asm Support hooks
1319 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
1320 /// call to be explicit llvm code if it wants to. This is useful for
1321 /// turning simple inline asms into LLVM intrinsics, which gives the
1322 /// compiler more information about the behavior of the code.
1323 virtual bool ExpandInlineAsm(CallInst *CI) const {
1327 enum ConstraintType {
1328 C_Register, // Constraint represents specific register(s).
1329 C_RegisterClass, // Constraint represents any of register(s) in class.
1330 C_Memory, // Memory constraint.
1331 C_Other, // Something else.
1332 C_Unknown // Unsupported constraint.
1335 enum ConstraintWeight {
1337 CW_Invalid = -1, // No match.
1338 CW_Okay = 0, // Acceptable.
1339 CW_Good = 1, // Good weight.
1340 CW_Better = 2, // Better weight.
1341 CW_Best = 3, // Best weight.
1343 // Well-known weights.
1344 CW_SpecificReg = CW_Okay, // Specific register operands.
1345 CW_Register = CW_Good, // Register operands.
1346 CW_Memory = CW_Better, // Memory operands.
1347 CW_Constant = CW_Best, // Constant operand.
1348 CW_Default = CW_Okay // Default or don't know type.
1351 /// AsmOperandInfo - This contains information for each constraint that we are
1353 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1354 /// ConstraintCode - This contains the actual string for the code, like "m".
1355 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1356 /// most closely matches the operand.
1357 std::string ConstraintCode;
1359 /// ConstraintType - Information about the constraint code, e.g. Register,
1360 /// RegisterClass, Memory, Other, Unknown.
1361 TargetLowering::ConstraintType ConstraintType;
1363 /// CallOperandval - If this is the result output operand or a
1364 /// clobber, this is null, otherwise it is the incoming operand to the
1365 /// CallInst. This gets modified as the asm is processed.
1366 Value *CallOperandVal;
1368 /// ConstraintVT - The ValueType for the operand value.
1371 /// isMatchingInputConstraint - Return true of this is an input operand that
1372 /// is a matching constraint like "4".
1373 bool isMatchingInputConstraint() const;
1375 /// getMatchedOperand - If this is an input matching constraint, this method
1376 /// returns the output operand it matches.
1377 unsigned getMatchedOperand() const;
1379 /// Copy constructor for copying from an AsmOperandInfo.
1380 AsmOperandInfo(const AsmOperandInfo &info)
1381 : InlineAsm::ConstraintInfo(info),
1382 ConstraintCode(info.ConstraintCode),
1383 ConstraintType(info.ConstraintType),
1384 CallOperandVal(info.CallOperandVal),
1385 ConstraintVT(info.ConstraintVT) {
1388 /// Copy constructor for copying from a ConstraintInfo.
1389 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1390 : InlineAsm::ConstraintInfo(info),
1391 ConstraintType(TargetLowering::C_Unknown),
1392 CallOperandVal(0), ConstraintVT(MVT::Other) {
1396 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
1398 /// ParseConstraints - Split up the constraint string from the inline
1399 /// assembly value into the specific constraints and their prefixes,
1400 /// and also tie in the associated operand values.
1401 /// If this returns an empty vector, and if the constraint string itself
1402 /// isn't empty, there was an error parsing.
1403 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
1405 /// Examine constraint type and operand type and determine a weight value.
1406 /// The operand object must already have been set up with the operand type.
1407 virtual ConstraintWeight getMultipleConstraintMatchWeight(
1408 AsmOperandInfo &info, int maIndex) const;
1410 /// Examine constraint string and operand type and determine a weight value.
1411 /// The operand object must already have been set up with the operand type.
1412 virtual ConstraintWeight getSingleConstraintMatchWeight(
1413 AsmOperandInfo &info, const char *constraint) const;
1415 /// ComputeConstraintToUse - Determines the constraint code and constraint
1416 /// type to use for the specific AsmOperandInfo, setting
1417 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1418 /// being passed in is available, it can be passed in as Op, otherwise an
1419 /// empty SDValue can be passed.
1420 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1422 SelectionDAG *DAG = 0) const;
1424 /// getConstraintType - Given a constraint, return the type of constraint it
1425 /// is for this target.
1426 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1428 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1429 /// return a list of registers that can be used to satisfy the constraint.
1430 /// This should only be used for C_RegisterClass constraints.
1431 virtual std::vector<unsigned>
1432 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1435 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1436 /// {edx}), return the register number and the register class for the
1439 /// Given a register class constraint, like 'r', if this corresponds directly
1440 /// to an LLVM register class, return a register of 0 and the register class
1443 /// This should only be used for C_Register constraints. On error,
1444 /// this returns a register number of 0 and a null register class pointer..
1445 virtual std::pair<unsigned, const TargetRegisterClass*>
1446 getRegForInlineAsmConstraint(const std::string &Constraint,
1449 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1450 /// with another that has more specific requirements based on the type of the
1451 /// corresponding operand. This returns null if there is no replacement to
1453 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
1455 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1456 /// vector. If it is invalid, don't add anything to Ops.
1457 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1458 std::vector<SDValue> &Ops,
1459 SelectionDAG &DAG) const;
1461 //===--------------------------------------------------------------------===//
1462 // Instruction Emitting Hooks
1465 // EmitInstrWithCustomInserter - This method should be implemented by targets
1466 // that mark instructions with the 'usesCustomInserter' flag. These
1467 // instructions are special in various ways, which require special support to
1468 // insert. The specified MachineInstr is created but not inserted into any
1469 // basic blocks, and this method is called to expand it into a sequence of
1470 // instructions, potentially also creating new basic blocks and control flow.
1471 virtual MachineBasicBlock *
1472 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
1474 //===--------------------------------------------------------------------===//
1475 // Addressing mode description hooks (used by LSR etc).
1478 /// AddrMode - This represents an addressing mode of:
1479 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1480 /// If BaseGV is null, there is no BaseGV.
1481 /// If BaseOffs is zero, there is no base offset.
1482 /// If HasBaseReg is false, there is no base register.
1483 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1487 GlobalValue *BaseGV;
1491 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1494 /// isLegalAddressingMode - Return true if the addressing mode represented by
1495 /// AM is legal for this target, for a load/store of the specified type.
1496 /// The type may be VoidTy, in which case only return true if the addressing
1497 /// mode is legal for a load/store of any legal type.
1498 /// TODO: Handle pre/postinc as well.
1499 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1501 /// isTruncateFree - Return true if it's free to truncate a value of
1502 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1503 /// register EAX to i16 by referencing its sub-register AX.
1504 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1508 virtual bool isTruncateFree(EVT VT1, EVT VT2) const {
1512 /// isZExtFree - Return true if any actual instruction that defines a
1513 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1514 /// register. This does not necessarily include registers defined in
1515 /// unknown ways, such as incoming arguments, or copies from unknown
1516 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1517 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1518 /// all instructions that define 32-bit values implicit zero-extend the
1519 /// result out to 64 bits.
1520 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
1524 virtual bool isZExtFree(EVT VT1, EVT VT2) const {
1528 /// isNarrowingProfitable - Return true if it's profitable to narrow
1529 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1530 /// from i32 to i8 but not from i32 to i16.
1531 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const {
1535 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1536 /// icmp immediate, that is the target has icmp instructions which can compare
1537 /// a register against the immediate without having to materialize the
1538 /// immediate into a register.
1539 virtual bool isLegalICmpImmediate(int64_t Imm) const {
1543 //===--------------------------------------------------------------------===//
1544 // Div utility functions
1546 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1547 std::vector<SDNode*>* Created) const;
1548 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1549 std::vector<SDNode*>* Created) const;
1552 //===--------------------------------------------------------------------===//
1553 // Runtime Library hooks
1556 /// setLibcallName - Rename the default libcall routine name for the specified
1558 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1559 LibcallRoutineNames[Call] = Name;
1562 /// getLibcallName - Get the libcall routine name for the specified libcall.
1564 const char *getLibcallName(RTLIB::Libcall Call) const {
1565 return LibcallRoutineNames[Call];
1568 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1569 /// result of the comparison libcall against zero.
1570 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1571 CmpLibcallCCs[Call] = CC;
1574 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1575 /// the comparison libcall against zero.
1576 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1577 return CmpLibcallCCs[Call];
1580 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1581 /// specified libcall.
1582 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1583 LibcallCallingConvs[Call] = CC;
1586 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1587 /// specified libcall.
1588 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1589 return LibcallCallingConvs[Call];
1593 const TargetMachine &TM;
1594 const TargetData *TD;
1595 const TargetLoweringObjectFile &TLOF;
1597 /// PointerTy - The type to use for pointers, usually i32 or i64.
1601 /// IsLittleEndian - True if this is a little endian target.
1603 bool IsLittleEndian;
1605 /// SelectIsExpensive - Tells the code generator not to expand operations
1606 /// into sequences that use the select operations if possible.
1607 bool SelectIsExpensive;
1609 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1610 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1611 /// a real cost model is in place. If we ever optimize for size, this will be
1612 /// set to true unconditionally.
1615 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1616 /// srl/add/sra for a signed divide by power of two, and let the target handle
1618 bool Pow2DivIsCheap;
1620 /// JumpIsExpensive - Tells the code generator that it shouldn't generate
1621 /// extra flow control instructions and should attempt to combine flow
1622 /// control instructions via predication.
1623 bool JumpIsExpensive;
1625 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1626 /// llvm.setjmp. Defaults to false.
1627 bool UseUnderscoreSetJmp;
1629 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1630 /// llvm.longjmp. Defaults to false.
1631 bool UseUnderscoreLongJmp;
1633 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1637 /// BooleanContents - Information about the contents of the high-bits in
1638 /// boolean values held in a type wider than i1. See getBooleanContents.
1639 BooleanContent BooleanContents;
1641 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1642 /// total cycles or lowest register usage.
1643 Sched::Preference SchedPreferenceInfo;
1645 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1646 unsigned JumpBufSize;
1648 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1650 unsigned JumpBufAlignment;
1652 /// MinStackArgumentAlignment - The minimum alignment that any argument
1653 /// on the stack needs to have.
1655 unsigned MinStackArgumentAlignment;
1657 /// PrefLoopAlignment - The perferred loop alignment.
1659 unsigned PrefLoopAlignment;
1661 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should
1662 /// be folded into the enclosed atomic intrinsic instruction by the
1664 bool ShouldFoldAtomicFences;
1666 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1667 /// specifies the register that llvm.savestack/llvm.restorestack should save
1669 unsigned StackPointerRegisterToSaveRestore;
1671 /// ExceptionPointerRegister - If set to a physical register, this specifies
1672 /// the register that receives the exception address on entry to a landing
1674 unsigned ExceptionPointerRegister;
1676 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1677 /// the register that receives the exception typeid on entry to a landing
1679 unsigned ExceptionSelectorRegister;
1681 /// RegClassForVT - This indicates the default register class to use for
1682 /// each ValueType the target supports natively.
1683 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1684 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1685 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1687 /// RepRegClassForVT - This indicates the "representative" register class to
1688 /// use for each ValueType the target supports natively. This information is
1689 /// used by the scheduler to track register pressure. By default, the
1690 /// representative register class is the largest legal super-reg register
1691 /// class of the register class of the specified type. e.g. On x86, i8, i16,
1692 /// and i32's representative class would be GR32.
1693 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1695 /// RepRegClassCostForVT - This indicates the "cost" of the "representative"
1696 /// register class for each ValueType. The cost is used by the scheduler to
1697 /// approximate register pressure.
1698 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1700 /// TransformToType - For any value types we are promoting or expanding, this
1701 /// contains the value type that we are changing to. For Expanded types, this
1702 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1703 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1704 /// by the system, this holds the same type (e.g. i32 -> i32).
1705 EVT TransformToType[MVT::LAST_VALUETYPE];
1707 /// OpActions - For each operation and each value type, keep a LegalizeAction
1708 /// that indicates how instruction selection should deal with the operation.
1709 /// Most operations are Legal (aka, supported natively by the target), but
1710 /// operations that are not should be described. Note that operations on
1711 /// non-legal value types are not described here.
1712 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1714 /// LoadExtActions - For each load extension type and each value type,
1715 /// keep a LegalizeAction that indicates how instruction selection should deal
1716 /// with a load of a specific value type and extension type.
1717 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1719 /// TruncStoreActions - For each value type pair keep a LegalizeAction that
1720 /// indicates whether a truncating store of a specific value type and
1721 /// truncating type is legal.
1722 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1724 /// IndexedModeActions - For each indexed mode and each value type,
1725 /// keep a pair of LegalizeAction that indicates how instruction
1726 /// selection should deal with the load / store. The first dimension is the
1727 /// value_type for the reference. The second dimension represents the various
1728 /// modes for load store.
1729 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1731 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1732 /// LegalizeAction that indicates how instruction selection should
1733 /// deal with the condition code.
1734 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1736 ValueTypeActionImpl ValueTypeActions;
1738 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
1740 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1741 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1742 /// which sets a bit in this array.
1744 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1746 /// PromoteToType - For operations that must be promoted to a specific type,
1747 /// this holds the destination type. This map should be sparse, so don't hold
1750 /// Targets add entries to this map with AddPromotedToType(..), clients access
1751 /// this with getTypeToPromoteTo(..).
1752 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1755 /// LibcallRoutineNames - Stores the name each libcall.
1757 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1759 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1760 /// of each of the comparison libcall against zero.
1761 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1763 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
1765 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1768 /// When lowering \@llvm.memset this field specifies the maximum number of
1769 /// store operations that may be substituted for the call to memset. Targets
1770 /// must set this value based on the cost threshold for that target. Targets
1771 /// should assume that the memset will be done using as many of the largest
1772 /// store operations first, followed by smaller ones, if necessary, per
1773 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1774 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1775 /// store. This only applies to setting a constant array of a constant size.
1776 /// @brief Specify maximum number of store instructions per memset call.
1777 unsigned maxStoresPerMemset;
1779 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1780 /// store operations that may be substituted for a call to memcpy. Targets
1781 /// must set this value based on the cost threshold for that target. Targets
1782 /// should assume that the memcpy will be done using as many of the largest
1783 /// store operations first, followed by smaller ones, if necessary, per
1784 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1785 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1786 /// and one 1-byte store. This only applies to copying a constant array of
1788 /// @brief Specify maximum bytes of store instructions per memcpy call.
1789 unsigned maxStoresPerMemcpy;
1791 /// When lowering \@llvm.memmove this field specifies the maximum number of
1792 /// store instructions that may be substituted for a call to memmove. Targets
1793 /// must set this value based on the cost threshold for that target. Targets
1794 /// should assume that the memmove will be done using as many of the largest
1795 /// store operations first, followed by smaller ones, if necessary, per
1796 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1797 /// with 8-bit alignment would result in nine 1-byte stores. This only
1798 /// applies to copying a constant array of constant size.
1799 /// @brief Specify maximum bytes of store instructions per memmove call.
1800 unsigned maxStoresPerMemmove;
1802 /// This field specifies whether the target can benefit from code placement
1804 bool benefitFromCodePlacementOpt;
1807 /// isLegalRC - Return true if the value types that can be represented by the
1808 /// specified register class are all legal.
1809 bool isLegalRC(const TargetRegisterClass *RC) const;
1811 /// hasLegalSuperRegRegClasses - Return true if the specified register class
1812 /// has one or more super-reg register classes that are legal.
1813 bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const;
1816 /// GetReturnInfo - Given an LLVM IR type and return type attributes,
1817 /// compute the return value EVTs and flags, and optionally also
1818 /// the offsets, if the return value is being lowered to memory.
1819 void GetReturnInfo(const Type* ReturnType, Attributes attr,
1820 SmallVectorImpl<ISD::OutputArg> &Outs,
1821 const TargetLowering &TLI,
1822 SmallVectorImpl<uint64_t> *Offsets = 0);
1824 } // end llvm namespace