1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/ADT/DenseMap.h"
26 #include "llvm/AddressingMode.h"
27 #include "llvm/Attributes.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/CodeGen/RuntimeLibcalls.h"
30 #include "llvm/CodeGen/SelectionDAGNodes.h"
31 #include "llvm/InlineAsm.h"
32 #include "llvm/Support/CallSite.h"
33 #include "llvm/Support/DebugLoc.h"
34 #include "llvm/Target/TargetCallingConv.h"
35 #include "llvm/Target/TargetMachine.h"
44 class FunctionLoweringInfo;
45 class ImmutableCallSite;
47 class MachineBasicBlock;
48 class MachineFunction;
50 class MachineJumpTableInfo;
53 template<typename T> class SmallVectorImpl;
55 class TargetRegisterClass;
56 class TargetLibraryInfo;
57 class TargetLoweringObjectFile;
62 None, // No preference
63 Source, // Follow source order.
64 RegPressure, // Scheduling for lowest register pressure.
65 Hybrid, // Scheduling for both latency and register pressure.
66 ILP, // Scheduling for ILP in low register pressure mode.
67 VLIW // Scheduling for VLIW targets.
72 //===----------------------------------------------------------------------===//
73 /// TargetLowering - This class defines information used to lower LLVM code to
74 /// legal SelectionDAG operators that the target instruction selector can accept
77 /// This class also defines callbacks that targets must implement to lower
78 /// target-specific constructs to SelectionDAG operators.
80 class TargetLowering {
81 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
82 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
84 /// LegalizeAction - This enum indicates whether operations are valid for a
85 /// target, and if not, what action should be used to make them valid.
87 Legal, // The target natively supports this operation.
88 Promote, // This operation should be executed in a larger type.
89 Expand, // Try to expand this to other ops, otherwise use a libcall.
90 Custom // Use the LowerOperation hook to implement custom lowering.
93 /// LegalizeTypeAction - This enum indicates whether a types are legal for a
94 /// target, and if not, what action should be used to make them valid.
95 enum LegalizeTypeAction {
96 TypeLegal, // The target natively supports this type.
97 TypePromoteInteger, // Replace this integer with a larger one.
98 TypeExpandInteger, // Split this integer into two of half the size.
99 TypeSoftenFloat, // Convert this float to a same size integer type.
100 TypeExpandFloat, // Split this float into two of half the size.
101 TypeScalarizeVector, // Replace this one-element vector with its element.
102 TypeSplitVector, // Split this vector into two of half the size.
103 TypeWidenVector // This vector should be widened into a larger vector.
106 /// LegalizeKind holds the legalization kind that needs to happen to EVT
107 /// in order to type-legalize it.
108 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
110 enum BooleanContent { // How the target represents true/false values.
111 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
112 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
113 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
116 enum SelectSupportKind {
117 ScalarValSelect, // The target supports scalar selects (ex: cmov).
118 ScalarCondVectorVal, // The target supports selects with a scalar condition
119 // and vector values (ex: cmov).
120 VectorMaskSelect // The target supports vector selects with a vector
121 // mask (ex: x86 blends).
124 static ISD::NodeType getExtendForContent(BooleanContent Content) {
126 case UndefinedBooleanContent:
127 // Extend by adding rubbish bits.
128 return ISD::ANY_EXTEND;
129 case ZeroOrOneBooleanContent:
130 // Extend by adding zero bits.
131 return ISD::ZERO_EXTEND;
132 case ZeroOrNegativeOneBooleanContent:
133 // Extend by copying the sign bit.
134 return ISD::SIGN_EXTEND;
136 llvm_unreachable("Invalid content kind");
139 /// NOTE: The constructor takes ownership of TLOF.
140 explicit TargetLowering(const TargetMachine &TM,
141 const TargetLoweringObjectFile *TLOF);
142 virtual ~TargetLowering();
144 const TargetMachine &getTargetMachine() const { return TM; }
145 const DataLayout *getDataLayout() const { return TD; }
146 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
148 bool isBigEndian() const { return !IsLittleEndian; }
149 bool isLittleEndian() const { return IsLittleEndian; }
150 // Return the pointer type for the given address space, defaults to
151 // the pointer type from the data layout.
152 // FIXME: The default needs to be removed once all the code is updated.
153 virtual MVT getPointerTy(uint32_t AS = 0) const { return PointerTy; }
154 virtual MVT getShiftAmountTy(EVT LHSTy) const;
156 /// isSelectExpensive - Return true if the select operation is expensive for
158 bool isSelectExpensive() const { return SelectIsExpensive; }
160 virtual bool isSelectSupported(SelectSupportKind kind) const { return true; }
162 /// shouldSplitVectorElementType - Return true if a vector of the given type
163 /// should be split (TypeSplitVector) instead of promoted
164 /// (TypePromoteInteger) during type legalization.
165 virtual bool shouldSplitVectorElementType(EVT VT) const { return false; }
167 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
168 /// a sequence of several shifts, adds, and multiplies for this target.
169 bool isIntDivCheap() const { return IntDivIsCheap; }
171 /// isSlowDivBypassed - Returns true if target has indicated at least one
172 /// type should be bypassed.
173 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
175 /// getBypassSlowDivTypes - Returns map of slow types for division or
176 /// remainder with corresponding fast types
177 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
178 return BypassSlowDivWidths;
181 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
183 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
185 /// isJumpExpensive() - Return true if Flow Control is an expensive operation
186 /// that should be avoided.
187 bool isJumpExpensive() const { return JumpIsExpensive; }
189 /// isPredictableSelectExpensive - Return true if selects are only cheaper
190 /// than branches if the branch is unlikely to be predicted right.
191 bool isPredictableSelectExpensive() const {
192 return predictableSelectIsExpensive;
195 /// getSetCCResultType - Return the ValueType of the result of SETCC
196 /// operations. Also used to obtain the target's preferred type for
197 /// the condition operand of SELECT and BRCOND nodes. In the case of
198 /// BRCOND the argument passed is MVT::Other since there are no other
199 /// operands to get a type hint from.
200 virtual EVT getSetCCResultType(EVT VT) const;
202 /// getCmpLibcallReturnType - Return the ValueType for comparison
203 /// libcalls. Comparions libcalls include floating point comparion calls,
204 /// and Ordered/Unordered check calls on floating point numbers.
206 MVT::SimpleValueType getCmpLibcallReturnType() const;
208 /// getBooleanContents - For targets without i1 registers, this gives the
209 /// nature of the high-bits of boolean values held in types wider than i1.
210 /// "Boolean values" are special true/false values produced by nodes like
211 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
212 /// Not to be confused with general values promoted from i1.
213 /// Some cpus distinguish between vectors of boolean and scalars; the isVec
214 /// parameter selects between the two kinds. For example on X86 a scalar
215 /// boolean should be zero extended from i1, while the elements of a vector
216 /// of booleans should be sign extended from i1.
217 BooleanContent getBooleanContents(bool isVec) const {
218 return isVec ? BooleanVectorContents : BooleanContents;
221 /// getSchedulingPreference - Return target scheduling preference.
222 Sched::Preference getSchedulingPreference() const {
223 return SchedPreferenceInfo;
226 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to
227 /// different scheduling heuristics for different nodes. This function returns
228 /// the preference (or none) for the given node.
229 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
233 /// getRegClassFor - Return the register class that should be used for the
234 /// specified value type.
235 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
236 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
237 assert(RC && "This value type is not natively supported!");
241 /// getRepRegClassFor - Return the 'representative' register class for the
242 /// specified value type. The 'representative' register class is the largest
243 /// legal super-reg register class for the register class of the value type.
244 /// For example, on i386 the rep register class for i8, i16, and i32 are GR32;
245 /// while the rep register class is GR64 on x86_64.
246 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
247 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
251 /// getRepRegClassCostFor - Return the cost of the 'representative' register
252 /// class for the specified value type.
253 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
254 return RepRegClassCostForVT[VT.SimpleTy];
257 /// isTypeLegal - Return true if the target has native support for the
258 /// specified value type. This means that it has a register that directly
259 /// holds it without promotions or expansions.
260 bool isTypeLegal(EVT VT) const {
261 assert(!VT.isSimple() ||
262 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
263 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
266 class ValueTypeActionImpl {
267 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
268 /// that indicates how instruction selection should deal with the type.
269 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
272 ValueTypeActionImpl() {
273 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0);
276 LegalizeTypeAction getTypeAction(MVT VT) const {
277 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
280 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
281 unsigned I = VT.SimpleTy;
282 ValueTypeActions[I] = Action;
286 const ValueTypeActionImpl &getValueTypeActions() const {
287 return ValueTypeActions;
290 /// getTypeAction - Return how we should legalize values of this type, either
291 /// it is already legal (return 'Legal') or we need to promote it to a larger
292 /// type (return 'Promote'), or we need to expand it into multiple registers
293 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
294 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
295 return getTypeConversion(Context, VT).first;
297 LegalizeTypeAction getTypeAction(MVT VT) const {
298 return ValueTypeActions.getTypeAction(VT);
301 /// getTypeToTransformTo - For types supported by the target, this is an
302 /// identity function. For types that must be promoted to larger types, this
303 /// returns the larger type to promote to. For integer types that are larger
304 /// than the largest integer register, this contains one step in the expansion
305 /// to get to the smaller register. For illegal floating point types, this
306 /// returns the integer type to transform to.
307 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
308 return getTypeConversion(Context, VT).second;
311 /// getTypeToExpandTo - For types supported by the target, this is an
312 /// identity function. For types that must be expanded (i.e. integer types
313 /// that are larger than the largest integer register or illegal floating
314 /// point types), this returns the largest legal type it will be expanded to.
315 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
316 assert(!VT.isVector());
318 switch (getTypeAction(Context, VT)) {
321 case TypeExpandInteger:
322 VT = getTypeToTransformTo(Context, VT);
325 llvm_unreachable("Type is not legal nor is it to be expanded!");
330 /// getVectorTypeBreakdown - Vector types are broken down into some number of
331 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
332 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
333 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
335 /// This method returns the number of registers needed, and the VT for each
336 /// register. It also returns the VT and quantity of the intermediate values
337 /// before they are promoted/expanded.
339 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
341 unsigned &NumIntermediates,
342 MVT &RegisterVT) const;
344 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
345 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
346 /// this is the case, it returns true and store the intrinsic
347 /// information into the IntrinsicInfo that was passed to the function.
348 struct IntrinsicInfo {
349 unsigned opc; // target opcode
350 EVT memVT; // memory VT
351 const Value* ptrVal; // value representing memory location
352 int offset; // offset off of ptrVal
353 unsigned align; // alignment
354 bool vol; // is volatile?
355 bool readMem; // reads memory?
356 bool writeMem; // writes memory?
359 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
360 unsigned /*Intrinsic*/) const {
364 /// isFPImmLegal - Returns true if the target can instruction select the
365 /// specified FP immediate natively. If false, the legalizer will materialize
366 /// the FP immediate as a load from a constant pool.
367 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
371 /// isShuffleMaskLegal - Targets can use this to indicate that they only
372 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
373 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
374 /// are assumed to be legal.
375 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
380 /// canOpTrap - Returns true if the operation can trap for the value type.
381 /// VT must be a legal type. By default, we optimistically assume most
382 /// operations don't trap except for divide and remainder.
383 virtual bool canOpTrap(unsigned Op, EVT VT) const;
385 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
386 /// used by Targets can use this to indicate if there is a suitable
387 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
389 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
394 /// getOperationAction - Return how this operation should be treated: either
395 /// it is legal, needs to be promoted to a larger size, needs to be
396 /// expanded to some other code sequence, or the target has a custom expander
398 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
399 if (VT.isExtended()) return Expand;
400 // If a target-specific SDNode requires legalization, require the target
401 // to provide custom legalization for it.
402 if (Op > array_lengthof(OpActions[0])) return Custom;
403 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
404 return (LegalizeAction)OpActions[I][Op];
407 /// isOperationLegalOrCustom - Return true if the specified operation is
408 /// legal on this target or can be made legal with custom lowering. This
409 /// is used to help guide high-level lowering decisions.
410 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
411 return (VT == MVT::Other || isTypeLegal(VT)) &&
412 (getOperationAction(Op, VT) == Legal ||
413 getOperationAction(Op, VT) == Custom);
416 /// isOperationExpand - Return true if the specified operation is illegal on
417 /// this target or unlikely to be made legal with custom lowering. This is
418 /// used to help guide high-level lowering decisions.
419 bool isOperationExpand(unsigned Op, EVT VT) const {
420 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
423 /// isOperationLegal - Return true if the specified operation is legal on this
425 bool isOperationLegal(unsigned Op, EVT VT) const {
426 return (VT == MVT::Other || isTypeLegal(VT)) &&
427 getOperationAction(Op, VT) == Legal;
430 /// getLoadExtAction - Return how this load with extension should be treated:
431 /// either it is legal, needs to be promoted to a larger size, needs to be
432 /// expanded to some other code sequence, or the target has a custom expander
434 LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const {
435 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
436 "Table isn't big enough!");
437 return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType];
440 /// isLoadExtLegal - Return true if the specified load with extension is legal
442 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
443 return VT.isSimple() &&
444 getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
447 /// getTruncStoreAction - Return how this store with truncation should be
448 /// treated: either it is legal, needs to be promoted to a larger size, needs
449 /// to be expanded to some other code sequence, or the target has a custom
451 LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const {
452 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
453 "Table isn't big enough!");
454 return (LegalizeAction)TruncStoreActions[ValVT.SimpleTy]
458 /// isTruncStoreLegal - Return true if the specified store with truncation is
459 /// legal on this target.
460 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
461 return isTypeLegal(ValVT) && MemVT.isSimple() &&
462 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
465 /// getIndexedLoadAction - Return how the indexed load should be treated:
466 /// either it is legal, needs to be promoted to a larger size, needs to be
467 /// expanded to some other code sequence, or the target has a custom expander
470 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
471 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
472 "Table isn't big enough!");
473 unsigned Ty = (unsigned)VT.SimpleTy;
474 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
477 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
479 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
480 return VT.isSimple() &&
481 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
482 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
485 /// getIndexedStoreAction - Return how the indexed store should be treated:
486 /// either it is legal, needs to be promoted to a larger size, needs to be
487 /// expanded to some other code sequence, or the target has a custom expander
490 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
491 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
492 "Table isn't big enough!");
493 unsigned Ty = (unsigned)VT.SimpleTy;
494 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
497 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
499 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
500 return VT.isSimple() &&
501 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
502 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
505 /// getCondCodeAction - Return how the condition code should be treated:
506 /// either it is legal, needs to be expanded to some other code sequence,
507 /// or the target has a custom expander for it.
509 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
510 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
511 (unsigned)VT.SimpleTy < sizeof(CondCodeActions[0])*4 &&
512 "Table isn't big enough!");
513 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit
514 /// value and the upper 27 bits index into the second dimension of the
515 /// array to select what 64bit value to use.
516 LegalizeAction Action = (LegalizeAction)
517 ((CondCodeActions[CC][VT.SimpleTy >> 5] >> (2*(VT.SimpleTy & 0x1F))) & 3);
518 assert(Action != Promote && "Can't promote condition code!");
522 /// isCondCodeLegal - Return true if the specified condition code is legal
524 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
526 getCondCodeAction(CC, VT) == Legal ||
527 getCondCodeAction(CC, VT) == Custom;
531 /// getTypeToPromoteTo - If the action for this operation is to promote, this
532 /// method returns the ValueType to promote to.
533 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
534 assert(getOperationAction(Op, VT) == Promote &&
535 "This operation isn't promoted!");
537 // See if this has an explicit type specified.
538 std::map<std::pair<unsigned, MVT::SimpleValueType>,
539 MVT::SimpleValueType>::const_iterator PTTI =
540 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
541 if (PTTI != PromoteToType.end()) return PTTI->second;
543 assert((VT.isInteger() || VT.isFloatingPoint()) &&
544 "Cannot autopromote this type, add it with AddPromotedToType.");
548 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
549 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
550 "Didn't find type to promote to!");
551 } while (!isTypeLegal(NVT) ||
552 getOperationAction(Op, NVT) == Promote);
556 /// getValueType - Return the EVT corresponding to this LLVM type.
557 /// This is fixed by the LLVM operations except for the pointer size. If
558 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
559 /// counterpart (e.g. structs), otherwise it will assert.
560 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
561 // Lower scalar pointers to native pointer types.
562 if (Ty->isPointerTy()) return PointerTy;
564 if (Ty->isVectorTy()) {
565 VectorType *VTy = cast<VectorType>(Ty);
566 Type *Elm = VTy->getElementType();
567 // Lower vectors of pointers to native pointer types.
568 if (Elm->isPointerTy())
569 Elm = EVT(PointerTy).getTypeForEVT(Ty->getContext());
570 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
571 VTy->getNumElements());
573 return EVT::getEVT(Ty, AllowUnknown);
576 /// Return the MVT corresponding to this LLVM type. See getValueType.
577 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
578 return getValueType(Ty, AllowUnknown).getSimpleVT();
581 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
582 /// function arguments in the caller parameter area. This is the actual
583 /// alignment, not its logarithm.
584 virtual unsigned getByValTypeAlignment(Type *Ty) const;
586 /// getRegisterType - Return the type of registers that this ValueType will
587 /// eventually require.
588 MVT getRegisterType(MVT VT) const {
589 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
590 return RegisterTypeForVT[VT.SimpleTy];
593 /// getRegisterType - Return the type of registers that this ValueType will
594 /// eventually require.
595 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
597 assert((unsigned)VT.getSimpleVT().SimpleTy <
598 array_lengthof(RegisterTypeForVT));
599 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
604 unsigned NumIntermediates;
605 (void)getVectorTypeBreakdown(Context, VT, VT1,
606 NumIntermediates, RegisterVT);
609 if (VT.isInteger()) {
610 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
612 llvm_unreachable("Unsupported extended type!");
615 /// getNumRegisters - Return the number of registers that this ValueType will
616 /// eventually require. This is one for any types promoted to live in larger
617 /// registers, but may be more than one for types (like i64) that are split
618 /// into pieces. For types like i140, which are first promoted then expanded,
619 /// it is the number of registers needed to hold all the bits of the original
620 /// type. For an i140 on a 32 bit machine this means 5 registers.
621 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
623 assert((unsigned)VT.getSimpleVT().SimpleTy <
624 array_lengthof(NumRegistersForVT));
625 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
630 unsigned NumIntermediates;
631 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
633 if (VT.isInteger()) {
634 unsigned BitWidth = VT.getSizeInBits();
635 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
636 return (BitWidth + RegWidth - 1) / RegWidth;
638 llvm_unreachable("Unsupported extended type!");
641 /// ShouldShrinkFPConstant - If true, then instruction selection should
642 /// seek to shrink the FP constant of the specified type to a smaller type
643 /// in order to save space and / or reduce runtime.
644 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
646 /// hasTargetDAGCombine - If true, the target has custom DAG combine
647 /// transformations that it can perform for the specified node.
648 bool hasTargetDAGCombine(ISD::NodeType NT) const {
649 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
650 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
653 /// This function returns the maximum number of store operations permitted
654 /// to replace a call to llvm.memset. The value is set by the target at the
655 /// performance threshold for such a replacement. If OptSize is true,
656 /// return the limit for functions that have OptSize attribute.
657 /// @brief Get maximum # of store operations permitted for llvm.memset
658 unsigned getMaxStoresPerMemset(bool OptSize) const {
659 return OptSize ? maxStoresPerMemsetOptSize : maxStoresPerMemset;
662 /// This function returns the maximum number of store operations permitted
663 /// to replace a call to llvm.memcpy. The value is set by the target at the
664 /// performance threshold for such a replacement. If OptSize is true,
665 /// return the limit for functions that have OptSize attribute.
666 /// @brief Get maximum # of store operations permitted for llvm.memcpy
667 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
668 return OptSize ? maxStoresPerMemcpyOptSize : maxStoresPerMemcpy;
671 /// This function returns the maximum number of store operations permitted
672 /// to replace a call to llvm.memmove. The value is set by the target at the
673 /// performance threshold for such a replacement. If OptSize is true,
674 /// return the limit for functions that have OptSize attribute.
675 /// @brief Get maximum # of store operations permitted for llvm.memmove
676 unsigned getMaxStoresPerMemmove(bool OptSize) const {
677 return OptSize ? maxStoresPerMemmoveOptSize : maxStoresPerMemmove;
680 /// This function returns true if the target allows unaligned memory accesses.
681 /// of the specified type. If true, it also returns whether the unaligned
682 /// memory access is "fast" in the second argument by reference. This is used,
683 /// for example, in situations where an array copy/move/set is converted to a
684 /// sequence of store operations. It's use helps to ensure that such
685 /// replacements don't generate code that causes an alignment error (trap) on
686 /// the target machine.
687 /// @brief Determine if the target supports unaligned memory accesses.
688 virtual bool allowsUnalignedMemoryAccesses(EVT, bool *Fast = 0) const {
692 /// This function returns true if the target would benefit from code placement
694 /// @brief Determine if the target should perform code placement optimization.
695 bool shouldOptimizeCodePlacement() const {
696 return benefitFromCodePlacementOpt;
699 /// getOptimalMemOpType - Returns the target specific optimal type for load
700 /// and store operations as a result of memset, memcpy, and memmove
701 /// lowering. If DstAlign is zero that means it's safe to destination
702 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
703 /// means there isn't a need to check it against alignment requirement,
704 /// probably because the source does not need to be loaded. If 'IsMemset' is
705 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
706 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
707 /// source is constant so it does not need to be loaded.
708 /// It returns EVT::Other if the type should be determined using generic
709 /// target-independent logic.
710 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
711 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
714 bool /*MemcpyStrSrc*/,
715 MachineFunction &/*MF*/) const {
719 /// isSafeMemOpType - Returns true if it's safe to use load / store of the
720 /// specified type to expand memcpy / memset inline. This is mostly true
721 /// for all types except for some special cases. For example, on X86
722 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
723 /// also does type conversion. Note the specified type doesn't have to be
724 /// legal as the hook is used before type legalization.
725 virtual bool isSafeMemOpType(MVT VT) const {
729 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
730 /// to implement llvm.setjmp.
731 bool usesUnderscoreSetJmp() const {
732 return UseUnderscoreSetJmp;
735 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
736 /// to implement llvm.longjmp.
737 bool usesUnderscoreLongJmp() const {
738 return UseUnderscoreLongJmp;
741 /// supportJumpTables - return whether the target can generate code for
743 bool supportJumpTables() const {
744 return SupportJumpTables;
747 /// getMinimumJumpTableEntries - return integer threshold on number of
748 /// blocks to use jump tables rather than if sequence.
749 int getMinimumJumpTableEntries() const {
750 return MinimumJumpTableEntries;
753 /// getStackPointerRegisterToSaveRestore - If a physical register, this
754 /// specifies the register that llvm.savestack/llvm.restorestack should save
756 unsigned getStackPointerRegisterToSaveRestore() const {
757 return StackPointerRegisterToSaveRestore;
760 /// getExceptionPointerRegister - If a physical register, this returns
761 /// the register that receives the exception address on entry to a landing
763 unsigned getExceptionPointerRegister() const {
764 return ExceptionPointerRegister;
767 /// getExceptionSelectorRegister - If a physical register, this returns
768 /// the register that receives the exception typeid on entry to a landing
770 unsigned getExceptionSelectorRegister() const {
771 return ExceptionSelectorRegister;
774 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
775 /// set, the default is 200)
776 unsigned getJumpBufSize() const {
780 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
781 /// (if never set, the default is 0)
782 unsigned getJumpBufAlignment() const {
783 return JumpBufAlignment;
786 /// getMinStackArgumentAlignment - return the minimum stack alignment of an
788 unsigned getMinStackArgumentAlignment() const {
789 return MinStackArgumentAlignment;
792 /// getMinFunctionAlignment - return the minimum function alignment.
794 unsigned getMinFunctionAlignment() const {
795 return MinFunctionAlignment;
798 /// getPrefFunctionAlignment - return the preferred function alignment.
800 unsigned getPrefFunctionAlignment() const {
801 return PrefFunctionAlignment;
804 /// getPrefLoopAlignment - return the preferred loop alignment.
806 unsigned getPrefLoopAlignment() const {
807 return PrefLoopAlignment;
810 /// getShouldFoldAtomicFences - return whether the combiner should fold
811 /// fence MEMBARRIER instructions into the atomic intrinsic instructions.
813 bool getShouldFoldAtomicFences() const {
814 return ShouldFoldAtomicFences;
817 /// getInsertFencesFor - return whether the DAG builder should automatically
818 /// insert fences and reduce ordering for atomics.
820 bool getInsertFencesForAtomic() const {
821 return InsertFencesForAtomic;
824 /// getPreIndexedAddressParts - returns true by value, base pointer and
825 /// offset pointer and addressing mode by reference if the node's address
826 /// can be legally represented as pre-indexed load / store address.
827 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
829 ISD::MemIndexedMode &/*AM*/,
830 SelectionDAG &/*DAG*/) const {
834 /// getPostIndexedAddressParts - returns true by value, base pointer and
835 /// offset pointer and addressing mode by reference if this node can be
836 /// combined with a load / store to form a post-indexed load / store.
837 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
838 SDValue &/*Base*/, SDValue &/*Offset*/,
839 ISD::MemIndexedMode &/*AM*/,
840 SelectionDAG &/*DAG*/) const {
844 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
845 /// current function. The returned value is a member of the
846 /// MachineJumpTableInfo::JTEntryKind enum.
847 virtual unsigned getJumpTableEncoding() const;
849 virtual const MCExpr *
850 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
851 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
852 MCContext &/*Ctx*/) const {
853 llvm_unreachable("Need to implement this hook if target has custom JTIs");
856 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
858 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
859 SelectionDAG &DAG) const;
861 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
862 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
864 virtual const MCExpr *
865 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
866 unsigned JTI, MCContext &Ctx) const;
868 /// isOffsetFoldingLegal - Return true if folding a constant offset
869 /// with the given GlobalAddress is legal. It is frequently not legal in
870 /// PIC relocation models.
871 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
873 /// getStackCookieLocation - Return true if the target stores stack
874 /// protector cookies at a fixed offset in some non-standard address
875 /// space, and populates the address space and offset as
877 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
878 unsigned &/*Offset*/) const {
882 /// getMaximalGlobalOffset - Returns the maximal possible offset which can be
883 /// used for loads / stores from the global.
884 virtual unsigned getMaximalGlobalOffset() const {
888 //===--------------------------------------------------------------------===//
889 // TargetLowering Optimization Methods
892 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
893 /// SDValues for returning information from TargetLowering to its clients
894 /// that want to combine
895 struct TargetLoweringOpt {
902 explicit TargetLoweringOpt(SelectionDAG &InDAG,
904 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
906 bool LegalTypes() const { return LegalTys; }
907 bool LegalOperations() const { return LegalOps; }
909 bool CombineTo(SDValue O, SDValue N) {
915 /// ShrinkDemandedConstant - Check to see if the specified operand of the
916 /// specified instruction is a constant integer. If so, check to see if
917 /// there are any bits set in the constant that are not demanded. If so,
918 /// shrink the constant and return true.
919 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
921 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
922 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
923 /// cast, but it could be generalized for targets with other types of
924 /// implicit widening casts.
925 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
929 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
930 /// DemandedMask bits of the result of Op are ever used downstream. If we can
931 /// use this information to simplify Op, create a new simplified DAG node and
932 /// return true, returning the original and new nodes in Old and New.
933 /// Otherwise, analyze the expression and return a mask of KnownOne and
934 /// KnownZero bits for the expression (used to simplify the caller).
935 /// The KnownZero/One bits may only be accurate for those bits in the
937 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
938 APInt &KnownZero, APInt &KnownOne,
939 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
941 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
942 /// Mask are known to be either zero or one and return them in the
943 /// KnownZero/KnownOne bitsets.
944 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
947 const SelectionDAG &DAG,
948 unsigned Depth = 0) const;
950 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
951 /// targets that want to expose additional information about sign bits to the
953 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
954 unsigned Depth = 0) const;
956 struct DAGCombinerInfo {
957 void *DC; // The DAG Combiner object.
959 bool BeforeLegalizeOps;
960 bool CalledByLegalizer;
964 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc)
965 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo),
966 CalledByLegalizer(cl), DAG(dag) {}
968 bool isBeforeLegalize() const { return BeforeLegalize; }
969 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; }
970 bool isCalledByLegalizer() const { return CalledByLegalizer; }
972 void AddToWorklist(SDNode *N);
973 void RemoveFromWorklist(SDNode *N);
974 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
976 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
977 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
979 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
982 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
983 /// and cc. If it is unable to simplify it, return a null SDValue.
984 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
985 ISD::CondCode Cond, bool foldBooleans,
986 DAGCombinerInfo &DCI, DebugLoc dl) const;
988 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
989 /// node is a GlobalAddress + offset.
991 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
993 /// PerformDAGCombine - This method will be invoked for all target nodes and
994 /// for any target-independent nodes that the target has registered with
997 /// The semantics are as follows:
999 /// SDValue.Val == 0 - No change was made
1000 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
1001 /// otherwise - N should be replaced by the returned Operand.
1003 /// In addition, methods provided by DAGCombinerInfo may be used to perform
1004 /// more complex transformations.
1006 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
1008 /// isTypeDesirableForOp - Return true if the target has native support for
1009 /// the specified value type and it is 'desirable' to use the type for the
1010 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
1011 /// instruction encodings are longer and some i16 instructions are slow.
1012 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
1013 // By default, assume all legal types are desirable.
1014 return isTypeLegal(VT);
1017 /// isDesirableToPromoteOp - Return true if it is profitable for dag combiner
1018 /// to transform a floating point op of specified opcode to a equivalent op of
1019 /// an integer type. e.g. f32 load -> i32 load can be profitable on ARM.
1020 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
1025 /// IsDesirableToPromoteOp - This method query the target whether it is
1026 /// beneficial for dag combiner to promote the specified node. If true, it
1027 /// should return the desired promotion type by reference.
1028 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
1032 //===--------------------------------------------------------------------===//
1033 // TargetLowering Configuration Methods - These methods should be invoked by
1034 // the derived class constructor to configure this object for the target.
1038 /// setBooleanContents - Specify how the target extends the result of a
1039 /// boolean value from i1 to a wider type. See getBooleanContents.
1040 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
1041 /// setBooleanVectorContents - Specify how the target extends the result
1042 /// of a vector boolean value from a vector of i1 to a wider type. See
1043 /// getBooleanContents.
1044 void setBooleanVectorContents(BooleanContent Ty) {
1045 BooleanVectorContents = Ty;
1048 /// setSchedulingPreference - Specify the target scheduling preference.
1049 void setSchedulingPreference(Sched::Preference Pref) {
1050 SchedPreferenceInfo = Pref;
1053 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
1054 /// use _setjmp to implement llvm.setjmp or the non _ version.
1055 /// Defaults to false.
1056 void setUseUnderscoreSetJmp(bool Val) {
1057 UseUnderscoreSetJmp = Val;
1060 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
1061 /// use _longjmp to implement llvm.longjmp or the non _ version.
1062 /// Defaults to false.
1063 void setUseUnderscoreLongJmp(bool Val) {
1064 UseUnderscoreLongJmp = Val;
1067 /// setSupportJumpTables - Indicate whether the target can generate code for
1069 void setSupportJumpTables(bool Val) {
1070 SupportJumpTables = Val;
1073 /// setMinimumJumpTableEntries - Indicate the number of blocks to generate
1074 /// jump tables rather than if sequence.
1075 void setMinimumJumpTableEntries(int Val) {
1076 MinimumJumpTableEntries = Val;
1079 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
1080 /// specifies the register that llvm.savestack/llvm.restorestack should save
1082 void setStackPointerRegisterToSaveRestore(unsigned R) {
1083 StackPointerRegisterToSaveRestore = R;
1086 /// setExceptionPointerRegister - If set to a physical register, this sets
1087 /// the register that receives the exception address on entry to a landing
1089 void setExceptionPointerRegister(unsigned R) {
1090 ExceptionPointerRegister = R;
1093 /// setExceptionSelectorRegister - If set to a physical register, this sets
1094 /// the register that receives the exception typeid on entry to a landing
1096 void setExceptionSelectorRegister(unsigned R) {
1097 ExceptionSelectorRegister = R;
1100 /// SelectIsExpensive - Tells the code generator not to expand operations
1101 /// into sequences that use the select operations if possible.
1102 void setSelectIsExpensive(bool isExpensive = true) {
1103 SelectIsExpensive = isExpensive;
1106 /// JumpIsExpensive - Tells the code generator not to expand sequence of
1107 /// operations into a separate sequences that increases the amount of
1109 void setJumpIsExpensive(bool isExpensive = true) {
1110 JumpIsExpensive = isExpensive;
1113 /// setIntDivIsCheap - Tells the code generator that integer divide is
1114 /// expensive, and if possible, should be replaced by an alternate sequence
1115 /// of instructions not containing an integer divide.
1116 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1118 /// addBypassSlowDiv - Tells the code generator which bitwidths to bypass.
1119 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1120 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1123 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
1124 /// srl/add/sra for a signed divide by power of two, and let the target handle
1126 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
1128 /// addRegisterClass - Add the specified register class as an available
1129 /// regclass for the specified value type. This indicates the selector can
1130 /// handle values of that class natively.
1131 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1132 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1133 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1134 RegClassForVT[VT.SimpleTy] = RC;
1137 /// findRepresentativeClass - Return the largest legal super-reg register class
1138 /// of the register class for the specified type and its associated "cost".
1139 virtual std::pair<const TargetRegisterClass*, uint8_t>
1140 findRepresentativeClass(MVT VT) const;
1142 /// computeRegisterProperties - Once all of the register classes are added,
1143 /// this allows us to compute derived properties we expose.
1144 void computeRegisterProperties();
1146 /// setOperationAction - Indicate that the specified operation does not work
1147 /// with the specified type and indicate what to do about it.
1148 void setOperationAction(unsigned Op, MVT VT,
1149 LegalizeAction Action) {
1150 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1151 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1154 /// setLoadExtAction - Indicate that the specified load with extension does
1155 /// not work with the specified type and indicate what to do about it.
1156 void setLoadExtAction(unsigned ExtType, MVT VT,
1157 LegalizeAction Action) {
1158 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
1159 "Table isn't big enough!");
1160 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1163 /// setTruncStoreAction - Indicate that the specified truncating store does
1164 /// not work with the specified type and indicate what to do about it.
1165 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1166 LegalizeAction Action) {
1167 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
1168 "Table isn't big enough!");
1169 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1172 /// setIndexedLoadAction - Indicate that the specified indexed load does or
1173 /// does not work with the specified type and indicate what to do abort
1174 /// it. NOTE: All indexed mode loads are initialized to Expand in
1175 /// TargetLowering.cpp
1176 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1177 LegalizeAction Action) {
1178 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1179 (unsigned)Action < 0xf && "Table isn't big enough!");
1180 // Load action are kept in the upper half.
1181 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1182 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1185 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1186 /// does not work with the specified type and indicate what to do about
1187 /// it. NOTE: All indexed mode stores are initialized to Expand in
1188 /// TargetLowering.cpp
1189 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1190 LegalizeAction Action) {
1191 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1192 (unsigned)Action < 0xf && "Table isn't big enough!");
1193 // Store action are kept in the lower half.
1194 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1195 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1198 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1199 /// supported on the target and indicate what to do about it.
1200 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1201 LegalizeAction Action) {
1202 assert(VT < MVT::LAST_VALUETYPE &&
1203 (unsigned)CC < array_lengthof(CondCodeActions) &&
1204 "Table isn't big enough!");
1205 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit
1206 /// value and the upper 27 bits index into the second dimension of the
1207 /// array to select what 64bit value to use.
1208 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5]
1209 &= ~(uint64_t(3UL) << (VT.SimpleTy & 0x1F)*2);
1210 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5]
1211 |= (uint64_t)Action << (VT.SimpleTy & 0x1F)*2;
1214 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1215 /// promotion code defaults to trying a larger integer/fp until it can find
1216 /// one that works. If that default is insufficient, this method can be used
1217 /// by the target to override the default.
1218 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1219 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1222 /// setTargetDAGCombine - Targets should invoke this method for each target
1223 /// independent node that they want to provide a custom DAG combiner for by
1224 /// implementing the PerformDAGCombine virtual method.
1225 void setTargetDAGCombine(ISD::NodeType NT) {
1226 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1227 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1230 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1231 /// bytes); default is 200
1232 void setJumpBufSize(unsigned Size) {
1236 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1237 /// alignment (in bytes); default is 0
1238 void setJumpBufAlignment(unsigned Align) {
1239 JumpBufAlignment = Align;
1242 /// setMinFunctionAlignment - Set the target's minimum function alignment (in
1244 void setMinFunctionAlignment(unsigned Align) {
1245 MinFunctionAlignment = Align;
1248 /// setPrefFunctionAlignment - Set the target's preferred function alignment.
1249 /// This should be set if there is a performance benefit to
1250 /// higher-than-minimum alignment (in log2(bytes))
1251 void setPrefFunctionAlignment(unsigned Align) {
1252 PrefFunctionAlignment = Align;
1255 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1256 /// alignment is zero, it means the target does not care about loop alignment.
1257 /// The alignment is specified in log2(bytes).
1258 void setPrefLoopAlignment(unsigned Align) {
1259 PrefLoopAlignment = Align;
1262 /// setMinStackArgumentAlignment - Set the minimum stack alignment of an
1263 /// argument (in log2(bytes)).
1264 void setMinStackArgumentAlignment(unsigned Align) {
1265 MinStackArgumentAlignment = Align;
1268 /// setShouldFoldAtomicFences - Set if the target's implementation of the
1269 /// atomic operation intrinsics includes locking. Default is false.
1270 void setShouldFoldAtomicFences(bool fold) {
1271 ShouldFoldAtomicFences = fold;
1274 /// setInsertFencesForAtomic - Set if the DAG builder should
1275 /// automatically insert fences and reduce the order of atomic memory
1276 /// operations to Monotonic.
1277 void setInsertFencesForAtomic(bool fence) {
1278 InsertFencesForAtomic = fence;
1282 //===--------------------------------------------------------------------===//
1283 // Lowering methods - These methods must be implemented by targets so that
1284 // the SelectionDAGBuilder code knows how to lower these.
1287 /// LowerFormalArguments - This hook must be implemented to lower the
1288 /// incoming (formal) arguments, described by the Ins array, into the
1289 /// specified DAG. The implementation should fill in the InVals array
1290 /// with legal-type argument values, and return the resulting token
1294 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
1296 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
1297 DebugLoc /*dl*/, SelectionDAG &/*DAG*/,
1298 SmallVectorImpl<SDValue> &/*InVals*/) const {
1299 llvm_unreachable("Not Implemented");
1302 struct ArgListEntry {
1313 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1314 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1316 typedef std::vector<ArgListEntry> ArgListTy;
1318 /// CallLoweringInfo - This structure contains all information that is
1319 /// necessary for lowering calls. It is passed to TLI::LowerCallTo when the
1320 /// SelectionDAG builder needs to lower a call, and targets will see this
1321 /// struct in their LowerCall implementation.
1322 struct CallLoweringInfo {
1329 bool DoesNotReturn : 1;
1330 bool IsReturnValueUsed : 1;
1332 // IsTailCall should be modified by implementations of
1333 // TargetLowering::LowerCall that perform tail call conversions.
1336 unsigned NumFixedArgs;
1337 CallingConv::ID CallConv;
1342 ImmutableCallSite *CS;
1343 SmallVector<ISD::OutputArg, 32> Outs;
1344 SmallVector<SDValue, 32> OutVals;
1345 SmallVector<ISD::InputArg, 32> Ins;
1348 /// CallLoweringInfo - Constructs a call lowering context based on the
1349 /// ImmutableCallSite \p cs.
1350 CallLoweringInfo(SDValue chain, Type *retTy,
1351 FunctionType *FTy, bool isTailCall, SDValue callee,
1352 ArgListTy &args, SelectionDAG &dag, DebugLoc dl,
1353 ImmutableCallSite &cs)
1354 : Chain(chain), RetTy(retTy), RetSExt(cs.paramHasAttr(0, Attribute::SExt)),
1355 RetZExt(cs.paramHasAttr(0, Attribute::ZExt)), IsVarArg(FTy->isVarArg()),
1356 IsInReg(cs.paramHasAttr(0, Attribute::InReg)),
1357 DoesNotReturn(cs.doesNotReturn()),
1358 IsReturnValueUsed(!cs.getInstruction()->use_empty()),
1359 IsTailCall(isTailCall), NumFixedArgs(FTy->getNumParams()),
1360 CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag),
1363 /// CallLoweringInfo - Constructs a call lowering context based on the
1364 /// provided call information.
1365 CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt,
1366 bool isVarArg, bool isInReg, unsigned numFixedArgs,
1367 CallingConv::ID callConv, bool isTailCall,
1368 bool doesNotReturn, bool isReturnValueUsed, SDValue callee,
1369 ArgListTy &args, SelectionDAG &dag, DebugLoc dl)
1370 : Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt),
1371 IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn),
1372 IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall),
1373 NumFixedArgs(numFixedArgs), CallConv(callConv), Callee(callee),
1374 Args(args), DAG(dag), DL(dl), CS(NULL) {}
1377 /// LowerCallTo - This function lowers an abstract call to a function into an
1378 /// actual call. This returns a pair of operands. The first element is the
1379 /// return value for the function (if RetTy is not VoidTy). The second
1380 /// element is the outgoing token chain. It calls LowerCall to do the actual
1382 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
1384 /// LowerCall - This hook must be implemented to lower calls into the
1385 /// the specified DAG. The outgoing arguments to the call are described
1386 /// by the Outs array, and the values to be returned by the call are
1387 /// described by the Ins array. The implementation should fill in the
1388 /// InVals array with legal-type return values from the call, and return
1389 /// the resulting token chain value.
1391 LowerCall(CallLoweringInfo &/*CLI*/,
1392 SmallVectorImpl<SDValue> &/*InVals*/) const {
1393 llvm_unreachable("Not Implemented");
1396 /// HandleByVal - Target-specific cleanup for formal ByVal parameters.
1397 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
1399 /// CanLowerReturn - This hook should be implemented to check whether the
1400 /// return values described by the Outs array can fit into the return
1401 /// registers. If false is returned, an sret-demotion is performed.
1403 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
1404 MachineFunction &/*MF*/, bool /*isVarArg*/,
1405 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
1406 LLVMContext &/*Context*/) const
1408 // Return true by default to get preexisting behavior.
1412 /// LowerReturn - This hook must be implemented to lower outgoing
1413 /// return values, described by the Outs array, into the specified
1414 /// DAG. The implementation should return the resulting token chain
1418 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
1420 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
1421 const SmallVectorImpl<SDValue> &/*OutVals*/,
1422 DebugLoc /*dl*/, SelectionDAG &/*DAG*/) const {
1423 llvm_unreachable("Not Implemented");
1426 /// isUsedByReturnOnly - Return true if result of the specified node is used
1427 /// by a return node only. It also compute and return the input chain for the
1429 /// This is used to determine whether it is possible
1430 /// to codegen a libcall as tail call at legalization time.
1431 virtual bool isUsedByReturnOnly(SDNode *, SDValue &Chain) const {
1435 /// mayBeEmittedAsTailCall - Return true if the target may be able emit the
1436 /// call instruction as a tail call. This is used by optimization passes to
1437 /// determine if it's profitable to duplicate return instructions to enable
1438 /// tailcall optimization.
1439 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
1443 /// getTypeForExtArgOrReturn - Return the type that should be used to zero or
1444 /// sign extend a zeroext/signext integer argument or return value.
1445 /// FIXME: Most C calling convention requires the return type to be promoted,
1446 /// but this is not true all the time, e.g. i1 on x86-64. It is also not
1447 /// necessary for non-C calling conventions. The frontend should handle this
1448 /// and include all of the necessary information.
1449 virtual MVT getTypeForExtArgOrReturn(MVT VT,
1450 ISD::NodeType /*ExtendKind*/) const {
1451 MVT MinVT = getRegisterType(MVT::i32);
1452 return VT.bitsLT(MinVT) ? MinVT : VT;
1455 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1456 /// to legalize nodes with an illegal operand type but legal result types.
1457 /// It replaces the LowerOperation callback in the type Legalizer.
1458 /// The reason we can not do away with LowerOperation entirely is that
1459 /// LegalizeDAG isn't yet ready to use this callback.
1460 /// TODO: Consider merging with ReplaceNodeResults.
1462 /// The target places new result values for the node in Results (their number
1463 /// and types must exactly match those of the original return values of
1464 /// the node), or leaves Results empty, which indicates that the node is not
1465 /// to be custom lowered after all.
1466 /// The default implementation calls LowerOperation.
1467 virtual void LowerOperationWrapper(SDNode *N,
1468 SmallVectorImpl<SDValue> &Results,
1469 SelectionDAG &DAG) const;
1471 /// LowerOperation - This callback is invoked for operations that are
1472 /// unsupported by the target, which are registered to use 'custom' lowering,
1473 /// and whose defined values are all legal.
1474 /// If the target has no operations that require custom lowering, it need not
1475 /// implement this. The default implementation of this aborts.
1476 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
1478 /// ReplaceNodeResults - This callback is invoked when a node result type is
1479 /// illegal for the target, and the operation was registered to use 'custom'
1480 /// lowering for that result type. The target places new result values for
1481 /// the node in Results (their number and types must exactly match those of
1482 /// the original return values of the node), or leaves Results empty, which
1483 /// indicates that the node is not to be custom lowered after all.
1485 /// If the target has no operations that require custom lowering, it need not
1486 /// implement this. The default implementation aborts.
1487 virtual void ReplaceNodeResults(SDNode * /*N*/,
1488 SmallVectorImpl<SDValue> &/*Results*/,
1489 SelectionDAG &/*DAG*/) const {
1490 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
1493 /// getTargetNodeName() - This method returns the name of a target specific
1495 virtual const char *getTargetNodeName(unsigned Opcode) const;
1497 /// createFastISel - This method returns a target specific FastISel object,
1498 /// or null if the target does not support "fast" ISel.
1499 virtual FastISel *createFastISel(FunctionLoweringInfo &,
1500 const TargetLibraryInfo *) const {
1504 //===--------------------------------------------------------------------===//
1505 // Inline Asm Support hooks
1508 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
1509 /// call to be explicit llvm code if it wants to. This is useful for
1510 /// turning simple inline asms into LLVM intrinsics, which gives the
1511 /// compiler more information about the behavior of the code.
1512 virtual bool ExpandInlineAsm(CallInst *) const {
1516 enum ConstraintType {
1517 C_Register, // Constraint represents specific register(s).
1518 C_RegisterClass, // Constraint represents any of register(s) in class.
1519 C_Memory, // Memory constraint.
1520 C_Other, // Something else.
1521 C_Unknown // Unsupported constraint.
1524 enum ConstraintWeight {
1526 CW_Invalid = -1, // No match.
1527 CW_Okay = 0, // Acceptable.
1528 CW_Good = 1, // Good weight.
1529 CW_Better = 2, // Better weight.
1530 CW_Best = 3, // Best weight.
1532 // Well-known weights.
1533 CW_SpecificReg = CW_Okay, // Specific register operands.
1534 CW_Register = CW_Good, // Register operands.
1535 CW_Memory = CW_Better, // Memory operands.
1536 CW_Constant = CW_Best, // Constant operand.
1537 CW_Default = CW_Okay // Default or don't know type.
1540 /// AsmOperandInfo - This contains information for each constraint that we are
1542 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1543 /// ConstraintCode - This contains the actual string for the code, like "m".
1544 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1545 /// most closely matches the operand.
1546 std::string ConstraintCode;
1548 /// ConstraintType - Information about the constraint code, e.g. Register,
1549 /// RegisterClass, Memory, Other, Unknown.
1550 TargetLowering::ConstraintType ConstraintType;
1552 /// CallOperandval - If this is the result output operand or a
1553 /// clobber, this is null, otherwise it is the incoming operand to the
1554 /// CallInst. This gets modified as the asm is processed.
1555 Value *CallOperandVal;
1557 /// ConstraintVT - The ValueType for the operand value.
1560 /// isMatchingInputConstraint - Return true of this is an input operand that
1561 /// is a matching constraint like "4".
1562 bool isMatchingInputConstraint() const;
1564 /// getMatchedOperand - If this is an input matching constraint, this method
1565 /// returns the output operand it matches.
1566 unsigned getMatchedOperand() const;
1568 /// Copy constructor for copying from an AsmOperandInfo.
1569 AsmOperandInfo(const AsmOperandInfo &info)
1570 : InlineAsm::ConstraintInfo(info),
1571 ConstraintCode(info.ConstraintCode),
1572 ConstraintType(info.ConstraintType),
1573 CallOperandVal(info.CallOperandVal),
1574 ConstraintVT(info.ConstraintVT) {
1577 /// Copy constructor for copying from a ConstraintInfo.
1578 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1579 : InlineAsm::ConstraintInfo(info),
1580 ConstraintType(TargetLowering::C_Unknown),
1581 CallOperandVal(0), ConstraintVT(MVT::Other) {
1585 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
1587 /// ParseConstraints - Split up the constraint string from the inline
1588 /// assembly value into the specific constraints and their prefixes,
1589 /// and also tie in the associated operand values.
1590 /// If this returns an empty vector, and if the constraint string itself
1591 /// isn't empty, there was an error parsing.
1592 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
1594 /// Examine constraint type and operand type and determine a weight value.
1595 /// The operand object must already have been set up with the operand type.
1596 virtual ConstraintWeight getMultipleConstraintMatchWeight(
1597 AsmOperandInfo &info, int maIndex) const;
1599 /// Examine constraint string and operand type and determine a weight value.
1600 /// The operand object must already have been set up with the operand type.
1601 virtual ConstraintWeight getSingleConstraintMatchWeight(
1602 AsmOperandInfo &info, const char *constraint) const;
1604 /// ComputeConstraintToUse - Determines the constraint code and constraint
1605 /// type to use for the specific AsmOperandInfo, setting
1606 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1607 /// being passed in is available, it can be passed in as Op, otherwise an
1608 /// empty SDValue can be passed.
1609 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1611 SelectionDAG *DAG = 0) const;
1613 /// getConstraintType - Given a constraint, return the type of constraint it
1614 /// is for this target.
1615 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1617 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1618 /// {edx}), return the register number and the register class for the
1621 /// Given a register class constraint, like 'r', if this corresponds directly
1622 /// to an LLVM register class, return a register of 0 and the register class
1625 /// This should only be used for C_Register constraints. On error,
1626 /// this returns a register number of 0 and a null register class pointer..
1627 virtual std::pair<unsigned, const TargetRegisterClass*>
1628 getRegForInlineAsmConstraint(const std::string &Constraint,
1631 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1632 /// with another that has more specific requirements based on the type of the
1633 /// corresponding operand. This returns null if there is no replacement to
1635 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
1637 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1638 /// vector. If it is invalid, don't add anything to Ops.
1639 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
1640 std::vector<SDValue> &Ops,
1641 SelectionDAG &DAG) const;
1643 //===--------------------------------------------------------------------===//
1644 // Instruction Emitting Hooks
1647 // EmitInstrWithCustomInserter - This method should be implemented by targets
1648 // that mark instructions with the 'usesCustomInserter' flag. These
1649 // instructions are special in various ways, which require special support to
1650 // insert. The specified MachineInstr is created but not inserted into any
1651 // basic blocks, and this method is called to expand it into a sequence of
1652 // instructions, potentially also creating new basic blocks and control flow.
1653 virtual MachineBasicBlock *
1654 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
1656 /// AdjustInstrPostInstrSelection - This method should be implemented by
1657 /// targets that mark instructions with the 'hasPostISelHook' flag. These
1658 /// instructions must be adjusted after instruction selection by target hooks.
1659 /// e.g. To fill in optional defs for ARM 's' setting instructions.
1661 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
1663 //===--------------------------------------------------------------------===//
1664 // Addressing mode description hooks (used by LSR etc).
1667 /// GetAddrModeArguments - CodeGenPrepare sinks address calculations into the
1668 /// same BB as Load/Store instructions reading the address. This allows as
1669 /// much computation as possible to be done in the address mode for that
1670 /// operand. This hook lets targets also pass back when this should be done
1671 /// on intrinsics which load/store.
1672 virtual bool GetAddrModeArguments(IntrinsicInst *I,
1673 SmallVectorImpl<Value*> &Ops,
1674 Type *&AccessTy) const {
1678 /// isLegalAddressingMode - Return true if the addressing mode represented by
1679 /// AM is legal for this target, for a load/store of the specified type.
1680 /// The type may be VoidTy, in which case only return true if the addressing
1681 /// mode is legal for a load/store of any legal type.
1682 /// TODO: Handle pre/postinc as well.
1683 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1685 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1686 /// icmp immediate, that is the target has icmp instructions which can compare
1687 /// a register against the immediate without having to materialize the
1688 /// immediate into a register.
1689 virtual bool isLegalICmpImmediate(int64_t) const {
1693 /// isLegalAddImmediate - Return true if the specified immediate is legal
1694 /// add immediate, that is the target has add instructions which can add
1695 /// a register with the immediate without having to materialize the
1696 /// immediate into a register.
1697 virtual bool isLegalAddImmediate(int64_t) const {
1701 /// isTruncateFree - Return true if it's free to truncate a value of
1702 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1703 /// register EAX to i16 by referencing its sub-register AX.
1704 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1708 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1712 /// isZExtFree - Return true if any actual instruction that defines a
1713 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1714 /// register. This does not necessarily include registers defined in
1715 /// unknown ways, such as incoming arguments, or copies from unknown
1716 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1717 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1718 /// all instructions that define 32-bit values implicit zero-extend the
1719 /// result out to 64 bits.
1720 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1724 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1728 /// isZExtFree - Return true if zero-extending the specific node Val to type
1729 /// VT2 is free (either because it's implicitly zero-extended such as ARM
1730 /// ldrb / ldrh or because it's folded such as X86 zero-extending loads).
1731 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1732 return isZExtFree(Val.getValueType(), VT2);
1735 /// isFNegFree - Return true if an fneg operation is free to the point where
1736 /// it is never worthwhile to replace it with a bitwise operation.
1737 virtual bool isFNegFree(EVT) const {
1741 /// isFAbsFree - Return true if an fneg operation is free to the point where
1742 /// it is never worthwhile to replace it with a bitwise operation.
1743 virtual bool isFAbsFree(EVT) const {
1747 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
1748 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
1749 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
1750 /// is expanded to mul + add.
1751 virtual bool isFMAFasterThanMulAndAdd(EVT) const {
1755 /// isNarrowingProfitable - Return true if it's profitable to narrow
1756 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1757 /// from i32 to i8 but not from i32 to i16.
1758 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1762 //===--------------------------------------------------------------------===//
1763 // Div utility functions
1765 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
1766 SelectionDAG &DAG) const;
1767 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
1768 std::vector<SDNode*> *Created) const;
1769 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
1770 std::vector<SDNode*> *Created) const;
1773 //===--------------------------------------------------------------------===//
1774 // Runtime Library hooks
1777 /// setLibcallName - Rename the default libcall routine name for the specified
1779 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1780 LibcallRoutineNames[Call] = Name;
1783 /// getLibcallName - Get the libcall routine name for the specified libcall.
1785 const char *getLibcallName(RTLIB::Libcall Call) const {
1786 return LibcallRoutineNames[Call];
1789 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1790 /// result of the comparison libcall against zero.
1791 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1792 CmpLibcallCCs[Call] = CC;
1795 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1796 /// the comparison libcall against zero.
1797 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1798 return CmpLibcallCCs[Call];
1801 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1802 /// specified libcall.
1803 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1804 LibcallCallingConvs[Call] = CC;
1807 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1808 /// specified libcall.
1809 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1810 return LibcallCallingConvs[Call];
1814 const TargetMachine &TM;
1815 const DataLayout *TD;
1816 const TargetLoweringObjectFile &TLOF;
1818 /// PointerTy - The type to use for pointers for the default address space,
1819 /// usually i32 or i64.
1823 /// IsLittleEndian - True if this is a little endian target.
1825 bool IsLittleEndian;
1827 /// SelectIsExpensive - Tells the code generator not to expand operations
1828 /// into sequences that use the select operations if possible.
1829 bool SelectIsExpensive;
1831 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1832 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1833 /// a real cost model is in place. If we ever optimize for size, this will be
1834 /// set to true unconditionally.
1837 /// BypassSlowDivMap - Tells the code generator to bypass slow divide or
1838 /// remainder instructions. For example, BypassSlowDivWidths[32,8] tells the
1839 /// code generator to bypass 32-bit integer div/rem with an 8-bit unsigned
1840 /// integer div/rem when the operands are positive and less than 256.
1841 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1843 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1844 /// srl/add/sra for a signed divide by power of two, and let the target handle
1846 bool Pow2DivIsCheap;
1848 /// JumpIsExpensive - Tells the code generator that it shouldn't generate
1849 /// extra flow control instructions and should attempt to combine flow
1850 /// control instructions via predication.
1851 bool JumpIsExpensive;
1853 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1854 /// llvm.setjmp. Defaults to false.
1855 bool UseUnderscoreSetJmp;
1857 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1858 /// llvm.longjmp. Defaults to false.
1859 bool UseUnderscoreLongJmp;
1861 /// SupportJumpTables - Whether the target can generate code for jumptables.
1862 /// If it's not true, then each jumptable must be lowered into if-then-else's.
1863 bool SupportJumpTables;
1865 /// MinimumJumpTableEntries - Number of blocks threshold to use jump tables.
1866 int MinimumJumpTableEntries;
1868 /// BooleanContents - Information about the contents of the high-bits in
1869 /// boolean values held in a type wider than i1. See getBooleanContents.
1870 BooleanContent BooleanContents;
1871 /// BooleanVectorContents - Information about the contents of the high-bits
1872 /// in boolean vector values when the element type is wider than i1. See
1873 /// getBooleanContents.
1874 BooleanContent BooleanVectorContents;
1876 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1877 /// total cycles or lowest register usage.
1878 Sched::Preference SchedPreferenceInfo;
1880 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1881 unsigned JumpBufSize;
1883 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1885 unsigned JumpBufAlignment;
1887 /// MinStackArgumentAlignment - The minimum alignment that any argument
1888 /// on the stack needs to have.
1890 unsigned MinStackArgumentAlignment;
1892 /// MinFunctionAlignment - The minimum function alignment (used when
1893 /// optimizing for size, and to prevent explicitly provided alignment
1894 /// from leading to incorrect code).
1896 unsigned MinFunctionAlignment;
1898 /// PrefFunctionAlignment - The preferred function alignment (used when
1899 /// alignment unspecified and optimizing for speed).
1901 unsigned PrefFunctionAlignment;
1903 /// PrefLoopAlignment - The preferred loop alignment.
1905 unsigned PrefLoopAlignment;
1907 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should
1908 /// be folded into the enclosed atomic intrinsic instruction by the
1910 bool ShouldFoldAtomicFences;
1912 /// InsertFencesForAtomic - Whether the DAG builder should automatically
1913 /// insert fences and reduce ordering for atomics. (This will be set for
1914 /// for most architectures with weak memory ordering.)
1915 bool InsertFencesForAtomic;
1917 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1918 /// specifies the register that llvm.savestack/llvm.restorestack should save
1920 unsigned StackPointerRegisterToSaveRestore;
1922 /// ExceptionPointerRegister - If set to a physical register, this specifies
1923 /// the register that receives the exception address on entry to a landing
1925 unsigned ExceptionPointerRegister;
1927 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1928 /// the register that receives the exception typeid on entry to a landing
1930 unsigned ExceptionSelectorRegister;
1932 /// RegClassForVT - This indicates the default register class to use for
1933 /// each ValueType the target supports natively.
1934 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1935 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1936 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1938 /// RepRegClassForVT - This indicates the "representative" register class to
1939 /// use for each ValueType the target supports natively. This information is
1940 /// used by the scheduler to track register pressure. By default, the
1941 /// representative register class is the largest legal super-reg register
1942 /// class of the register class of the specified type. e.g. On x86, i8, i16,
1943 /// and i32's representative class would be GR32.
1944 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1946 /// RepRegClassCostForVT - This indicates the "cost" of the "representative"
1947 /// register class for each ValueType. The cost is used by the scheduler to
1948 /// approximate register pressure.
1949 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1951 /// TransformToType - For any value types we are promoting or expanding, this
1952 /// contains the value type that we are changing to. For Expanded types, this
1953 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1954 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1955 /// by the system, this holds the same type (e.g. i32 -> i32).
1956 MVT TransformToType[MVT::LAST_VALUETYPE];
1958 /// OpActions - For each operation and each value type, keep a LegalizeAction
1959 /// that indicates how instruction selection should deal with the operation.
1960 /// Most operations are Legal (aka, supported natively by the target), but
1961 /// operations that are not should be described. Note that operations on
1962 /// non-legal value types are not described here.
1963 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1965 /// LoadExtActions - For each load extension type and each value type,
1966 /// keep a LegalizeAction that indicates how instruction selection should deal
1967 /// with a load of a specific value type and extension type.
1968 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1970 /// TruncStoreActions - For each value type pair keep a LegalizeAction that
1971 /// indicates whether a truncating store of a specific value type and
1972 /// truncating type is legal.
1973 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1975 /// IndexedModeActions - For each indexed mode and each value type,
1976 /// keep a pair of LegalizeAction that indicates how instruction
1977 /// selection should deal with the load / store. The first dimension is the
1978 /// value_type for the reference. The second dimension represents the various
1979 /// modes for load store.
1980 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1982 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1983 /// LegalizeAction that indicates how instruction selection should
1984 /// deal with the condition code.
1985 /// Because each CC action takes up 2 bits, we need to have the array size
1986 /// be large enough to fit all of the value types. This can be done by
1987 /// dividing the MVT::LAST_VALUETYPE by 32 and adding one.
1988 uint64_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE / 32) + 1];
1990 ValueTypeActionImpl ValueTypeActions;
1994 getTypeConversion(LLVMContext &Context, EVT VT) const {
1995 // If this is a simple type, use the ComputeRegisterProp mechanism.
1996 if (VT.isSimple()) {
1997 MVT SVT = VT.getSimpleVT();
1998 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1999 MVT NVT = TransformToType[SVT.SimpleTy];
2000 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
2004 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)
2005 && "Promote may not follow Expand or Promote");
2007 if (LA == TypeSplitVector)
2008 return LegalizeKind(LA, EVT::getVectorVT(Context,
2009 SVT.getVectorElementType(),
2010 SVT.getVectorNumElements()/2));
2011 if (LA == TypeScalarizeVector)
2012 return LegalizeKind(LA, SVT.getVectorElementType());
2013 return LegalizeKind(LA, NVT);
2016 // Handle Extended Scalar Types.
2017 if (!VT.isVector()) {
2018 assert(VT.isInteger() && "Float types must be simple");
2019 unsigned BitSize = VT.getSizeInBits();
2020 // First promote to a power-of-two size, then expand if necessary.
2021 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
2022 EVT NVT = VT.getRoundIntegerType(Context);
2023 assert(NVT != VT && "Unable to round integer VT");
2024 LegalizeKind NextStep = getTypeConversion(Context, NVT);
2025 // Avoid multi-step promotion.
2026 if (NextStep.first == TypePromoteInteger) return NextStep;
2027 // Return rounded integer type.
2028 return LegalizeKind(TypePromoteInteger, NVT);
2031 return LegalizeKind(TypeExpandInteger,
2032 EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
2035 // Handle vector types.
2036 unsigned NumElts = VT.getVectorNumElements();
2037 EVT EltVT = VT.getVectorElementType();
2039 // Vectors with only one element are always scalarized.
2041 return LegalizeKind(TypeScalarizeVector, EltVT);
2043 // Try to widen vector elements until a legal type is found.
2044 if (EltVT.isInteger()) {
2045 // Vectors with a number of elements that is not a power of two are always
2046 // widened, for example <3 x float> -> <4 x float>.
2047 if (!VT.isPow2VectorType()) {
2048 NumElts = (unsigned)NextPowerOf2(NumElts);
2049 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
2050 return LegalizeKind(TypeWidenVector, NVT);
2053 // Examine the element type.
2054 LegalizeKind LK = getTypeConversion(Context, EltVT);
2056 // If type is to be expanded, split the vector.
2057 // <4 x i140> -> <2 x i140>
2058 if (LK.first == TypeExpandInteger)
2059 return LegalizeKind(TypeSplitVector,
2060 EVT::getVectorVT(Context, EltVT, NumElts / 2));
2062 // Promote the integer element types until a legal vector type is found
2063 // or until the element integer type is too big. If a legal type was not
2064 // found, fallback to the usual mechanism of widening/splitting the
2067 // Increase the bitwidth of the element to the next pow-of-two
2068 // (which is greater than 8 bits).
2069 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
2070 ).getRoundIntegerType(Context);
2072 // Stop trying when getting a non-simple element type.
2073 // Note that vector elements may be greater than legal vector element
2074 // types. Example: X86 XMM registers hold 64bit element on 32bit systems.
2075 if (!EltVT.isSimple()) break;
2077 // Build a new vector type and check if it is legal.
2078 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
2079 // Found a legal promoted vector type.
2080 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
2081 return LegalizeKind(TypePromoteInteger,
2082 EVT::getVectorVT(Context, EltVT, NumElts));
2086 // Try to widen the vector until a legal type is found.
2087 // If there is no wider legal type, split the vector.
2089 // Round up to the next power of 2.
2090 NumElts = (unsigned)NextPowerOf2(NumElts);
2092 // If there is no simple vector type with this many elements then there
2093 // cannot be a larger legal vector type. Note that this assumes that
2094 // there are no skipped intermediate vector types in the simple types.
2095 if (!EltVT.isSimple()) break;
2096 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
2097 if (LargerVector == MVT()) break;
2099 // If this type is legal then widen the vector.
2100 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
2101 return LegalizeKind(TypeWidenVector, LargerVector);
2104 // Widen odd vectors to next power of two.
2105 if (!VT.isPow2VectorType()) {
2106 EVT NVT = VT.getPow2VectorType(Context);
2107 return LegalizeKind(TypeWidenVector, NVT);
2110 // Vectors with illegal element types are expanded.
2111 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
2112 return LegalizeKind(TypeSplitVector, NVT);
2116 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
2118 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
2119 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
2120 /// which sets a bit in this array.
2122 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2124 /// PromoteToType - For operations that must be promoted to a specific type,
2125 /// this holds the destination type. This map should be sparse, so don't hold
2128 /// Targets add entries to this map with AddPromotedToType(..), clients access
2129 /// this with getTypeToPromoteTo(..).
2130 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2133 /// LibcallRoutineNames - Stores the name each libcall.
2135 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
2137 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
2138 /// of each of the comparison libcall against zero.
2139 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2141 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
2143 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2146 /// When lowering \@llvm.memset this field specifies the maximum number of
2147 /// store operations that may be substituted for the call to memset. Targets
2148 /// must set this value based on the cost threshold for that target. Targets
2149 /// should assume that the memset will be done using as many of the largest
2150 /// store operations first, followed by smaller ones, if necessary, per
2151 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2152 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2153 /// store. This only applies to setting a constant array of a constant size.
2154 /// @brief Specify maximum number of store instructions per memset call.
2155 unsigned maxStoresPerMemset;
2157 /// Maximum number of stores operations that may be substituted for the call
2158 /// to memset, used for functions with OptSize attribute.
2159 unsigned maxStoresPerMemsetOptSize;
2161 /// When lowering \@llvm.memcpy this field specifies the maximum number of
2162 /// store operations that may be substituted for a call to memcpy. Targets
2163 /// must set this value based on the cost threshold for that target. Targets
2164 /// should assume that the memcpy will be done using as many of the largest
2165 /// store operations first, followed by smaller ones, if necessary, per
2166 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2167 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2168 /// and one 1-byte store. This only applies to copying a constant array of
2170 /// @brief Specify maximum bytes of store instructions per memcpy call.
2171 unsigned maxStoresPerMemcpy;
2173 /// Maximum number of store operations that may be substituted for a call
2174 /// to memcpy, used for functions with OptSize attribute.
2175 unsigned maxStoresPerMemcpyOptSize;
2177 /// When lowering \@llvm.memmove this field specifies the maximum number of
2178 /// store instructions that may be substituted for a call to memmove. Targets
2179 /// must set this value based on the cost threshold for that target. Targets
2180 /// should assume that the memmove will be done using as many of the largest
2181 /// store operations first, followed by smaller ones, if necessary, per
2182 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2183 /// with 8-bit alignment would result in nine 1-byte stores. This only
2184 /// applies to copying a constant array of constant size.
2185 /// @brief Specify maximum bytes of store instructions per memmove call.
2186 unsigned maxStoresPerMemmove;
2188 /// Maximum number of store instructions that may be substituted for a call
2189 /// to memmove, used for functions with OpSize attribute.
2190 unsigned maxStoresPerMemmoveOptSize;
2192 /// This field specifies whether the target can benefit from code placement
2194 bool benefitFromCodePlacementOpt;
2196 /// predictableSelectIsExpensive - Tells the code generator that select is
2197 /// more expensive than a branch if the branch is usually predicted right.
2198 bool predictableSelectIsExpensive;
2201 /// isLegalRC - Return true if the value types that can be represented by the
2202 /// specified register class are all legal.
2203 bool isLegalRC(const TargetRegisterClass *RC) const;
2206 /// GetReturnInfo - Given an LLVM IR type and return type attributes,
2207 /// compute the return value EVTs and flags, and optionally also
2208 /// the offsets, if the return value is being lowered to memory.
2209 void GetReturnInfo(Type* ReturnType, Attribute attr,
2210 SmallVectorImpl<ISD::OutputArg> &Outs,
2211 const TargetLowering &TLI);
2213 } // end llvm namespace