1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CallingConv.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/CodeGen/SelectionDAGNodes.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/ADT/APFloat.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/STLExtras.h"
34 #include "llvm/Support/DebugLoc.h"
35 #include "llvm/Target/TargetCallingConv.h"
36 #include "llvm/Target/TargetMachine.h"
46 class MachineBasicBlock;
47 class MachineFunction;
48 class MachineFrameInfo;
50 class MachineJumpTableInfo;
58 class TargetRegisterClass;
59 class TargetLoweringObjectFile;
62 // FIXME: should this be here?
71 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
74 //===----------------------------------------------------------------------===//
75 /// TargetLowering - This class defines information used to lower LLVM code to
76 /// legal SelectionDAG operators that the target instruction selector can accept
79 /// This class also defines callbacks that targets must implement to lower
80 /// target-specific constructs to SelectionDAG operators.
82 class TargetLowering {
83 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT
84 void operator=(const TargetLowering&); // DO NOT IMPLEMENT
86 /// LegalizeAction - This enum indicates whether operations are valid for a
87 /// target, and if not, what action should be used to make them valid.
89 Legal, // The target natively supports this operation.
90 Promote, // This operation should be executed in a larger type.
91 Expand, // Try to expand this to other ops, otherwise use a libcall.
92 Custom // Use the LowerOperation hook to implement custom lowering.
95 enum BooleanContent { // How the target represents true/false values.
96 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
97 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
98 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
101 /// NOTE: The constructor takes ownership of TLOF.
102 explicit TargetLowering(const TargetMachine &TM,
103 const TargetLoweringObjectFile *TLOF);
104 virtual ~TargetLowering();
106 const TargetMachine &getTargetMachine() const { return TM; }
107 const TargetData *getTargetData() const { return TD; }
108 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
110 bool isBigEndian() const { return !IsLittleEndian; }
111 bool isLittleEndian() const { return IsLittleEndian; }
112 MVT getPointerTy() const { return PointerTy; }
113 MVT getShiftAmountTy() const { return ShiftAmountTy; }
115 /// isSelectExpensive - Return true if the select operation is expensive for
117 bool isSelectExpensive() const { return SelectIsExpensive; }
119 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
120 /// a sequence of several shifts, adds, and multiplies for this target.
121 bool isIntDivCheap() const { return IntDivIsCheap; }
123 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
125 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
127 /// getSetCCResultType - Return the ValueType of the result of SETCC
128 /// operations. Also used to obtain the target's preferred type for
129 /// the condition operand of SELECT and BRCOND nodes. In the case of
130 /// BRCOND the argument passed is MVT::Other since there are no other
131 /// operands to get a type hint from.
133 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
135 /// getCmpLibcallReturnType - Return the ValueType for comparison
136 /// libcalls. Comparions libcalls include floating point comparion calls,
137 /// and Ordered/Unordered check calls on floating point numbers.
139 MVT::SimpleValueType getCmpLibcallReturnType() const;
141 /// getBooleanContents - For targets without i1 registers, this gives the
142 /// nature of the high-bits of boolean values held in types wider than i1.
143 /// "Boolean values" are special true/false values produced by nodes like
144 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
145 /// Not to be confused with general values promoted from i1.
146 BooleanContent getBooleanContents() const { return BooleanContents;}
148 /// getSchedulingPreference - Return target scheduling preference.
149 Sched::Preference getSchedulingPreference() const {
150 return SchedPreferenceInfo;
153 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to
154 /// different scheduling heuristics for different nodes. This function returns
155 /// the preference (or none) for the given node.
156 virtual Sched::Preference getSchedulingPreference(SDNode *N) const {
160 /// getRegClassFor - Return the register class that should be used for the
161 /// specified value type.
162 virtual TargetRegisterClass *getRegClassFor(EVT VT) const {
163 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
164 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
165 assert(RC && "This value type is not natively supported!");
169 /// isTypeLegal - Return true if the target has native support for the
170 /// specified value type. This means that it has a register that directly
171 /// holds it without promotions or expansions.
172 bool isTypeLegal(EVT VT) const {
173 assert(!VT.isSimple() ||
174 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
175 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
178 /// isTypeSynthesizable - Return true if it's OK for the compiler to create
179 /// new operations of this type. All Legal types are synthesizable except
180 /// MMX vector types on X86. Non-Legal types are not synthesizable.
181 bool isTypeSynthesizable(EVT VT) const {
182 return isTypeLegal(VT) && Synthesizable[VT.getSimpleVT().SimpleTy];
185 class ValueTypeActionImpl {
186 /// ValueTypeActions - For each value type, keep a LegalizeAction enum
187 /// that indicates how instruction selection should deal with the type.
188 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
190 ValueTypeActionImpl() {
191 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0);
193 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
194 if (VT.isExtended()) {
196 return VT.isPow2VectorType() ? Expand : Promote;
199 // First promote to a power-of-two size, then expand if necessary.
200 return VT == VT.getRoundIntegerType(Context) ? Expand : Promote;
201 assert(0 && "Unsupported extended type!");
204 unsigned I = VT.getSimpleVT().SimpleTy;
205 return (LegalizeAction)ValueTypeActions[I];
207 void setTypeAction(EVT VT, LegalizeAction Action) {
208 unsigned I = VT.getSimpleVT().SimpleTy;
209 ValueTypeActions[I] = Action;
213 const ValueTypeActionImpl &getValueTypeActions() const {
214 return ValueTypeActions;
217 /// getTypeAction - Return how we should legalize values of this type, either
218 /// it is already legal (return 'Legal') or we need to promote it to a larger
219 /// type (return 'Promote'), or we need to expand it into multiple registers
220 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
221 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
222 return ValueTypeActions.getTypeAction(Context, VT);
225 /// getTypeToTransformTo - For types supported by the target, this is an
226 /// identity function. For types that must be promoted to larger types, this
227 /// returns the larger type to promote to. For integer types that are larger
228 /// than the largest integer register, this contains one step in the expansion
229 /// to get to the smaller register. For illegal floating point types, this
230 /// returns the integer type to transform to.
231 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
233 assert((unsigned)VT.getSimpleVT().SimpleTy <
234 array_lengthof(TransformToType));
235 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
236 assert(getTypeAction(Context, NVT) != Promote &&
237 "Promote may not follow Expand or Promote");
242 EVT NVT = VT.getPow2VectorType(Context);
244 // Vector length is a power of 2 - split to half the size.
245 unsigned NumElts = VT.getVectorNumElements();
246 EVT EltVT = VT.getVectorElementType();
247 return (NumElts == 1) ?
248 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2);
250 // Promote to a power of two size, avoiding multi-step promotion.
251 return getTypeAction(Context, NVT) == Promote ?
252 getTypeToTransformTo(Context, NVT) : NVT;
253 } else if (VT.isInteger()) {
254 EVT NVT = VT.getRoundIntegerType(Context);
256 // Size is a power of two - expand to half the size.
257 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2);
259 // Promote to a power of two size, avoiding multi-step promotion.
260 return getTypeAction(Context, NVT) == Promote ?
261 getTypeToTransformTo(Context, NVT) : NVT;
263 assert(0 && "Unsupported extended type!");
264 return MVT(MVT::Other); // Not reached
267 /// getTypeToExpandTo - For types supported by the target, this is an
268 /// identity function. For types that must be expanded (i.e. integer types
269 /// that are larger than the largest integer register or illegal floating
270 /// point types), this returns the largest legal type it will be expanded to.
271 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
272 assert(!VT.isVector());
274 switch (getTypeAction(Context, VT)) {
278 VT = getTypeToTransformTo(Context, VT);
281 assert(false && "Type is not legal nor is it to be expanded!");
288 /// getVectorTypeBreakdown - Vector types are broken down into some number of
289 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
290 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
291 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
293 /// This method returns the number of registers needed, and the VT for each
294 /// register. It also returns the VT and quantity of the intermediate values
295 /// before they are promoted/expanded.
297 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
299 unsigned &NumIntermediates,
300 EVT &RegisterVT) const;
302 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
303 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
304 /// this is the case, it returns true and store the intrinsic
305 /// information into the IntrinsicInfo that was passed to the function.
306 struct IntrinsicInfo {
307 unsigned opc; // target opcode
308 EVT memVT; // memory VT
309 const Value* ptrVal; // value representing memory location
310 int offset; // offset off of ptrVal
311 unsigned align; // alignment
312 bool vol; // is volatile?
313 bool readMem; // reads memory?
314 bool writeMem; // writes memory?
317 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
318 const CallInst &I, unsigned Intrinsic) const {
322 /// isFPImmLegal - Returns true if the target can instruction select the
323 /// specified FP immediate natively. If false, the legalizer will materialize
324 /// the FP immediate as a load from a constant pool.
325 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const {
329 /// isShuffleMaskLegal - Targets can use this to indicate that they only
330 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
331 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
332 /// are assumed to be legal.
333 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
338 /// canOpTrap - Returns true if the operation can trap for the value type.
339 /// VT must be a legal type. By default, we optimistically assume most
340 /// operations don't trap except for divide and remainder.
341 virtual bool canOpTrap(unsigned Op, EVT VT) const;
343 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
344 /// used by Targets can use this to indicate if there is a suitable
345 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
347 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
352 /// getOperationAction - Return how this operation should be treated: either
353 /// it is legal, needs to be promoted to a larger size, needs to be
354 /// expanded to some other code sequence, or the target has a custom expander
356 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
357 if (VT.isExtended()) return Expand;
358 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
359 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
360 return (LegalizeAction)OpActions[I][Op];
363 /// isOperationLegalOrCustom - Return true if the specified operation is
364 /// legal on this target or can be made legal with custom lowering. This
365 /// is used to help guide high-level lowering decisions.
366 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
367 return (VT == MVT::Other || isTypeLegal(VT)) &&
368 (getOperationAction(Op, VT) == Legal ||
369 getOperationAction(Op, VT) == Custom);
372 /// isOperationLegal - Return true if the specified operation is legal on this
374 bool isOperationLegal(unsigned Op, EVT VT) const {
375 return (VT == MVT::Other || isTypeLegal(VT)) &&
376 getOperationAction(Op, VT) == Legal;
379 /// getLoadExtAction - Return how this load with extension should be treated:
380 /// either it is legal, needs to be promoted to a larger size, needs to be
381 /// expanded to some other code sequence, or the target has a custom expander
383 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const {
384 assert(ExtType < ISD::LAST_LOADEXT_TYPE &&
385 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
386 "Table isn't big enough!");
387 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType];
390 /// isLoadExtLegal - Return true if the specified load with extension is legal
392 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
393 return VT.isSimple() &&
394 (getLoadExtAction(ExtType, VT) == Legal ||
395 getLoadExtAction(ExtType, VT) == Custom);
398 /// getTruncStoreAction - Return how this store with truncation should be
399 /// treated: either it is legal, needs to be promoted to a larger size, needs
400 /// to be expanded to some other code sequence, or the target has a custom
402 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
403 assert((unsigned)ValVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
404 (unsigned)MemVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
405 "Table isn't big enough!");
406 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy]
407 [MemVT.getSimpleVT().SimpleTy];
410 /// isTruncStoreLegal - Return true if the specified store with truncation is
411 /// legal on this target.
412 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
413 return isTypeLegal(ValVT) && MemVT.isSimple() &&
414 (getTruncStoreAction(ValVT, MemVT) == Legal ||
415 getTruncStoreAction(ValVT, MemVT) == Custom);
418 /// getIndexedLoadAction - Return how the indexed load should be treated:
419 /// either it is legal, needs to be promoted to a larger size, needs to be
420 /// expanded to some other code sequence, or the target has a custom expander
423 getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
424 assert( IdxMode < ISD::LAST_INDEXED_MODE &&
425 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
426 "Table isn't big enough!");
427 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy;
428 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
431 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
433 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
434 return VT.isSimple() &&
435 (getIndexedLoadAction(IdxMode, VT) == Legal ||
436 getIndexedLoadAction(IdxMode, VT) == Custom);
439 /// getIndexedStoreAction - Return how the indexed store should be treated:
440 /// either it is legal, needs to be promoted to a larger size, needs to be
441 /// expanded to some other code sequence, or the target has a custom expander
444 getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
445 assert( IdxMode < ISD::LAST_INDEXED_MODE &&
446 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
447 "Table isn't big enough!");
448 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy;
449 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
452 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
454 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
455 return VT.isSimple() &&
456 (getIndexedStoreAction(IdxMode, VT) == Legal ||
457 getIndexedStoreAction(IdxMode, VT) == Custom);
460 /// getCondCodeAction - Return how the condition code should be treated:
461 /// either it is legal, needs to be expanded to some other code sequence,
462 /// or the target has a custom expander for it.
464 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
465 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
466 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
467 "Table isn't big enough!");
468 LegalizeAction Action = (LegalizeAction)
469 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);
470 assert(Action != Promote && "Can't promote condition code!");
474 /// isCondCodeLegal - Return true if the specified condition code is legal
476 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
477 return getCondCodeAction(CC, VT) == Legal ||
478 getCondCodeAction(CC, VT) == Custom;
482 /// getTypeToPromoteTo - If the action for this operation is to promote, this
483 /// method returns the ValueType to promote to.
484 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const {
485 assert(getOperationAction(Op, VT) == Promote &&
486 "This operation isn't promoted!");
488 // See if this has an explicit type specified.
489 std::map<std::pair<unsigned, MVT::SimpleValueType>,
490 MVT::SimpleValueType>::const_iterator PTTI =
491 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
492 if (PTTI != PromoteToType.end()) return PTTI->second;
494 assert((VT.isInteger() || VT.isFloatingPoint()) &&
495 "Cannot autopromote this type, add it with AddPromotedToType.");
499 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
500 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
501 "Didn't find type to promote to!");
502 } while (!isTypeLegal(NVT) ||
503 getOperationAction(Op, NVT) == Promote);
507 /// getValueType - Return the EVT corresponding to this LLVM type.
508 /// This is fixed by the LLVM operations except for the pointer size. If
509 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
510 /// counterpart (e.g. structs), otherwise it will assert.
511 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
512 EVT VT = EVT::getEVT(Ty, AllowUnknown);
513 return VT == MVT::iPTR ? PointerTy : VT;
516 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
517 /// function arguments in the caller parameter area. This is the actual
518 /// alignment, not its logarithm.
519 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
521 /// getRegisterType - Return the type of registers that this ValueType will
522 /// eventually require.
523 EVT getRegisterType(MVT VT) const {
524 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
525 return RegisterTypeForVT[VT.SimpleTy];
528 /// getRegisterType - Return the type of registers that this ValueType will
529 /// eventually require.
530 EVT getRegisterType(LLVMContext &Context, EVT VT) const {
532 assert((unsigned)VT.getSimpleVT().SimpleTy <
533 array_lengthof(RegisterTypeForVT));
534 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
538 unsigned NumIntermediates;
539 (void)getVectorTypeBreakdown(Context, VT, VT1,
540 NumIntermediates, RegisterVT);
543 if (VT.isInteger()) {
544 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
546 assert(0 && "Unsupported extended type!");
547 return EVT(MVT::Other); // Not reached
550 /// getNumRegisters - Return the number of registers that this ValueType will
551 /// eventually require. This is one for any types promoted to live in larger
552 /// registers, but may be more than one for types (like i64) that are split
553 /// into pieces. For types like i140, which are first promoted then expanded,
554 /// it is the number of registers needed to hold all the bits of the original
555 /// type. For an i140 on a 32 bit machine this means 5 registers.
556 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
558 assert((unsigned)VT.getSimpleVT().SimpleTy <
559 array_lengthof(NumRegistersForVT));
560 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
564 unsigned NumIntermediates;
565 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
567 if (VT.isInteger()) {
568 unsigned BitWidth = VT.getSizeInBits();
569 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
570 return (BitWidth + RegWidth - 1) / RegWidth;
572 assert(0 && "Unsupported extended type!");
573 return 0; // Not reached
576 /// ShouldShrinkFPConstant - If true, then instruction selection should
577 /// seek to shrink the FP constant of the specified type to a smaller type
578 /// in order to save space and / or reduce runtime.
579 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; }
581 /// hasTargetDAGCombine - If true, the target has custom DAG combine
582 /// transformations that it can perform for the specified node.
583 bool hasTargetDAGCombine(ISD::NodeType NT) const {
584 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
585 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
588 /// This function returns the maximum number of store operations permitted
589 /// to replace a call to llvm.memset. The value is set by the target at the
590 /// performance threshold for such a replacement.
591 /// @brief Get maximum # of store operations permitted for llvm.memset
592 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
594 /// This function returns the maximum number of store operations permitted
595 /// to replace a call to llvm.memcpy. The value is set by the target at the
596 /// performance threshold for such a replacement.
597 /// @brief Get maximum # of store operations permitted for llvm.memcpy
598 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
600 /// This function returns the maximum number of store operations permitted
601 /// to replace a call to llvm.memmove. The value is set by the target at the
602 /// performance threshold for such a replacement.
603 /// @brief Get maximum # of store operations permitted for llvm.memmove
604 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
606 /// This function returns true if the target allows unaligned memory accesses.
607 /// of the specified type. This is used, for example, in situations where an
608 /// array copy/move/set is converted to a sequence of store operations. It's
609 /// use helps to ensure that such replacements don't generate code that causes
610 /// an alignment error (trap) on the target machine.
611 /// @brief Determine if the target supports unaligned memory accesses.
612 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
616 /// This function returns true if the target would benefit from code placement
618 /// @brief Determine if the target should perform code placement optimization.
619 bool shouldOptimizeCodePlacement() const {
620 return benefitFromCodePlacementOpt;
623 /// getOptimalMemOpType - Returns the target specific optimal type for load
624 /// and store operations as a result of memset, memcpy, and memmove
625 /// lowering. If DstAlign is zero that means it's safe to destination
626 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
627 /// means there isn't a need to check it against alignment requirement,
628 /// probably because the source does not need to be loaded. If
629 /// 'NonScalarIntSafe' is true, that means it's safe to return a
630 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
631 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
632 /// constant so it does not need to be loaded.
633 /// It returns EVT::Other if the type should be determined using generic
634 /// target-independent logic.
635 virtual EVT getOptimalMemOpType(uint64_t Size,
636 unsigned DstAlign, unsigned SrcAlign,
637 bool NonScalarIntSafe, bool MemcpyStrSrc,
638 MachineFunction &MF) const {
642 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
643 /// to implement llvm.setjmp.
644 bool usesUnderscoreSetJmp() const {
645 return UseUnderscoreSetJmp;
648 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
649 /// to implement llvm.longjmp.
650 bool usesUnderscoreLongJmp() const {
651 return UseUnderscoreLongJmp;
654 /// getStackPointerRegisterToSaveRestore - If a physical register, this
655 /// specifies the register that llvm.savestack/llvm.restorestack should save
657 unsigned getStackPointerRegisterToSaveRestore() const {
658 return StackPointerRegisterToSaveRestore;
661 /// getExceptionAddressRegister - If a physical register, this returns
662 /// the register that receives the exception address on entry to a landing
664 unsigned getExceptionAddressRegister() const {
665 return ExceptionPointerRegister;
668 /// getExceptionSelectorRegister - If a physical register, this returns
669 /// the register that receives the exception typeid on entry to a landing
671 unsigned getExceptionSelectorRegister() const {
672 return ExceptionSelectorRegister;
675 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
676 /// set, the default is 200)
677 unsigned getJumpBufSize() const {
681 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
682 /// (if never set, the default is 0)
683 unsigned getJumpBufAlignment() const {
684 return JumpBufAlignment;
687 /// getPrefLoopAlignment - return the preferred loop alignment.
689 unsigned getPrefLoopAlignment() const {
690 return PrefLoopAlignment;
693 /// getShouldFoldAtomicFences - return whether the combiner should fold
694 /// fence MEMBARRIER instructions into the atomic intrinsic instructions.
696 bool getShouldFoldAtomicFences() const {
697 return ShouldFoldAtomicFences;
700 /// getPreIndexedAddressParts - returns true by value, base pointer and
701 /// offset pointer and addressing mode by reference if the node's address
702 /// can be legally represented as pre-indexed load / store address.
703 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
705 ISD::MemIndexedMode &AM,
706 SelectionDAG &DAG) const {
710 /// getPostIndexedAddressParts - returns true by value, base pointer and
711 /// offset pointer and addressing mode by reference if this node can be
712 /// combined with a load / store to form a post-indexed load / store.
713 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
714 SDValue &Base, SDValue &Offset,
715 ISD::MemIndexedMode &AM,
716 SelectionDAG &DAG) const {
720 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
721 /// current function. The returned value is a member of the
722 /// MachineJumpTableInfo::JTEntryKind enum.
723 virtual unsigned getJumpTableEncoding() const;
725 virtual const MCExpr *
726 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
727 const MachineBasicBlock *MBB, unsigned uid,
728 MCContext &Ctx) const {
729 assert(0 && "Need to implement this hook if target has custom JTIs");
733 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
735 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
736 SelectionDAG &DAG) const;
738 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
739 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
741 virtual const MCExpr *
742 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
743 unsigned JTI, MCContext &Ctx) const;
745 /// isOffsetFoldingLegal - Return true if folding a constant offset
746 /// with the given GlobalAddress is legal. It is frequently not legal in
747 /// PIC relocation models.
748 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
750 /// getFunctionAlignment - Return the Log2 alignment of this function.
751 virtual unsigned getFunctionAlignment(const Function *) const = 0;
753 /// getStackCookieLocation - Return true if the target stores stack
754 /// protector cookies at a fixed offset in some non-standard address
755 /// space, and populates the address space and offset as
757 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const {
761 //===--------------------------------------------------------------------===//
762 // TargetLowering Optimization Methods
765 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
766 /// SDValues for returning information from TargetLowering to its clients
767 /// that want to combine
768 struct TargetLoweringOpt {
775 explicit TargetLoweringOpt(SelectionDAG &InDAG,
777 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
779 bool LegalTypes() const { return LegalTys; }
780 bool LegalOperations() const { return LegalOps; }
782 bool CombineTo(SDValue O, SDValue N) {
788 /// ShrinkDemandedConstant - Check to see if the specified operand of the
789 /// specified instruction is a constant integer. If so, check to see if
790 /// there are any bits set in the constant that are not demanded. If so,
791 /// shrink the constant and return true.
792 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
794 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
795 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
796 /// cast, but it could be generalized for targets with other types of
797 /// implicit widening casts.
798 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
802 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
803 /// DemandedMask bits of the result of Op are ever used downstream. If we can
804 /// use this information to simplify Op, create a new simplified DAG node and
805 /// return true, returning the original and new nodes in Old and New.
806 /// Otherwise, analyze the expression and return a mask of KnownOne and
807 /// KnownZero bits for the expression (used to simplify the caller).
808 /// The KnownZero/One bits may only be accurate for those bits in the
810 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
811 APInt &KnownZero, APInt &KnownOne,
812 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
814 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
815 /// Mask are known to be either zero or one and return them in the
816 /// KnownZero/KnownOne bitsets.
817 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
821 const SelectionDAG &DAG,
822 unsigned Depth = 0) const;
824 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
825 /// targets that want to expose additional information about sign bits to the
827 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
828 unsigned Depth = 0) const;
830 struct DAGCombinerInfo {
831 void *DC; // The DAG Combiner object.
833 bool BeforeLegalizeOps;
834 bool CalledByLegalizer;
838 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc)
839 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo),
840 CalledByLegalizer(cl), DAG(dag) {}
842 bool isBeforeLegalize() const { return BeforeLegalize; }
843 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; }
844 bool isCalledByLegalizer() const { return CalledByLegalizer; }
846 void AddToWorklist(SDNode *N);
847 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
849 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
850 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
852 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
855 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
856 /// and cc. If it is unable to simplify it, return a null SDValue.
857 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
858 ISD::CondCode Cond, bool foldBooleans,
859 DAGCombinerInfo &DCI, DebugLoc dl) const;
861 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
862 /// node is a GlobalAddress + offset.
864 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
866 /// PerformDAGCombine - This method will be invoked for all target nodes and
867 /// for any target-independent nodes that the target has registered with
870 /// The semantics are as follows:
872 /// SDValue.Val == 0 - No change was made
873 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
874 /// otherwise - N should be replaced by the returned Operand.
876 /// In addition, methods provided by DAGCombinerInfo may be used to perform
877 /// more complex transformations.
879 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
881 /// isTypeDesirableForOp - Return true if the target has native support for
882 /// the specified value type and it is 'desirable' to use the type for the
883 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
884 /// instruction encodings are longer and some i16 instructions are slow.
885 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const {
886 // By default, assume all legal types are desirable.
887 return isTypeLegal(VT);
890 /// IsDesirableToPromoteOp - This method query the target whether it is
891 /// beneficial for dag combiner to promote the specified node. If true, it
892 /// should return the desired promotion type by reference.
893 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
897 //===--------------------------------------------------------------------===//
898 // TargetLowering Configuration Methods - These methods should be invoked by
899 // the derived class constructor to configure this object for the target.
903 /// setShiftAmountType - Describe the type that should be used for shift
904 /// amounts. This type defaults to the pointer type.
905 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
907 /// setBooleanContents - Specify how the target extends the result of a
908 /// boolean value from i1 to a wider type. See getBooleanContents.
909 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
911 /// setSchedulingPreference - Specify the target scheduling preference.
912 void setSchedulingPreference(Sched::Preference Pref) {
913 SchedPreferenceInfo = Pref;
916 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
917 /// use _setjmp to implement llvm.setjmp or the non _ version.
918 /// Defaults to false.
919 void setUseUnderscoreSetJmp(bool Val) {
920 UseUnderscoreSetJmp = Val;
923 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
924 /// use _longjmp to implement llvm.longjmp or the non _ version.
925 /// Defaults to false.
926 void setUseUnderscoreLongJmp(bool Val) {
927 UseUnderscoreLongJmp = Val;
930 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
931 /// specifies the register that llvm.savestack/llvm.restorestack should save
933 void setStackPointerRegisterToSaveRestore(unsigned R) {
934 StackPointerRegisterToSaveRestore = R;
937 /// setExceptionPointerRegister - If set to a physical register, this sets
938 /// the register that receives the exception address on entry to a landing
940 void setExceptionPointerRegister(unsigned R) {
941 ExceptionPointerRegister = R;
944 /// setExceptionSelectorRegister - If set to a physical register, this sets
945 /// the register that receives the exception typeid on entry to a landing
947 void setExceptionSelectorRegister(unsigned R) {
948 ExceptionSelectorRegister = R;
951 /// SelectIsExpensive - Tells the code generator not to expand operations
952 /// into sequences that use the select operations if possible.
953 void setSelectIsExpensive() { SelectIsExpensive = true; }
955 /// setIntDivIsCheap - Tells the code generator that integer divide is
956 /// expensive, and if possible, should be replaced by an alternate sequence
957 /// of instructions not containing an integer divide.
958 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
960 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
961 /// srl/add/sra for a signed divide by power of two, and let the target handle
963 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
965 /// addRegisterClass - Add the specified register class as an available
966 /// regclass for the specified value type. This indicates the selector can
967 /// handle values of that class natively.
968 void addRegisterClass(EVT VT, TargetRegisterClass *RC,
969 bool isSynthesizable = true) {
970 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
971 AvailableRegClasses.push_back(std::make_pair(VT, RC));
972 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
973 Synthesizable[VT.getSimpleVT().SimpleTy] = isSynthesizable;
976 /// computeRegisterProperties - Once all of the register classes are added,
977 /// this allows us to compute derived properties we expose.
978 void computeRegisterProperties();
980 /// setOperationAction - Indicate that the specified operation does not work
981 /// with the specified type and indicate what to do about it.
982 void setOperationAction(unsigned Op, MVT VT,
983 LegalizeAction Action) {
984 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
985 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
988 /// setLoadExtAction - Indicate that the specified load with extension does
989 /// not work with the specified type and indicate what to do about it.
990 void setLoadExtAction(unsigned ExtType, MVT VT,
991 LegalizeAction Action) {
992 assert(ExtType < ISD::LAST_LOADEXT_TYPE &&
993 (unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
994 "Table isn't big enough!");
995 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
998 /// setTruncStoreAction - Indicate that the specified truncating store does
999 /// not work with the specified type and indicate what to do about it.
1000 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1001 LegalizeAction Action) {
1002 assert((unsigned)ValVT.SimpleTy < MVT::LAST_VALUETYPE &&
1003 (unsigned)MemVT.SimpleTy < MVT::LAST_VALUETYPE &&
1004 "Table isn't big enough!");
1005 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1008 /// setIndexedLoadAction - Indicate that the specified indexed load does or
1009 /// does not work with the specified type and indicate what to do abort
1010 /// it. NOTE: All indexed mode loads are initialized to Expand in
1011 /// TargetLowering.cpp
1012 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1013 LegalizeAction Action) {
1014 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1015 IdxMode < ISD::LAST_INDEXED_MODE &&
1016 (unsigned)Action < 0xf &&
1017 "Table isn't big enough!");
1018 // Load action are kept in the upper half.
1019 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1020 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1023 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1024 /// does not work with the specified type and indicate what to do about
1025 /// it. NOTE: All indexed mode stores are initialized to Expand in
1026 /// TargetLowering.cpp
1027 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1028 LegalizeAction Action) {
1029 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1030 IdxMode < ISD::LAST_INDEXED_MODE &&
1031 (unsigned)Action < 0xf &&
1032 "Table isn't big enough!");
1033 // Store action are kept in the lower half.
1034 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1035 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1038 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1039 /// supported on the target and indicate what to do about it.
1040 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1041 LegalizeAction Action) {
1042 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1043 (unsigned)CC < array_lengthof(CondCodeActions) &&
1044 "Table isn't big enough!");
1045 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1046 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2;
1049 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1050 /// promotion code defaults to trying a larger integer/fp until it can find
1051 /// one that works. If that default is insufficient, this method can be used
1052 /// by the target to override the default.
1053 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1054 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1057 /// setTargetDAGCombine - Targets should invoke this method for each target
1058 /// independent node that they want to provide a custom DAG combiner for by
1059 /// implementing the PerformDAGCombine virtual method.
1060 void setTargetDAGCombine(ISD::NodeType NT) {
1061 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1062 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1065 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1066 /// bytes); default is 200
1067 void setJumpBufSize(unsigned Size) {
1071 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1072 /// alignment (in bytes); default is 0
1073 void setJumpBufAlignment(unsigned Align) {
1074 JumpBufAlignment = Align;
1077 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1078 /// alignment is zero, it means the target does not care about loop alignment.
1079 void setPrefLoopAlignment(unsigned Align) {
1080 PrefLoopAlignment = Align;
1083 /// setShouldFoldAtomicFences - Set if the target's implementation of the
1084 /// atomic operation intrinsics includes locking. Default is false.
1085 void setShouldFoldAtomicFences(bool fold) {
1086 ShouldFoldAtomicFences = fold;
1090 //===--------------------------------------------------------------------===//
1091 // Lowering methods - These methods must be implemented by targets so that
1092 // the SelectionDAGLowering code knows how to lower these.
1095 /// LowerFormalArguments - This hook must be implemented to lower the
1096 /// incoming (formal) arguments, described by the Ins array, into the
1097 /// specified DAG. The implementation should fill in the InVals array
1098 /// with legal-type argument values, and return the resulting token
1102 LowerFormalArguments(SDValue Chain,
1103 CallingConv::ID CallConv, bool isVarArg,
1104 const SmallVectorImpl<ISD::InputArg> &Ins,
1105 DebugLoc dl, SelectionDAG &DAG,
1106 SmallVectorImpl<SDValue> &InVals) const {
1107 assert(0 && "Not Implemented");
1108 return SDValue(); // this is here to silence compiler errors
1111 /// LowerCallTo - This function lowers an abstract call to a function into an
1112 /// actual call. This returns a pair of operands. The first element is the
1113 /// return value for the function (if RetTy is not VoidTy). The second
1114 /// element is the outgoing token chain. It calls LowerCall to do the actual
1116 struct ArgListEntry {
1127 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1128 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1130 typedef std::vector<ArgListEntry> ArgListTy;
1131 std::pair<SDValue, SDValue>
1132 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1133 bool isVarArg, bool isInreg, unsigned NumFixedArgs,
1134 CallingConv::ID CallConv, bool isTailCall,
1135 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
1136 SelectionDAG &DAG, DebugLoc dl) const;
1138 /// LowerCall - This hook must be implemented to lower calls into the
1139 /// the specified DAG. The outgoing arguments to the call are described
1140 /// by the Outs array, and the values to be returned by the call are
1141 /// described by the Ins array. The implementation should fill in the
1142 /// InVals array with legal-type return values from the call, and return
1143 /// the resulting token chain value.
1145 LowerCall(SDValue Chain, SDValue Callee,
1146 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
1147 const SmallVectorImpl<ISD::OutputArg> &Outs,
1148 const SmallVectorImpl<ISD::InputArg> &Ins,
1149 DebugLoc dl, SelectionDAG &DAG,
1150 SmallVectorImpl<SDValue> &InVals) const {
1151 assert(0 && "Not Implemented");
1152 return SDValue(); // this is here to silence compiler errors
1155 /// CanLowerReturn - This hook should be implemented to check whether the
1156 /// return values described by the Outs array can fit into the return
1157 /// registers. If false is returned, an sret-demotion is performed.
1159 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1160 const SmallVectorImpl<EVT> &OutTys,
1161 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1162 LLVMContext &Context) const
1164 // Return true by default to get preexisting behavior.
1168 /// LowerReturn - This hook must be implemented to lower outgoing
1169 /// return values, described by the Outs array, into the specified
1170 /// DAG. The implementation should return the resulting token chain
1174 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1175 const SmallVectorImpl<ISD::OutputArg> &Outs,
1176 DebugLoc dl, SelectionDAG &DAG) const {
1177 assert(0 && "Not Implemented");
1178 return SDValue(); // this is here to silence compiler errors
1181 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1182 /// to legalize nodes with an illegal operand type but legal result types.
1183 /// It replaces the LowerOperation callback in the type Legalizer.
1184 /// The reason we can not do away with LowerOperation entirely is that
1185 /// LegalizeDAG isn't yet ready to use this callback.
1186 /// TODO: Consider merging with ReplaceNodeResults.
1188 /// The target places new result values for the node in Results (their number
1189 /// and types must exactly match those of the original return values of
1190 /// the node), or leaves Results empty, which indicates that the node is not
1191 /// to be custom lowered after all.
1192 /// The default implementation calls LowerOperation.
1193 virtual void LowerOperationWrapper(SDNode *N,
1194 SmallVectorImpl<SDValue> &Results,
1195 SelectionDAG &DAG) const;
1197 /// LowerOperation - This callback is invoked for operations that are
1198 /// unsupported by the target, which are registered to use 'custom' lowering,
1199 /// and whose defined values are all legal.
1200 /// If the target has no operations that require custom lowering, it need not
1201 /// implement this. The default implementation of this aborts.
1202 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
1204 /// ReplaceNodeResults - This callback is invoked when a node result type is
1205 /// illegal for the target, and the operation was registered to use 'custom'
1206 /// lowering for that result type. The target places new result values for
1207 /// the node in Results (their number and types must exactly match those of
1208 /// the original return values of the node), or leaves Results empty, which
1209 /// indicates that the node is not to be custom lowered after all.
1211 /// If the target has no operations that require custom lowering, it need not
1212 /// implement this. The default implementation aborts.
1213 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1214 SelectionDAG &DAG) const {
1215 assert(0 && "ReplaceNodeResults not implemented for this target!");
1218 /// getTargetNodeName() - This method returns the name of a target specific
1220 virtual const char *getTargetNodeName(unsigned Opcode) const;
1222 /// createFastISel - This method returns a target specific FastISel object,
1223 /// or null if the target does not support "fast" ISel.
1225 createFastISel(MachineFunction &,
1226 DenseMap<const Value *, unsigned> &,
1227 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
1228 DenseMap<const AllocaInst *, int> &,
1229 std::vector<std::pair<MachineInstr*, unsigned> > &
1231 , SmallSet<const Instruction *, 8> &CatchInfoLost
1237 //===--------------------------------------------------------------------===//
1238 // Inline Asm Support hooks
1241 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
1242 /// call to be explicit llvm code if it wants to. This is useful for
1243 /// turning simple inline asms into LLVM intrinsics, which gives the
1244 /// compiler more information about the behavior of the code.
1245 virtual bool ExpandInlineAsm(CallInst *CI) const {
1249 enum ConstraintType {
1250 C_Register, // Constraint represents specific register(s).
1251 C_RegisterClass, // Constraint represents any of register(s) in class.
1252 C_Memory, // Memory constraint.
1253 C_Other, // Something else.
1254 C_Unknown // Unsupported constraint.
1257 /// AsmOperandInfo - This contains information for each constraint that we are
1259 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1260 /// ConstraintCode - This contains the actual string for the code, like "m".
1261 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1262 /// most closely matches the operand.
1263 std::string ConstraintCode;
1265 /// ConstraintType - Information about the constraint code, e.g. Register,
1266 /// RegisterClass, Memory, Other, Unknown.
1267 TargetLowering::ConstraintType ConstraintType;
1269 /// CallOperandval - If this is the result output operand or a
1270 /// clobber, this is null, otherwise it is the incoming operand to the
1271 /// CallInst. This gets modified as the asm is processed.
1272 Value *CallOperandVal;
1274 /// ConstraintVT - The ValueType for the operand value.
1277 /// isMatchingInputConstraint - Return true of this is an input operand that
1278 /// is a matching constraint like "4".
1279 bool isMatchingInputConstraint() const;
1281 /// getMatchedOperand - If this is an input matching constraint, this method
1282 /// returns the output operand it matches.
1283 unsigned getMatchedOperand() const;
1285 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1286 : InlineAsm::ConstraintInfo(info),
1287 ConstraintType(TargetLowering::C_Unknown),
1288 CallOperandVal(0), ConstraintVT(MVT::Other) {
1292 /// ComputeConstraintToUse - Determines the constraint code and constraint
1293 /// type to use for the specific AsmOperandInfo, setting
1294 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1295 /// being passed in is available, it can be passed in as Op, otherwise an
1296 /// empty SDValue can be passed.
1297 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1299 SelectionDAG *DAG = 0) const;
1301 /// getConstraintType - Given a constraint, return the type of constraint it
1302 /// is for this target.
1303 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1305 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1306 /// return a list of registers that can be used to satisfy the constraint.
1307 /// This should only be used for C_RegisterClass constraints.
1308 virtual std::vector<unsigned>
1309 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1312 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1313 /// {edx}), return the register number and the register class for the
1316 /// Given a register class constraint, like 'r', if this corresponds directly
1317 /// to an LLVM register class, return a register of 0 and the register class
1320 /// This should only be used for C_Register constraints. On error,
1321 /// this returns a register number of 0 and a null register class pointer..
1322 virtual std::pair<unsigned, const TargetRegisterClass*>
1323 getRegForInlineAsmConstraint(const std::string &Constraint,
1326 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1327 /// with another that has more specific requirements based on the type of the
1328 /// corresponding operand. This returns null if there is no replacement to
1330 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
1332 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1333 /// vector. If it is invalid, don't add anything to Ops.
1334 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1335 std::vector<SDValue> &Ops,
1336 SelectionDAG &DAG) const;
1338 //===--------------------------------------------------------------------===//
1339 // Instruction Emitting Hooks
1342 // EmitInstrWithCustomInserter - This method should be implemented by targets
1343 // that mark instructions with the 'usesCustomInserter' flag. These
1344 // instructions are special in various ways, which require special support to
1345 // insert. The specified MachineInstr is created but not inserted into any
1346 // basic blocks, and this method is called to expand it into a sequence of
1347 // instructions, potentially also creating new basic blocks and control flow.
1348 virtual MachineBasicBlock *
1349 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
1351 //===--------------------------------------------------------------------===//
1352 // Addressing mode description hooks (used by LSR etc).
1355 /// AddrMode - This represents an addressing mode of:
1356 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1357 /// If BaseGV is null, there is no BaseGV.
1358 /// If BaseOffs is zero, there is no base offset.
1359 /// If HasBaseReg is false, there is no base register.
1360 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1364 GlobalValue *BaseGV;
1368 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1371 /// isLegalAddressingMode - Return true if the addressing mode represented by
1372 /// AM is legal for this target, for a load/store of the specified type.
1373 /// The type may be VoidTy, in which case only return true if the addressing
1374 /// mode is legal for a load/store of any legal type.
1375 /// TODO: Handle pre/postinc as well.
1376 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1378 /// isTruncateFree - Return true if it's free to truncate a value of
1379 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1380 /// register EAX to i16 by referencing its sub-register AX.
1381 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1385 virtual bool isTruncateFree(EVT VT1, EVT VT2) const {
1389 /// isZExtFree - Return true if any actual instruction that defines a
1390 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1391 /// register. This does not necessarily include registers defined in
1392 /// unknown ways, such as incoming arguments, or copies from unknown
1393 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1394 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1395 /// all instructions that define 32-bit values implicit zero-extend the
1396 /// result out to 64 bits.
1397 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
1401 virtual bool isZExtFree(EVT VT1, EVT VT2) const {
1405 /// isNarrowingProfitable - Return true if it's profitable to narrow
1406 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1407 /// from i32 to i8 but not from i32 to i16.
1408 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const {
1412 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1413 /// icmp immediate, that is the target has icmp instructions which can compare
1414 /// a register against the immediate without having to materialize the
1415 /// immediate into a register.
1416 virtual bool isLegalICmpImmediate(int64_t Imm) const {
1420 //===--------------------------------------------------------------------===//
1421 // Div utility functions
1423 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1424 std::vector<SDNode*>* Created) const;
1425 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1426 std::vector<SDNode*>* Created) const;
1429 //===--------------------------------------------------------------------===//
1430 // Runtime Library hooks
1433 /// setLibcallName - Rename the default libcall routine name for the specified
1435 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1436 LibcallRoutineNames[Call] = Name;
1439 /// getLibcallName - Get the libcall routine name for the specified libcall.
1441 const char *getLibcallName(RTLIB::Libcall Call) const {
1442 return LibcallRoutineNames[Call];
1445 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1446 /// result of the comparison libcall against zero.
1447 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1448 CmpLibcallCCs[Call] = CC;
1451 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1452 /// the comparison libcall against zero.
1453 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1454 return CmpLibcallCCs[Call];
1457 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1458 /// specified libcall.
1459 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1460 LibcallCallingConvs[Call] = CC;
1463 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1464 /// specified libcall.
1465 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1466 return LibcallCallingConvs[Call];
1470 const TargetMachine &TM;
1471 const TargetData *TD;
1472 const TargetLoweringObjectFile &TLOF;
1474 /// PointerTy - The type to use for pointers, usually i32 or i64.
1478 /// IsLittleEndian - True if this is a little endian target.
1480 bool IsLittleEndian;
1482 /// SelectIsExpensive - Tells the code generator not to expand operations
1483 /// into sequences that use the select operations if possible.
1484 bool SelectIsExpensive;
1486 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1487 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1488 /// a real cost model is in place. If we ever optimize for size, this will be
1489 /// set to true unconditionally.
1492 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1493 /// srl/add/sra for a signed divide by power of two, and let the target handle
1495 bool Pow2DivIsCheap;
1497 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1498 /// llvm.setjmp. Defaults to false.
1499 bool UseUnderscoreSetJmp;
1501 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1502 /// llvm.longjmp. Defaults to false.
1503 bool UseUnderscoreLongJmp;
1505 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1509 /// BooleanContents - Information about the contents of the high-bits in
1510 /// boolean values held in a type wider than i1. See getBooleanContents.
1511 BooleanContent BooleanContents;
1513 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1514 /// total cycles or lowest register usage.
1515 Sched::Preference SchedPreferenceInfo;
1517 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1518 unsigned JumpBufSize;
1520 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1522 unsigned JumpBufAlignment;
1524 /// PrefLoopAlignment - The perferred loop alignment.
1526 unsigned PrefLoopAlignment;
1528 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should
1529 /// be folded into the enclosed atomic intrinsic instruction by the
1531 bool ShouldFoldAtomicFences;
1533 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1534 /// specifies the register that llvm.savestack/llvm.restorestack should save
1536 unsigned StackPointerRegisterToSaveRestore;
1538 /// ExceptionPointerRegister - If set to a physical register, this specifies
1539 /// the register that receives the exception address on entry to a landing
1541 unsigned ExceptionPointerRegister;
1543 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1544 /// the register that receives the exception typeid on entry to a landing
1546 unsigned ExceptionSelectorRegister;
1548 /// RegClassForVT - This indicates the default register class to use for
1549 /// each ValueType the target supports natively.
1550 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1551 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1552 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1554 /// Synthesizable indicates whether it is OK for the compiler to create new
1555 /// operations using this type. All Legal types are Synthesizable except
1556 /// MMX types on X86. Non-Legal types are not Synthesizable.
1557 bool Synthesizable[MVT::LAST_VALUETYPE];
1559 /// TransformToType - For any value types we are promoting or expanding, this
1560 /// contains the value type that we are changing to. For Expanded types, this
1561 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1562 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1563 /// by the system, this holds the same type (e.g. i32 -> i32).
1564 EVT TransformToType[MVT::LAST_VALUETYPE];
1566 /// OpActions - For each operation and each value type, keep a LegalizeAction
1567 /// that indicates how instruction selection should deal with the operation.
1568 /// Most operations are Legal (aka, supported natively by the target), but
1569 /// operations that are not should be described. Note that operations on
1570 /// non-legal value types are not described here.
1571 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1573 /// LoadExtActions - For each load extension type and each value type,
1574 /// keep a LegalizeAction that indicates how instruction selection should deal
1575 /// with a load of a specific value type and extension type.
1576 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1578 /// TruncStoreActions - For each value type pair keep a LegalizeAction that
1579 /// indicates whether a truncating store of a specific value type and
1580 /// truncating type is legal.
1581 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1583 /// IndexedModeActions - For each indexed mode and each value type,
1584 /// keep a pair of LegalizeAction that indicates how instruction
1585 /// selection should deal with the load / store. The first dimension is the
1586 /// value_type for the reference. The second dimension represents the various
1587 /// modes for load store.
1588 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1590 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1591 /// LegalizeAction that indicates how instruction selection should
1592 /// deal with the condition code.
1593 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1595 ValueTypeActionImpl ValueTypeActions;
1597 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
1599 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1600 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1601 /// which sets a bit in this array.
1603 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1605 /// PromoteToType - For operations that must be promoted to a specific type,
1606 /// this holds the destination type. This map should be sparse, so don't hold
1609 /// Targets add entries to this map with AddPromotedToType(..), clients access
1610 /// this with getTypeToPromoteTo(..).
1611 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1614 /// LibcallRoutineNames - Stores the name each libcall.
1616 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1618 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1619 /// of each of the comparison libcall against zero.
1620 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1622 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
1624 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1627 /// When lowering \@llvm.memset this field specifies the maximum number of
1628 /// store operations that may be substituted for the call to memset. Targets
1629 /// must set this value based on the cost threshold for that target. Targets
1630 /// should assume that the memset will be done using as many of the largest
1631 /// store operations first, followed by smaller ones, if necessary, per
1632 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1633 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1634 /// store. This only applies to setting a constant array of a constant size.
1635 /// @brief Specify maximum number of store instructions per memset call.
1636 unsigned maxStoresPerMemset;
1638 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1639 /// store operations that may be substituted for a call to memcpy. Targets
1640 /// must set this value based on the cost threshold for that target. Targets
1641 /// should assume that the memcpy will be done using as many of the largest
1642 /// store operations first, followed by smaller ones, if necessary, per
1643 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1644 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1645 /// and one 1-byte store. This only applies to copying a constant array of
1647 /// @brief Specify maximum bytes of store instructions per memcpy call.
1648 unsigned maxStoresPerMemcpy;
1650 /// When lowering \@llvm.memmove this field specifies the maximum number of
1651 /// store instructions that may be substituted for a call to memmove. Targets
1652 /// must set this value based on the cost threshold for that target. Targets
1653 /// should assume that the memmove will be done using as many of the largest
1654 /// store operations first, followed by smaller ones, if necessary, per
1655 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1656 /// with 8-bit alignment would result in nine 1-byte stores. This only
1657 /// applies to copying a constant array of constant size.
1658 /// @brief Specify maximum bytes of store instructions per memmove call.
1659 unsigned maxStoresPerMemmove;
1661 /// This field specifies whether the target can benefit from code placement
1663 bool benefitFromCodePlacementOpt;
1665 } // end llvm namespace