1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/InlineAsm.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/CodeGen/RuntimeLibcalls.h"
28 #include "llvm/ADT/APFloat.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/SmallSet.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/STLExtras.h"
33 #include "llvm/CodeGen/DebugLoc.h"
34 #include "llvm/Target/TargetMachine.h"
44 class MachineBasicBlock;
45 class MachineFunction;
46 class MachineFrameInfo;
48 class MachineModuleInfo;
55 class TargetRegisterClass;
56 class TargetSubtarget;
59 // FIXME: should this be here?
68 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
71 //===----------------------------------------------------------------------===//
72 /// TargetLowering - This class defines information used to lower LLVM code to
73 /// legal SelectionDAG operators that the target instruction selector can accept
76 /// This class also defines callbacks that targets must implement to lower
77 /// target-specific constructs to SelectionDAG operators.
79 class TargetLowering {
81 /// LegalizeAction - This enum indicates whether operations are valid for a
82 /// target, and if not, what action should be used to make them valid.
84 Legal, // The target natively supports this operation.
85 Promote, // This operation should be executed in a larger type.
86 Expand, // Try to expand this to other ops, otherwise use a libcall.
87 Custom // Use the LowerOperation hook to implement custom lowering.
90 enum OutOfRangeShiftAmount {
91 Undefined, // Oversized shift amounts are undefined (default).
92 Mask, // Shift amounts are auto masked (anded) to value size.
93 Extend // Oversized shift pulls in zeros or sign bits.
96 enum BooleanContent { // How the target represents true/false values.
97 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
98 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
99 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
102 enum SchedPreference {
103 SchedulingForLatency, // Scheduling for shortest total latency.
104 SchedulingForRegPressure // Scheduling for lowest register pressure.
107 explicit TargetLowering(TargetMachine &TM);
108 virtual ~TargetLowering();
110 TargetMachine &getTargetMachine() const { return TM; }
111 const TargetData *getTargetData() const { return TD; }
113 bool isBigEndian() const { return !IsLittleEndian; }
114 bool isLittleEndian() const { return IsLittleEndian; }
115 MVT getPointerTy() const { return PointerTy; }
116 MVT getShiftAmountTy() const { return ShiftAmountTy; }
117 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
119 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
121 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
123 /// isSelectExpensive - Return true if the select operation is expensive for
125 bool isSelectExpensive() const { return SelectIsExpensive; }
127 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
128 /// a sequence of several shifts, adds, and multiplies for this target.
129 bool isIntDivCheap() const { return IntDivIsCheap; }
131 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
133 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
135 /// getSetCCResultType - Return the ValueType of the result of SETCC
136 /// operations. Also used to obtain the target's preferred type for
137 /// the condition operand of SELECT and BRCOND nodes. In the case of
138 /// BRCOND the argument passed is MVT::Other since there are no other
139 /// operands to get a type hint from.
140 virtual MVT getSetCCResultType(MVT VT) const;
142 /// getBooleanContents - For targets without i1 registers, this gives the
143 /// nature of the high-bits of boolean values held in types wider than i1.
144 /// "Boolean values" are special true/false values produced by nodes like
145 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
146 /// Not to be confused with general values promoted from i1.
147 BooleanContent getBooleanContents() const { return BooleanContents;}
149 /// getSchedulingPreference - Return target scheduling preference.
150 SchedPreference getSchedulingPreference() const {
151 return SchedPreferenceInfo;
154 /// getRegClassFor - Return the register class that should be used for the
155 /// specified value type. This may only be called on legal types.
156 TargetRegisterClass *getRegClassFor(MVT VT) const {
157 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
158 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()];
159 assert(RC && "This value type is not natively supported!");
163 /// isTypeLegal - Return true if the target has native support for the
164 /// specified value type. This means that it has a register that directly
165 /// holds it without promotions or expansions.
166 bool isTypeLegal(MVT VT) const {
167 assert(!VT.isSimple() ||
168 (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
169 return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0;
172 class ValueTypeActionImpl {
173 /// ValueTypeActions - This is a bitvector that contains two bits for each
174 /// value type, where the two bits correspond to the LegalizeAction enum.
175 /// This can be queried with "getTypeAction(VT)".
176 uint32_t ValueTypeActions[2];
178 ValueTypeActionImpl() {
179 ValueTypeActions[0] = ValueTypeActions[1] = 0;
181 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
182 ValueTypeActions[0] = RHS.ValueTypeActions[0];
183 ValueTypeActions[1] = RHS.ValueTypeActions[1];
186 LegalizeAction getTypeAction(MVT VT) const {
187 if (VT.isExtended()) {
189 return VT.isPow2VectorType() ? Expand : Promote;
192 // First promote to a power-of-two size, then expand if necessary.
193 return VT == VT.getRoundIntegerType() ? Expand : Promote;
194 assert(0 && "Unsupported extended type!");
197 unsigned I = VT.getSimpleVT();
198 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
199 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
201 void setTypeAction(MVT VT, LegalizeAction Action) {
202 unsigned I = VT.getSimpleVT();
203 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
204 ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
208 const ValueTypeActionImpl &getValueTypeActions() const {
209 return ValueTypeActions;
212 /// getTypeAction - Return how we should legalize values of this type, either
213 /// it is already legal (return 'Legal') or we need to promote it to a larger
214 /// type (return 'Promote'), or we need to expand it into multiple registers
215 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
216 LegalizeAction getTypeAction(MVT VT) const {
217 return ValueTypeActions.getTypeAction(VT);
220 /// getTypeToTransformTo - For types supported by the target, this is an
221 /// identity function. For types that must be promoted to larger types, this
222 /// returns the larger type to promote to. For integer types that are larger
223 /// than the largest integer register, this contains one step in the expansion
224 /// to get to the smaller register. For illegal floating point types, this
225 /// returns the integer type to transform to.
226 MVT getTypeToTransformTo(MVT VT) const {
228 assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType));
229 MVT NVT = TransformToType[VT.getSimpleVT()];
230 assert(getTypeAction(NVT) != Promote &&
231 "Promote may not follow Expand or Promote");
236 MVT NVT = VT.getPow2VectorType();
238 // Vector length is a power of 2 - split to half the size.
239 unsigned NumElts = VT.getVectorNumElements();
240 MVT EltVT = VT.getVectorElementType();
241 return (NumElts == 1) ? EltVT : MVT::getVectorVT(EltVT, NumElts / 2);
243 // Promote to a power of two size, avoiding multi-step promotion.
244 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
245 } else if (VT.isInteger()) {
246 MVT NVT = VT.getRoundIntegerType();
248 // Size is a power of two - expand to half the size.
249 return MVT::getIntegerVT(VT.getSizeInBits() / 2);
251 // Promote to a power of two size, avoiding multi-step promotion.
252 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
254 assert(0 && "Unsupported extended type!");
255 return MVT(); // Not reached
258 /// getTypeToExpandTo - For types supported by the target, this is an
259 /// identity function. For types that must be expanded (i.e. integer types
260 /// that are larger than the largest integer register or illegal floating
261 /// point types), this returns the largest legal type it will be expanded to.
262 MVT getTypeToExpandTo(MVT VT) const {
263 assert(!VT.isVector());
265 switch (getTypeAction(VT)) {
269 VT = getTypeToTransformTo(VT);
272 assert(false && "Type is not legal nor is it to be expanded!");
279 /// getVectorTypeBreakdown - Vector types are broken down into some number of
280 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
281 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
282 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
284 /// This method returns the number of registers needed, and the VT for each
285 /// register. It also returns the VT and quantity of the intermediate values
286 /// before they are promoted/expanded.
288 unsigned getVectorTypeBreakdown(MVT VT,
290 unsigned &NumIntermediates,
291 MVT &RegisterVT) const;
293 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
294 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
295 /// this is the case, it returns true and store the intrinsic
296 /// information into the IntrinsicInfo that was passed to the function.
297 typedef struct IntrinsicInfo {
298 unsigned opc; // target opcode
299 MVT memVT; // memory VT
300 const Value* ptrVal; // value representing memory location
301 int offset; // offset off of ptrVal
302 unsigned align; // alignment
303 bool vol; // is volatile?
304 bool readMem; // reads memory?
305 bool writeMem; // writes memory?
308 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info,
309 CallInst &I, unsigned Intrinsic) {
313 /// getWidenVectorType: given a vector type, returns the type to widen to
314 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
315 /// If there is no vector type that we want to widen to, returns MVT::Other
316 /// When and were to widen is target dependent based on the cost of
317 /// scalarizing vs using the wider vector type.
318 virtual MVT getWidenVectorType(MVT VT) const;
320 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator;
321 legal_fpimm_iterator legal_fpimm_begin() const {
322 return LegalFPImmediates.begin();
324 legal_fpimm_iterator legal_fpimm_end() const {
325 return LegalFPImmediates.end();
328 /// isShuffleMaskLegal - Targets can use this to indicate that they only
329 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
330 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
331 /// are assumed to be legal.
332 virtual bool isShuffleMaskLegal(SmallVectorImpl<int> &Mask, MVT VT) const {
336 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
337 /// used by Targets can use this to indicate if there is a suitable
338 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
340 virtual bool isVectorClearMaskLegal(SmallVectorImpl<int> &M, MVT VT) const {
344 /// getOperationAction - Return how this operation should be treated: either
345 /// it is legal, needs to be promoted to a larger size, needs to be
346 /// expanded to some other code sequence, or the target has a custom expander
348 LegalizeAction getOperationAction(unsigned Op, MVT VT) const {
349 if (VT.isExtended()) return Expand;
350 assert(Op < array_lengthof(OpActions) &&
351 (unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
352 "Table isn't big enough!");
353 return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3);
356 /// isOperationLegalOrCustom - Return true if the specified operation is
357 /// legal on this target or can be made legal with custom lowering. This
358 /// is used to help guide high-level lowering decisions.
359 bool isOperationLegalOrCustom(unsigned Op, MVT VT) const {
360 return (VT == MVT::Other || isTypeLegal(VT)) &&
361 (getOperationAction(Op, VT) == Legal ||
362 getOperationAction(Op, VT) == Custom);
365 /// isOperationLegal - Return true if the specified operation is legal on this
367 bool isOperationLegal(unsigned Op, MVT VT) const {
368 return (VT == MVT::Other || isTypeLegal(VT)) &&
369 getOperationAction(Op, VT) == Legal;
372 /// getLoadExtAction - Return how this load with extension should be treated:
373 /// either it is legal, needs to be promoted to a larger size, needs to be
374 /// expanded to some other code sequence, or the target has a custom expander
376 LegalizeAction getLoadExtAction(unsigned LType, MVT VT) const {
377 assert(LType < array_lengthof(LoadExtActions) &&
378 (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
379 "Table isn't big enough!");
380 return (LegalizeAction)((LoadExtActions[LType] >> (2*VT.getSimpleVT())) & 3);
383 /// isLoadExtLegal - Return true if the specified load with extension is legal
385 bool isLoadExtLegal(unsigned LType, MVT VT) const {
386 return VT.isSimple() &&
387 (getLoadExtAction(LType, VT) == Legal ||
388 getLoadExtAction(LType, VT) == Custom);
391 /// getTruncStoreAction - Return how this store with truncation should be
392 /// treated: either it is legal, needs to be promoted to a larger size, needs
393 /// to be expanded to some other code sequence, or the target has a custom
395 LegalizeAction getTruncStoreAction(MVT ValVT,
397 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
398 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
399 "Table isn't big enough!");
400 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >>
401 (2*MemVT.getSimpleVT())) & 3);
404 /// isTruncStoreLegal - Return true if the specified store with truncation is
405 /// legal on this target.
406 bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const {
407 return isTypeLegal(ValVT) && MemVT.isSimple() &&
408 (getTruncStoreAction(ValVT, MemVT) == Legal ||
409 getTruncStoreAction(ValVT, MemVT) == Custom);
412 /// getIndexedLoadAction - Return how the indexed load should be treated:
413 /// either it is legal, needs to be promoted to a larger size, needs to be
414 /// expanded to some other code sequence, or the target has a custom expander
417 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
418 assert(IdxMode < array_lengthof(IndexedModeActions[0]) &&
419 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0][0])*4 &&
420 "Table isn't big enough!");
421 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >>
422 (2*VT.getSimpleVT())) & 3);
425 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
427 bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const {
428 return VT.isSimple() &&
429 (getIndexedLoadAction(IdxMode, VT) == Legal ||
430 getIndexedLoadAction(IdxMode, VT) == Custom);
433 /// getIndexedStoreAction - Return how the indexed store should be treated:
434 /// either it is legal, needs to be promoted to a larger size, needs to be
435 /// expanded to some other code sequence, or the target has a custom expander
438 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
439 assert(IdxMode < array_lengthof(IndexedModeActions[1]) &&
440 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
441 "Table isn't big enough!");
442 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >>
443 (2*VT.getSimpleVT())) & 3);
446 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
448 bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const {
449 return VT.isSimple() &&
450 (getIndexedStoreAction(IdxMode, VT) == Legal ||
451 getIndexedStoreAction(IdxMode, VT) == Custom);
454 /// getConvertAction - Return how the conversion should be treated:
455 /// either it is legal, needs to be promoted to a larger size, needs to be
456 /// expanded to some other code sequence, or the target has a custom expander
459 getConvertAction(MVT FromVT, MVT ToVT) const {
460 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
461 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
462 "Table isn't big enough!");
463 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >>
464 (2*ToVT.getSimpleVT())) & 3);
467 /// isConvertLegal - Return true if the specified conversion is legal
469 bool isConvertLegal(MVT FromVT, MVT ToVT) const {
470 return isTypeLegal(FromVT) && isTypeLegal(ToVT) &&
471 (getConvertAction(FromVT, ToVT) == Legal ||
472 getConvertAction(FromVT, ToVT) == Custom);
475 /// getCondCodeAction - Return how the condition code should be treated:
476 /// either it is legal, needs to be expanded to some other code sequence,
477 /// or the target has a custom expander for it.
479 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
480 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
481 (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
482 "Table isn't big enough!");
483 LegalizeAction Action = (LegalizeAction)
484 ((CondCodeActions[CC] >> (2*VT.getSimpleVT())) & 3);
485 assert(Action != Promote && "Can't promote condition code!");
489 /// isCondCodeLegal - Return true if the specified condition code is legal
491 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
492 return getCondCodeAction(CC, VT) == Legal ||
493 getCondCodeAction(CC, VT) == Custom;
497 /// getTypeToPromoteTo - If the action for this operation is to promote, this
498 /// method returns the ValueType to promote to.
499 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
500 assert(getOperationAction(Op, VT) == Promote &&
501 "This operation isn't promoted!");
503 // See if this has an explicit type specified.
504 std::map<std::pair<unsigned, MVT::SimpleValueType>,
505 MVT::SimpleValueType>::const_iterator PTTI =
506 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT()));
507 if (PTTI != PromoteToType.end()) return PTTI->second;
509 assert((VT.isInteger() || VT.isFloatingPoint()) &&
510 "Cannot autopromote this type, add it with AddPromotedToType.");
514 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1);
515 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
516 "Didn't find type to promote to!");
517 } while (!isTypeLegal(NVT) ||
518 getOperationAction(Op, NVT) == Promote);
522 /// getValueType - Return the MVT corresponding to this LLVM type.
523 /// This is fixed by the LLVM operations except for the pointer size. If
524 /// AllowUnknown is true, this will return MVT::Other for types with no MVT
525 /// counterpart (e.g. structs), otherwise it will assert.
526 MVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
527 MVT VT = MVT::getMVT(Ty, AllowUnknown);
528 return VT == MVT::iPTR ? PointerTy : VT;
531 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
532 /// function arguments in the caller parameter area. This is the actual
533 /// alignment, not its logarithm.
534 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
536 /// getRegisterType - Return the type of registers that this ValueType will
537 /// eventually require.
538 MVT getRegisterType(MVT VT) const {
540 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT));
541 return RegisterTypeForVT[VT.getSimpleVT()];
545 unsigned NumIntermediates;
546 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
549 if (VT.isInteger()) {
550 return getRegisterType(getTypeToTransformTo(VT));
552 assert(0 && "Unsupported extended type!");
553 return MVT(); // Not reached
556 /// getNumRegisters - Return the number of registers that this ValueType will
557 /// eventually require. This is one for any types promoted to live in larger
558 /// registers, but may be more than one for types (like i64) that are split
559 /// into pieces. For types like i140, which are first promoted then expanded,
560 /// it is the number of registers needed to hold all the bits of the original
561 /// type. For an i140 on a 32 bit machine this means 5 registers.
562 unsigned getNumRegisters(MVT VT) const {
564 assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT));
565 return NumRegistersForVT[VT.getSimpleVT()];
569 unsigned NumIntermediates;
570 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
572 if (VT.isInteger()) {
573 unsigned BitWidth = VT.getSizeInBits();
574 unsigned RegWidth = getRegisterType(VT).getSizeInBits();
575 return (BitWidth + RegWidth - 1) / RegWidth;
577 assert(0 && "Unsupported extended type!");
578 return 0; // Not reached
581 /// ShouldShrinkFPConstant - If true, then instruction selection should
582 /// seek to shrink the FP constant of the specified type to a smaller type
583 /// in order to save space and / or reduce runtime.
584 virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; }
586 /// hasTargetDAGCombine - If true, the target has custom DAG combine
587 /// transformations that it can perform for the specified node.
588 bool hasTargetDAGCombine(ISD::NodeType NT) const {
589 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
590 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
593 /// This function returns the maximum number of store operations permitted
594 /// to replace a call to llvm.memset. The value is set by the target at the
595 /// performance threshold for such a replacement.
596 /// @brief Get maximum # of store operations permitted for llvm.memset
597 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
599 /// This function returns the maximum number of store operations permitted
600 /// to replace a call to llvm.memcpy. The value is set by the target at the
601 /// performance threshold for such a replacement.
602 /// @brief Get maximum # of store operations permitted for llvm.memcpy
603 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
605 /// This function returns the maximum number of store operations permitted
606 /// to replace a call to llvm.memmove. The value is set by the target at the
607 /// performance threshold for such a replacement.
608 /// @brief Get maximum # of store operations permitted for llvm.memmove
609 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
611 /// This function returns true if the target allows unaligned memory accesses.
612 /// This is used, for example, in situations where an array copy/move/set is
613 /// converted to a sequence of store operations. It's use helps to ensure that
614 /// such replacements don't generate code that causes an alignment error
615 /// (trap) on the target machine.
616 /// @brief Determine if the target supports unaligned memory accesses.
617 bool allowsUnalignedMemoryAccesses() const {
618 return allowUnalignedMemoryAccesses;
621 /// getOptimalMemOpType - Returns the target specific optimal type for load
622 /// and store operations as a result of memset, memcpy, and memmove lowering.
623 /// It returns MVT::iAny if SelectionDAG should be responsible for
625 virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
626 bool isSrcConst, bool isSrcStr) const {
630 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
631 /// to implement llvm.setjmp.
632 bool usesUnderscoreSetJmp() const {
633 return UseUnderscoreSetJmp;
636 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
637 /// to implement llvm.longjmp.
638 bool usesUnderscoreLongJmp() const {
639 return UseUnderscoreLongJmp;
642 /// getStackPointerRegisterToSaveRestore - If a physical register, this
643 /// specifies the register that llvm.savestack/llvm.restorestack should save
645 unsigned getStackPointerRegisterToSaveRestore() const {
646 return StackPointerRegisterToSaveRestore;
649 /// getExceptionAddressRegister - If a physical register, this returns
650 /// the register that receives the exception address on entry to a landing
652 unsigned getExceptionAddressRegister() const {
653 return ExceptionPointerRegister;
656 /// getExceptionSelectorRegister - If a physical register, this returns
657 /// the register that receives the exception typeid on entry to a landing
659 unsigned getExceptionSelectorRegister() const {
660 return ExceptionSelectorRegister;
663 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
664 /// set, the default is 200)
665 unsigned getJumpBufSize() const {
669 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
670 /// (if never set, the default is 0)
671 unsigned getJumpBufAlignment() const {
672 return JumpBufAlignment;
675 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
676 /// limit. Any block whose size is greater should not be predicated.
677 unsigned getIfCvtBlockSizeLimit() const {
678 return IfCvtBlockSizeLimit;
681 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
682 /// block to be considered for duplication. Any block whose size is greater
683 /// should not be duplicated to facilitate its predication.
684 unsigned getIfCvtDupBlockSizeLimit() const {
685 return IfCvtDupBlockSizeLimit;
688 /// getPrefLoopAlignment - return the preferred loop alignment.
690 unsigned getPrefLoopAlignment() const {
691 return PrefLoopAlignment;
694 /// getPreIndexedAddressParts - returns true by value, base pointer and
695 /// offset pointer and addressing mode by reference if the node's address
696 /// can be legally represented as pre-indexed load / store address.
697 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
699 ISD::MemIndexedMode &AM,
700 SelectionDAG &DAG) const {
704 /// getPostIndexedAddressParts - returns true by value, base pointer and
705 /// offset pointer and addressing mode by reference if this node can be
706 /// combined with a load / store to form a post-indexed load / store.
707 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
708 SDValue &Base, SDValue &Offset,
709 ISD::MemIndexedMode &AM,
710 SelectionDAG &DAG) const {
714 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
716 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
717 SelectionDAG &DAG) const;
719 /// isOffsetFoldingLegal - Return true if folding a constant offset
720 /// with the given GlobalAddress is legal. It is frequently not legal in
721 /// PIC relocation models.
722 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
724 //===--------------------------------------------------------------------===//
725 // TargetLowering Optimization Methods
728 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
729 /// SDValues for returning information from TargetLowering to its clients
730 /// that want to combine
731 struct TargetLoweringOpt {
736 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
738 bool CombineTo(SDValue O, SDValue N) {
744 /// ShrinkDemandedConstant - Check to see if the specified operand of the
745 /// specified instruction is a constant integer. If so, check to see if
746 /// there are any bits set in the constant that are not demanded. If so,
747 /// shrink the constant and return true.
748 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
750 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
751 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
752 /// cast, but it could be generalized for targets with other types of
753 /// implicit widening casts.
754 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
758 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
759 /// DemandedMask bits of the result of Op are ever used downstream. If we can
760 /// use this information to simplify Op, create a new simplified DAG node and
761 /// return true, returning the original and new nodes in Old and New.
762 /// Otherwise, analyze the expression and return a mask of KnownOne and
763 /// KnownZero bits for the expression (used to simplify the caller).
764 /// The KnownZero/One bits may only be accurate for those bits in the
766 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
767 APInt &KnownZero, APInt &KnownOne,
768 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
770 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
771 /// Mask are known to be either zero or one and return them in the
772 /// KnownZero/KnownOne bitsets.
773 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
777 const SelectionDAG &DAG,
778 unsigned Depth = 0) const;
780 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
781 /// targets that want to expose additional information about sign bits to the
783 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
784 unsigned Depth = 0) const;
786 struct DAGCombinerInfo {
787 void *DC; // The DAG Combiner object.
789 bool CalledByLegalizer;
793 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc)
794 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {}
796 bool isBeforeLegalize() const { return BeforeLegalize; }
797 bool isCalledByLegalizer() const { return CalledByLegalizer; }
799 void AddToWorklist(SDNode *N);
800 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
802 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
803 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
805 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
808 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
809 /// and cc. If it is unable to simplify it, return a null SDValue.
810 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
811 ISD::CondCode Cond, bool foldBooleans,
812 DAGCombinerInfo &DCI, DebugLoc dl) const;
814 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
815 /// node is a GlobalAddress + offset.
817 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
819 /// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is
820 /// loading 'Bytes' bytes from a location that is 'Dist' units away from the
821 /// location that the 'Base' load is loading from.
822 bool isConsecutiveLoad(SDNode *LD, SDNode *Base, unsigned Bytes, int Dist,
823 const MachineFrameInfo *MFI) const;
825 /// PerformDAGCombine - This method will be invoked for all target nodes and
826 /// for any target-independent nodes that the target has registered with
829 /// The semantics are as follows:
831 /// SDValue.Val == 0 - No change was made
832 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
833 /// otherwise - N should be replaced by the returned Operand.
835 /// In addition, methods provided by DAGCombinerInfo may be used to perform
836 /// more complex transformations.
838 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
840 //===--------------------------------------------------------------------===//
841 // TargetLowering Configuration Methods - These methods should be invoked by
842 // the derived class constructor to configure this object for the target.
846 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
847 /// GOT for PC-relative code.
848 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
850 /// setShiftAmountType - Describe the type that should be used for shift
851 /// amounts. This type defaults to the pointer type.
852 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
854 /// setBooleanContents - Specify how the target extends the result of a
855 /// boolean value from i1 to a wider type. See getBooleanContents.
856 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
858 /// setSchedulingPreference - Specify the target scheduling preference.
859 void setSchedulingPreference(SchedPreference Pref) {
860 SchedPreferenceInfo = Pref;
863 /// setShiftAmountFlavor - Describe how the target handles out of range shift
865 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
866 ShiftAmtHandling = OORSA;
869 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
870 /// use _setjmp to implement llvm.setjmp or the non _ version.
871 /// Defaults to false.
872 void setUseUnderscoreSetJmp(bool Val) {
873 UseUnderscoreSetJmp = Val;
876 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
877 /// use _longjmp to implement llvm.longjmp or the non _ version.
878 /// Defaults to false.
879 void setUseUnderscoreLongJmp(bool Val) {
880 UseUnderscoreLongJmp = Val;
883 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
884 /// specifies the register that llvm.savestack/llvm.restorestack should save
886 void setStackPointerRegisterToSaveRestore(unsigned R) {
887 StackPointerRegisterToSaveRestore = R;
890 /// setExceptionPointerRegister - If set to a physical register, this sets
891 /// the register that receives the exception address on entry to a landing
893 void setExceptionPointerRegister(unsigned R) {
894 ExceptionPointerRegister = R;
897 /// setExceptionSelectorRegister - If set to a physical register, this sets
898 /// the register that receives the exception typeid on entry to a landing
900 void setExceptionSelectorRegister(unsigned R) {
901 ExceptionSelectorRegister = R;
904 /// SelectIsExpensive - Tells the code generator not to expand operations
905 /// into sequences that use the select operations if possible.
906 void setSelectIsExpensive() { SelectIsExpensive = true; }
908 /// setIntDivIsCheap - Tells the code generator that integer divide is
909 /// expensive, and if possible, should be replaced by an alternate sequence
910 /// of instructions not containing an integer divide.
911 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
913 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
914 /// srl/add/sra for a signed divide by power of two, and let the target handle
916 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
918 /// addRegisterClass - Add the specified register class as an available
919 /// regclass for the specified value type. This indicates the selector can
920 /// handle values of that class natively.
921 void addRegisterClass(MVT VT, TargetRegisterClass *RC) {
922 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
923 AvailableRegClasses.push_back(std::make_pair(VT, RC));
924 RegClassForVT[VT.getSimpleVT()] = RC;
927 /// computeRegisterProperties - Once all of the register classes are added,
928 /// this allows us to compute derived properties we expose.
929 void computeRegisterProperties();
931 /// setOperationAction - Indicate that the specified operation does not work
932 /// with the specified type and indicate what to do about it.
933 void setOperationAction(unsigned Op, MVT VT,
934 LegalizeAction Action) {
935 assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
936 Op < array_lengthof(OpActions) && "Table isn't big enough!");
937 OpActions[Op] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
938 OpActions[Op] |= (uint64_t)Action << VT.getSimpleVT()*2;
941 /// setLoadExtAction - Indicate that the specified load with extension does
942 /// not work with the with specified type and indicate what to do about it.
943 void setLoadExtAction(unsigned ExtType, MVT VT,
944 LegalizeAction Action) {
945 assert((unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
946 ExtType < array_lengthof(LoadExtActions) &&
947 "Table isn't big enough!");
948 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
949 LoadExtActions[ExtType] |= (uint64_t)Action << VT.getSimpleVT()*2;
952 /// setTruncStoreAction - Indicate that the specified truncating store does
953 /// not work with the with specified type and indicate what to do about it.
954 void setTruncStoreAction(MVT ValVT, MVT MemVT,
955 LegalizeAction Action) {
956 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
957 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
958 "Table isn't big enough!");
959 TruncStoreActions[ValVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
960 MemVT.getSimpleVT()*2);
961 TruncStoreActions[ValVT.getSimpleVT()] |= (uint64_t)Action <<
962 MemVT.getSimpleVT()*2;
965 /// setIndexedLoadAction - Indicate that the specified indexed load does or
966 /// does not work with the with specified type and indicate what to do abort
967 /// it. NOTE: All indexed mode loads are initialized to Expand in
968 /// TargetLowering.cpp
969 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
970 LegalizeAction Action) {
971 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0])*4 &&
972 IdxMode < array_lengthof(IndexedModeActions[0]) &&
973 "Table isn't big enough!");
974 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
975 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
978 /// setIndexedStoreAction - Indicate that the specified indexed store does or
979 /// does not work with the with specified type and indicate what to do about
980 /// it. NOTE: All indexed mode stores are initialized to Expand in
981 /// TargetLowering.cpp
982 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
983 LegalizeAction Action) {
984 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
985 IdxMode < array_lengthof(IndexedModeActions[1]) &&
986 "Table isn't big enough!");
987 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
988 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
991 /// setConvertAction - Indicate that the specified conversion does or does
992 /// not work with the with specified type and indicate what to do about it.
993 void setConvertAction(MVT FromVT, MVT ToVT,
994 LegalizeAction Action) {
995 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
996 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
997 "Table isn't big enough!");
998 ConvertActions[FromVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
999 ToVT.getSimpleVT()*2);
1000 ConvertActions[FromVT.getSimpleVT()] |= (uint64_t)Action <<
1001 ToVT.getSimpleVT()*2;
1004 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1005 /// supported on the target and indicate what to do about it.
1006 void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) {
1007 assert((unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
1008 (unsigned)CC < array_lengthof(CondCodeActions) &&
1009 "Table isn't big enough!");
1010 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
1011 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.getSimpleVT()*2;
1014 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1015 /// promotion code defaults to trying a larger integer/fp until it can find
1016 /// one that works. If that default is insufficient, this method can be used
1017 /// by the target to override the default.
1018 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1019 PromoteToType[std::make_pair(Opc, OrigVT.getSimpleVT())] =
1020 DestVT.getSimpleVT();
1023 /// addLegalFPImmediate - Indicate that this target can instruction select
1024 /// the specified FP immediate natively.
1025 void addLegalFPImmediate(const APFloat& Imm) {
1026 LegalFPImmediates.push_back(Imm);
1029 /// setTargetDAGCombine - Targets should invoke this method for each target
1030 /// independent node that they want to provide a custom DAG combiner for by
1031 /// implementing the PerformDAGCombine virtual method.
1032 void setTargetDAGCombine(ISD::NodeType NT) {
1033 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1034 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1037 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1038 /// bytes); default is 200
1039 void setJumpBufSize(unsigned Size) {
1043 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1044 /// alignment (in bytes); default is 0
1045 void setJumpBufAlignment(unsigned Align) {
1046 JumpBufAlignment = Align;
1049 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
1050 /// limit (in number of instructions); default is 2.
1051 void setIfCvtBlockSizeLimit(unsigned Limit) {
1052 IfCvtBlockSizeLimit = Limit;
1055 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
1056 /// of instructions) to be considered for code duplication during
1057 /// if-conversion; default is 2.
1058 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
1059 IfCvtDupBlockSizeLimit = Limit;
1062 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1063 /// alignment is zero, it means the target does not care about loop alignment.
1064 void setPrefLoopAlignment(unsigned Align) {
1065 PrefLoopAlignment = Align;
1070 virtual const TargetSubtarget *getSubtarget() {
1071 assert(0 && "Not Implemented");
1072 return NULL; // this is here to silence compiler errors
1074 //===--------------------------------------------------------------------===//
1075 // Lowering methods - These methods must be implemented by targets so that
1076 // the SelectionDAGLowering code knows how to lower these.
1079 /// LowerArguments - This hook must be implemented to indicate how we should
1080 /// lower the arguments for the specified function, into the specified DAG.
1082 LowerArguments(Function &F, SelectionDAG &DAG,
1083 SmallVectorImpl<SDValue>& ArgValues, DebugLoc dl);
1085 /// LowerCallTo - This hook lowers an abstract call to a function into an
1086 /// actual call. This returns a pair of operands. The first element is the
1087 /// return value for the function (if RetTy is not VoidTy). The second
1088 /// element is the outgoing token chain.
1089 struct ArgListEntry {
1100 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1101 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1103 typedef std::vector<ArgListEntry> ArgListTy;
1104 virtual std::pair<SDValue, SDValue>
1105 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1106 bool isVarArg, bool isInreg, unsigned CallingConv,
1107 bool isTailCall, SDValue Callee, ArgListTy &Args,
1108 SelectionDAG &DAG, DebugLoc dl);
1110 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
1111 /// memcpy. This can be used by targets to provide code sequences for cases
1112 /// that don't fit the target's parameters for simple loads/stores and can be
1113 /// more efficient than using a library call. This function can return a null
1114 /// SDValue if the target declines to use custom code and a different
1115 /// lowering strategy should be used.
1117 /// If AlwaysInline is true, the size is constant and the target should not
1118 /// emit any calls and is strongly encouraged to attempt to emit inline code
1119 /// even if it is beyond the usual threshold because this intrinsic is being
1120 /// expanded in a place where calls are not feasible (e.g. within the prologue
1121 /// for another call). If the target chooses to decline an AlwaysInline
1122 /// request here, legalize will resort to using simple loads and stores.
1124 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1126 SDValue Op1, SDValue Op2,
1127 SDValue Op3, unsigned Align,
1129 const Value *DstSV, uint64_t DstOff,
1130 const Value *SrcSV, uint64_t SrcOff) {
1134 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a
1135 /// memmove. This can be used by targets to provide code sequences for cases
1136 /// that don't fit the target's parameters for simple loads/stores and can be
1137 /// more efficient than using a library call. This function can return a null
1138 /// SDValue if the target declines to use custom code and a different
1139 /// lowering strategy should be used.
1141 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl,
1143 SDValue Op1, SDValue Op2,
1144 SDValue Op3, unsigned Align,
1145 const Value *DstSV, uint64_t DstOff,
1146 const Value *SrcSV, uint64_t SrcOff) {
1150 /// EmitTargetCodeForMemset - Emit target-specific code that performs a
1151 /// memset. This can be used by targets to provide code sequences for cases
1152 /// that don't fit the target's parameters for simple stores and can be more
1153 /// efficient than using a library call. This function can return a null
1154 /// SDValue if the target declines to use custom code and a different
1155 /// lowering strategy should be used.
1157 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
1159 SDValue Op1, SDValue Op2,
1160 SDValue Op3, unsigned Align,
1161 const Value *DstSV, uint64_t DstOff) {
1165 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1166 /// to legalize nodes with an illegal operand type but legal result types.
1167 /// It replaces the LowerOperation callback in the type Legalizer.
1168 /// The reason we can not do away with LowerOperation entirely is that
1169 /// LegalizeDAG isn't yet ready to use this callback.
1170 /// TODO: Consider merging with ReplaceNodeResults.
1172 /// The target places new result values for the node in Results (their number
1173 /// and types must exactly match those of the original return values of
1174 /// the node), or leaves Results empty, which indicates that the node is not
1175 /// to be custom lowered after all.
1176 /// The default implementation calls LowerOperation.
1177 virtual void LowerOperationWrapper(SDNode *N,
1178 SmallVectorImpl<SDValue> &Results,
1181 /// LowerOperation - This callback is invoked for operations that are
1182 /// unsupported by the target, which are registered to use 'custom' lowering,
1183 /// and whose defined values are all legal.
1184 /// If the target has no operations that require custom lowering, it need not
1185 /// implement this. The default implementation of this aborts.
1186 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
1188 /// ReplaceNodeResults - This callback is invoked when a node result type is
1189 /// illegal for the target, and the operation was registered to use 'custom'
1190 /// lowering for that result type. The target places new result values for
1191 /// the node in Results (their number and types must exactly match those of
1192 /// the original return values of the node), or leaves Results empty, which
1193 /// indicates that the node is not to be custom lowered after all.
1195 /// If the target has no operations that require custom lowering, it need not
1196 /// implement this. The default implementation aborts.
1197 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1198 SelectionDAG &DAG) {
1199 assert(0 && "ReplaceNodeResults not implemented for this target!");
1202 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for
1203 /// tail call optimization. Targets which want to do tail call optimization
1204 /// should override this function.
1205 virtual bool IsEligibleForTailCallOptimization(CallSDNode *Call,
1207 SelectionDAG &DAG) const {
1211 /// CheckTailCallReturnConstraints - Check whether CALL node immediatly
1212 /// preceeds the RET node and whether the return uses the result of the node
1213 /// or is a void return. This function can be used by the target to determine
1214 /// eligiblity of tail call optimization.
1215 static bool CheckTailCallReturnConstraints(CallSDNode *TheCall, SDValue Ret);
1217 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if
1218 /// it exists. Skip a possible ISD::TokenFactor.
1219 static SDValue GetPossiblePreceedingTailCall(SDValue Chain,
1220 unsigned TailCallNodeOpCode) {
1221 if (Chain.getOpcode() == TailCallNodeOpCode) {
1223 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1224 if (Chain.getNumOperands() &&
1225 Chain.getOperand(0).getOpcode() == TailCallNodeOpCode)
1226 return Chain.getOperand(0);
1231 /// getTargetNodeName() - This method returns the name of a target specific
1233 virtual const char *getTargetNodeName(unsigned Opcode) const;
1235 /// createFastISel - This method returns a target specific FastISel object,
1236 /// or null if the target does not support "fast" ISel.
1238 createFastISel(MachineFunction &,
1239 MachineModuleInfo *, DwarfWriter *,
1240 DenseMap<const Value *, unsigned> &,
1241 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
1242 DenseMap<const AllocaInst *, int> &
1244 , SmallSet<Instruction*, 8> &CatchInfoLost
1250 //===--------------------------------------------------------------------===//
1251 // Inline Asm Support hooks
1254 enum ConstraintType {
1255 C_Register, // Constraint represents specific register(s).
1256 C_RegisterClass, // Constraint represents any of register(s) in class.
1257 C_Memory, // Memory constraint.
1258 C_Other, // Something else.
1259 C_Unknown // Unsupported constraint.
1262 /// AsmOperandInfo - This contains information for each constraint that we are
1264 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1265 /// ConstraintCode - This contains the actual string for the code, like "m".
1266 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1267 /// most closely matches the operand.
1268 std::string ConstraintCode;
1270 /// ConstraintType - Information about the constraint code, e.g. Register,
1271 /// RegisterClass, Memory, Other, Unknown.
1272 TargetLowering::ConstraintType ConstraintType;
1274 /// CallOperandval - If this is the result output operand or a
1275 /// clobber, this is null, otherwise it is the incoming operand to the
1276 /// CallInst. This gets modified as the asm is processed.
1277 Value *CallOperandVal;
1279 /// ConstraintVT - The ValueType for the operand value.
1282 /// isMatchingInputConstraint - Return true of this is an input operand that
1283 /// is a matching constraint like "4".
1284 bool isMatchingInputConstraint() const;
1286 /// getMatchedOperand - If this is an input matching constraint, this method
1287 /// returns the output operand it matches.
1288 unsigned getMatchedOperand() const;
1290 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1291 : InlineAsm::ConstraintInfo(info),
1292 ConstraintType(TargetLowering::C_Unknown),
1293 CallOperandVal(0), ConstraintVT(MVT::Other) {
1297 /// ComputeConstraintToUse - Determines the constraint code and constraint
1298 /// type to use for the specific AsmOperandInfo, setting
1299 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1300 /// being passed in is available, it can be passed in as Op, otherwise an
1301 /// empty SDValue can be passed. If hasMemory is true it means one of the asm
1302 /// constraint of the inline asm instruction being processed is 'm'.
1303 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1306 SelectionDAG *DAG = 0) const;
1308 /// getConstraintType - Given a constraint, return the type of constraint it
1309 /// is for this target.
1310 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1312 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1313 /// return a list of registers that can be used to satisfy the constraint.
1314 /// This should only be used for C_RegisterClass constraints.
1315 virtual std::vector<unsigned>
1316 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1319 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1320 /// {edx}), return the register number and the register class for the
1323 /// Given a register class constraint, like 'r', if this corresponds directly
1324 /// to an LLVM register class, return a register of 0 and the register class
1327 /// This should only be used for C_Register constraints. On error,
1328 /// this returns a register number of 0 and a null register class pointer..
1329 virtual std::pair<unsigned, const TargetRegisterClass*>
1330 getRegForInlineAsmConstraint(const std::string &Constraint,
1333 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1334 /// with another that has more specific requirements based on the type of the
1335 /// corresponding operand. This returns null if there is no replacement to
1337 virtual const char *LowerXConstraint(MVT ConstraintVT) const;
1339 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1340 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
1341 /// it means one of the asm constraint of the inline asm instruction being
1342 /// processed is 'm'.
1343 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1345 std::vector<SDValue> &Ops,
1346 SelectionDAG &DAG) const;
1348 //===--------------------------------------------------------------------===//
1352 // EmitInstrWithCustomInserter - This method should be implemented by targets
1353 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
1354 // instructions are special in various ways, which require special support to
1355 // insert. The specified MachineInstr is created but not inserted into any
1356 // basic blocks, and the scheduler passes ownership of it to this method.
1357 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
1358 MachineBasicBlock *MBB) const;
1360 //===--------------------------------------------------------------------===//
1361 // Addressing mode description hooks (used by LSR etc).
1364 /// AddrMode - This represents an addressing mode of:
1365 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1366 /// If BaseGV is null, there is no BaseGV.
1367 /// If BaseOffs is zero, there is no base offset.
1368 /// If HasBaseReg is false, there is no base register.
1369 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1373 GlobalValue *BaseGV;
1377 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1380 /// isLegalAddressingMode - Return true if the addressing mode represented by
1381 /// AM is legal for this target, for a load/store of the specified type.
1382 /// TODO: Handle pre/postinc as well.
1383 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1385 /// isTruncateFree - Return true if it's free to truncate a value of
1386 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1387 /// register EAX to i16 by referencing its sub-register AX.
1388 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1392 virtual bool isTruncateFree(MVT VT1, MVT VT2) const {
1396 /// isZExtFree - Return true if any actual instruction that defines a
1397 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
1398 /// register. This does not necessarily include registers defined in
1399 /// unknown ways, such as incoming arguments, or copies from unknown
1400 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1401 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1402 /// all instructions that define 32-bit values implicit zero-extend the
1403 /// result out to 64 bits.
1404 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
1408 virtual bool isZExtFree(MVT VT1, MVT VT2) const {
1412 //===--------------------------------------------------------------------===//
1413 // Div utility functions
1415 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1416 std::vector<SDNode*>* Created) const;
1417 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1418 std::vector<SDNode*>* Created) const;
1421 //===--------------------------------------------------------------------===//
1422 // Runtime Library hooks
1425 /// setLibcallName - Rename the default libcall routine name for the specified
1427 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1428 LibcallRoutineNames[Call] = Name;
1431 /// getLibcallName - Get the libcall routine name for the specified libcall.
1433 const char *getLibcallName(RTLIB::Libcall Call) const {
1434 return LibcallRoutineNames[Call];
1437 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1438 /// result of the comparison libcall against zero.
1439 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1440 CmpLibcallCCs[Call] = CC;
1443 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1444 /// the comparison libcall against zero.
1445 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1446 return CmpLibcallCCs[Call];
1451 const TargetData *TD;
1453 /// PointerTy - The type to use for pointers, usually i32 or i64.
1457 /// IsLittleEndian - True if this is a little endian target.
1459 bool IsLittleEndian;
1461 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
1463 bool UsesGlobalOffsetTable;
1465 /// SelectIsExpensive - Tells the code generator not to expand operations
1466 /// into sequences that use the select operations if possible.
1467 bool SelectIsExpensive;
1469 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1470 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1471 /// a real cost model is in place. If we ever optimize for size, this will be
1472 /// set to true unconditionally.
1475 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1476 /// srl/add/sra for a signed divide by power of two, and let the target handle
1478 bool Pow2DivIsCheap;
1480 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1481 /// llvm.setjmp. Defaults to false.
1482 bool UseUnderscoreSetJmp;
1484 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1485 /// llvm.longjmp. Defaults to false.
1486 bool UseUnderscoreLongJmp;
1488 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1492 OutOfRangeShiftAmount ShiftAmtHandling;
1494 /// BooleanContents - Information about the contents of the high-bits in
1495 /// boolean values held in a type wider than i1. See getBooleanContents.
1496 BooleanContent BooleanContents;
1498 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1499 /// total cycles or lowest register usage.
1500 SchedPreference SchedPreferenceInfo;
1502 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1503 unsigned JumpBufSize;
1505 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1507 unsigned JumpBufAlignment;
1509 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1511 unsigned IfCvtBlockSizeLimit;
1513 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1514 /// duplicated during if-conversion.
1515 unsigned IfCvtDupBlockSizeLimit;
1517 /// PrefLoopAlignment - The perferred loop alignment.
1519 unsigned PrefLoopAlignment;
1521 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1522 /// specifies the register that llvm.savestack/llvm.restorestack should save
1524 unsigned StackPointerRegisterToSaveRestore;
1526 /// ExceptionPointerRegister - If set to a physical register, this specifies
1527 /// the register that receives the exception address on entry to a landing
1529 unsigned ExceptionPointerRegister;
1531 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1532 /// the register that receives the exception typeid on entry to a landing
1534 unsigned ExceptionSelectorRegister;
1536 /// RegClassForVT - This indicates the default register class to use for
1537 /// each ValueType the target supports natively.
1538 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1539 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1540 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1542 /// TransformToType - For any value types we are promoting or expanding, this
1543 /// contains the value type that we are changing to. For Expanded types, this
1544 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1545 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1546 /// by the system, this holds the same type (e.g. i32 -> i32).
1547 MVT TransformToType[MVT::LAST_VALUETYPE];
1549 /// OpActions - For each operation and each value type, keep a LegalizeAction
1550 /// that indicates how instruction selection should deal with the operation.
1551 /// Most operations are Legal (aka, supported natively by the target), but
1552 /// operations that are not should be described. Note that operations on
1553 /// non-legal value types are not described here.
1554 uint64_t OpActions[ISD::BUILTIN_OP_END];
1556 /// LoadExtActions - For each load of load extension type and each value type,
1557 /// keep a LegalizeAction that indicates how instruction selection should deal
1559 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE];
1561 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
1562 /// indicates how instruction selection should deal with the store.
1563 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
1565 /// IndexedModeActions - For each indexed mode and each value type, keep a
1566 /// pair of LegalizeAction that indicates how instruction selection should
1567 /// deal with the load / store.
1568 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
1570 /// ConvertActions - For each conversion from source type to destination type,
1571 /// keep a LegalizeAction that indicates how instruction selection should
1572 /// deal with the conversion.
1573 /// Currently, this is used only for floating->floating conversions
1574 /// (FP_EXTEND and FP_ROUND).
1575 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
1577 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1578 /// LegalizeAction that indicates how instruction selection should
1579 /// deal with the condition code.
1580 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1582 ValueTypeActionImpl ValueTypeActions;
1584 std::vector<APFloat> LegalFPImmediates;
1586 std::vector<std::pair<MVT, TargetRegisterClass*> > AvailableRegClasses;
1588 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1589 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1590 /// which sets a bit in this array.
1592 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1594 /// PromoteToType - For operations that must be promoted to a specific type,
1595 /// this holds the destination type. This map should be sparse, so don't hold
1598 /// Targets add entries to this map with AddPromotedToType(..), clients access
1599 /// this with getTypeToPromoteTo(..).
1600 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1603 /// LibcallRoutineNames - Stores the name each libcall.
1605 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1607 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1608 /// of each of the comparison libcall against zero.
1609 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1612 /// When lowering \@llvm.memset this field specifies the maximum number of
1613 /// store operations that may be substituted for the call to memset. Targets
1614 /// must set this value based on the cost threshold for that target. Targets
1615 /// should assume that the memset will be done using as many of the largest
1616 /// store operations first, followed by smaller ones, if necessary, per
1617 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1618 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1619 /// store. This only applies to setting a constant array of a constant size.
1620 /// @brief Specify maximum number of store instructions per memset call.
1621 unsigned maxStoresPerMemset;
1623 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1624 /// store operations that may be substituted for a call to memcpy. Targets
1625 /// must set this value based on the cost threshold for that target. Targets
1626 /// should assume that the memcpy will be done using as many of the largest
1627 /// store operations first, followed by smaller ones, if necessary, per
1628 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1629 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1630 /// and one 1-byte store. This only applies to copying a constant array of
1632 /// @brief Specify maximum bytes of store instructions per memcpy call.
1633 unsigned maxStoresPerMemcpy;
1635 /// When lowering \@llvm.memmove this field specifies the maximum number of
1636 /// store instructions that may be substituted for a call to memmove. Targets
1637 /// must set this value based on the cost threshold for that target. Targets
1638 /// should assume that the memmove will be done using as many of the largest
1639 /// store operations first, followed by smaller ones, if necessary, per
1640 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1641 /// with 8-bit alignment would result in nine 1-byte stores. This only
1642 /// applies to copying a constant array of constant size.
1643 /// @brief Specify maximum bytes of store instructions per memmove call.
1644 unsigned maxStoresPerMemmove;
1646 /// This field specifies whether the target machine permits unaligned memory
1647 /// accesses. This is used, for example, to determine the size of store
1648 /// operations when copying small arrays and other similar tasks.
1649 /// @brief Indicate whether the target permits unaligned memory accesses.
1650 bool allowUnalignedMemoryAccesses;
1652 } // end llvm namespace