1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/IR/IRBuilder.h"
35 #include "llvm/MC/MCRegisterInfo.h"
36 #include "llvm/Target/TargetCallingConv.h"
37 #include "llvm/Target/TargetMachine.h"
46 class FunctionLoweringInfo;
47 class ImmutableCallSite;
49 class MachineBasicBlock;
50 class MachineFunction;
52 class MachineJumpTableInfo;
57 template<typename T> class SmallVectorImpl;
59 class TargetRegisterClass;
60 class TargetLibraryInfo;
61 class TargetLoweringObjectFile;
66 None, // No preference
67 Source, // Follow source order.
68 RegPressure, // Scheduling for lowest register pressure.
69 Hybrid, // Scheduling for both latency and register pressure.
70 ILP, // Scheduling for ILP in low register pressure mode.
71 VLIW // Scheduling for VLIW targets.
75 /// This base class for TargetLowering contains the SelectionDAG-independent
76 /// parts that can be used from the rest of CodeGen.
77 class TargetLoweringBase {
78 TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
79 void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
82 /// This enum indicates whether operations are valid for a target, and if not,
83 /// what action should be used to make them valid.
85 Legal, // The target natively supports this operation.
86 Promote, // This operation should be executed in a larger type.
87 Expand, // Try to expand this to other ops, otherwise use a libcall.
88 Custom // Use the LowerOperation hook to implement custom lowering.
91 /// This enum indicates whether a types are legal for a target, and if not,
92 /// what action should be used to make them valid.
93 enum LegalizeTypeAction {
94 TypeLegal, // The target natively supports this type.
95 TypePromoteInteger, // Replace this integer with a larger one.
96 TypeExpandInteger, // Split this integer into two of half the size.
97 TypeSoftenFloat, // Convert this float to a same size integer type.
98 TypeExpandFloat, // Split this float into two of half the size.
99 TypeScalarizeVector, // Replace this one-element vector with its element.
100 TypeSplitVector, // Split this vector into two of half the size.
101 TypeWidenVector // This vector should be widened into a larger vector.
104 /// LegalizeKind holds the legalization kind that needs to happen to EVT
105 /// in order to type-legalize it.
106 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
108 /// Enum that describes how the target represents true/false values.
109 enum BooleanContent {
110 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
111 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
112 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
115 /// Enum that describes what type of support for selects the target has.
116 enum SelectSupportKind {
117 ScalarValSelect, // The target supports scalar selects (ex: cmov).
118 ScalarCondVectorVal, // The target supports selects with a scalar condition
119 // and vector values (ex: cmov).
120 VectorMaskSelect // The target supports vector selects with a vector
121 // mask (ex: x86 blends).
124 static ISD::NodeType getExtendForContent(BooleanContent Content) {
126 case UndefinedBooleanContent:
127 // Extend by adding rubbish bits.
128 return ISD::ANY_EXTEND;
129 case ZeroOrOneBooleanContent:
130 // Extend by adding zero bits.
131 return ISD::ZERO_EXTEND;
132 case ZeroOrNegativeOneBooleanContent:
133 // Extend by copying the sign bit.
134 return ISD::SIGN_EXTEND;
136 llvm_unreachable("Invalid content kind");
139 /// NOTE: The constructor takes ownership of TLOF.
140 explicit TargetLoweringBase(const TargetMachine &TM,
141 const TargetLoweringObjectFile *TLOF);
142 virtual ~TargetLoweringBase();
145 /// \brief Initialize all of the actions to default values.
149 const TargetMachine &getTargetMachine() const { return TM; }
150 const DataLayout *getDataLayout() const { return DL; }
151 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
153 bool isBigEndian() const { return !IsLittleEndian; }
154 bool isLittleEndian() const { return IsLittleEndian; }
156 /// Return the pointer type for the given address space, defaults to
157 /// the pointer type from the data layout.
158 /// FIXME: The default needs to be removed once all the code is updated.
159 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const;
160 unsigned getPointerSizeInBits(uint32_t AS = 0) const;
161 unsigned getPointerTypeSizeInBits(Type *Ty) const;
162 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
164 EVT getShiftAmountTy(EVT LHSTy) const;
166 /// Returns the type to be used for the index operand of:
167 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
168 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
169 virtual MVT getVectorIdxTy() const {
170 return getPointerTy();
173 /// Return true if the select operation is expensive for this target.
174 bool isSelectExpensive() const { return SelectIsExpensive; }
176 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
180 /// Return true if multiple condition registers are available.
181 bool hasMultipleConditionRegisters() const {
182 return HasMultipleConditionRegisters;
185 /// Return true if the target has BitExtract instructions.
186 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
188 /// Return the preferred vector type legalization action.
189 virtual TargetLoweringBase::LegalizeTypeAction
190 getPreferredVectorAction(EVT VT) const {
191 // The default action for one element vectors is to scalarize
192 if (VT.getVectorNumElements() == 1)
193 return TypeScalarizeVector;
194 // The default action for other vectors is to promote
195 return TypePromoteInteger;
198 // There are two general methods for expanding a BUILD_VECTOR node:
199 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
201 // 2. Build the vector on the stack and then load it.
202 // If this function returns true, then method (1) will be used, subject to
203 // the constraint that all of the necessary shuffles are legal (as determined
204 // by isShuffleMaskLegal). If this function returns false, then method (2) is
205 // always used. The vector type, and the number of defined values, are
208 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
209 unsigned DefinedValues) const {
210 return DefinedValues < 3;
213 /// Return true if integer divide is usually cheaper than a sequence of
214 /// several shifts, adds, and multiplies for this target.
215 bool isIntDivCheap() const { return IntDivIsCheap; }
217 /// Returns true if target has indicated at least one type should be bypassed.
218 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
220 /// Returns map of slow types for division or remainder with corresponding
222 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
223 return BypassSlowDivWidths;
226 /// Return true if pow2 div is cheaper than a chain of srl/add/sra.
227 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
229 /// Return true if Flow Control is an expensive operation that should be
231 bool isJumpExpensive() const { return JumpIsExpensive; }
233 /// Return true if selects are only cheaper than branches if the branch is
234 /// unlikely to be predicted right.
235 bool isPredictableSelectExpensive() const {
236 return PredictableSelectIsExpensive;
239 /// isLoadBitCastBeneficial() - Return true if the following transform
241 /// fold (conv (load x)) -> (load (conv*)x)
242 /// On architectures that don't natively support some vector loads efficiently,
243 /// casting the load to a smaller vector of larger types and loading
244 /// is more efficient, however, this can be undone by optimizations in
246 virtual bool isLoadBitCastBeneficial(EVT /* Load */, EVT /* Bitcast */) const {
250 /// \brief Return if the target supports combining a
253 /// %andResult = and %val1, #imm-with-one-bit-set;
254 /// %icmpResult = icmp %andResult, 0
255 /// br i1 %icmpResult, label %dest1, label %dest2
257 /// into a single machine instruction of a form like:
259 /// brOnBitSet %register, #bitNumber, dest
261 bool isMaskAndBranchFoldingLegal() const {
262 return MaskAndBranchFoldingIsLegal;
265 /// Return true if target supports floating point exceptions.
266 bool hasFloatingPointExceptions() const {
267 return HasFloatingPointExceptions;
270 /// Return the ValueType of the result of SETCC operations. Also used to
271 /// obtain the target's preferred type for the condition operand of SELECT and
272 /// BRCOND nodes. In the case of BRCOND the argument passed is MVT::Other
273 /// since there are no other operands to get a type hint from.
274 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
276 /// Return the ValueType for comparison libcalls. Comparions libcalls include
277 /// floating point comparion calls, and Ordered/Unordered check calls on
278 /// floating point numbers.
280 MVT::SimpleValueType getCmpLibcallReturnType() const;
282 /// For targets without i1 registers, this gives the nature of the high-bits
283 /// of boolean values held in types wider than i1.
285 /// "Boolean values" are special true/false values produced by nodes like
286 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
287 /// Not to be confused with general values promoted from i1. Some cpus
288 /// distinguish between vectors of boolean and scalars; the isVec parameter
289 /// selects between the two kinds. For example on X86 a scalar boolean should
290 /// be zero extended from i1, while the elements of a vector of booleans
291 /// should be sign extended from i1.
293 /// Some cpus also treat floating point types the same way as they treat
294 /// vectors instead of the way they treat scalars.
295 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
297 return BooleanVectorContents;
298 return isFloat ? BooleanFloatContents : BooleanContents;
301 BooleanContent getBooleanContents(EVT Type) const {
302 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
305 /// Return target scheduling preference.
306 Sched::Preference getSchedulingPreference() const {
307 return SchedPreferenceInfo;
310 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
311 /// for different nodes. This function returns the preference (or none) for
313 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
317 /// Return the register class that should be used for the specified value
319 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
320 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
321 assert(RC && "This value type is not natively supported!");
325 /// Return the 'representative' register class for the specified value
328 /// The 'representative' register class is the largest legal super-reg
329 /// register class for the register class of the value type. For example, on
330 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
331 /// register class is GR64 on x86_64.
332 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
333 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
337 /// Return the cost of the 'representative' register class for the specified
339 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
340 return RepRegClassCostForVT[VT.SimpleTy];
343 /// Return true if the target has native support for the specified value type.
344 /// This means that it has a register that directly holds it without
345 /// promotions or expansions.
346 bool isTypeLegal(EVT VT) const {
347 assert(!VT.isSimple() ||
348 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
349 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
352 class ValueTypeActionImpl {
353 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
354 /// that indicates how instruction selection should deal with the type.
355 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
358 ValueTypeActionImpl() {
359 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions), 0);
362 LegalizeTypeAction getTypeAction(MVT VT) const {
363 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
366 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
367 unsigned I = VT.SimpleTy;
368 ValueTypeActions[I] = Action;
372 const ValueTypeActionImpl &getValueTypeActions() const {
373 return ValueTypeActions;
376 /// Return how we should legalize values of this type, either it is already
377 /// legal (return 'Legal') or we need to promote it to a larger type (return
378 /// 'Promote'), or we need to expand it into multiple registers of smaller
379 /// integer type (return 'Expand'). 'Custom' is not an option.
380 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
381 return getTypeConversion(Context, VT).first;
383 LegalizeTypeAction getTypeAction(MVT VT) const {
384 return ValueTypeActions.getTypeAction(VT);
387 /// For types supported by the target, this is an identity function. For
388 /// types that must be promoted to larger types, this returns the larger type
389 /// to promote to. For integer types that are larger than the largest integer
390 /// register, this contains one step in the expansion to get to the smaller
391 /// register. For illegal floating point types, this returns the integer type
393 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
394 return getTypeConversion(Context, VT).second;
397 /// For types supported by the target, this is an identity function. For
398 /// types that must be expanded (i.e. integer types that are larger than the
399 /// largest integer register or illegal floating point types), this returns
400 /// the largest legal type it will be expanded to.
401 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
402 assert(!VT.isVector());
404 switch (getTypeAction(Context, VT)) {
407 case TypeExpandInteger:
408 VT = getTypeToTransformTo(Context, VT);
411 llvm_unreachable("Type is not legal nor is it to be expanded!");
416 /// Vector types are broken down into some number of legal first class types.
417 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
418 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
419 /// turns into 4 EVT::i32 values with both PPC and X86.
421 /// This method returns the number of registers needed, and the VT for each
422 /// register. It also returns the VT and quantity of the intermediate values
423 /// before they are promoted/expanded.
424 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
426 unsigned &NumIntermediates,
427 MVT &RegisterVT) const;
429 struct IntrinsicInfo {
430 unsigned opc; // target opcode
431 EVT memVT; // memory VT
432 const Value* ptrVal; // value representing memory location
433 int offset; // offset off of ptrVal
434 unsigned size; // the size of the memory location
435 // (taken from memVT if zero)
436 unsigned align; // alignment
437 bool vol; // is volatile?
438 bool readMem; // reads memory?
439 bool writeMem; // writes memory?
441 IntrinsicInfo() : opc(0), ptrVal(nullptr), offset(0), size(0), align(1),
442 vol(false), readMem(false), writeMem(false) {}
445 /// Given an intrinsic, checks if on the target the intrinsic will need to map
446 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
447 /// true and store the intrinsic information into the IntrinsicInfo that was
448 /// passed to the function.
449 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
450 unsigned /*Intrinsic*/) const {
454 /// Returns true if the target can instruction select the specified FP
455 /// immediate natively. If false, the legalizer will materialize the FP
456 /// immediate as a load from a constant pool.
457 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
461 /// Targets can use this to indicate that they only support *some*
462 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
463 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
465 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
470 /// Returns true if the operation can trap for the value type.
472 /// VT must be a legal type. By default, we optimistically assume most
473 /// operations don't trap except for divide and remainder.
474 virtual bool canOpTrap(unsigned Op, EVT VT) const;
476 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
477 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
478 /// a VAND with a constant pool entry.
479 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
484 /// Return how this operation should be treated: either it is legal, needs to
485 /// be promoted to a larger size, needs to be expanded to some other code
486 /// sequence, or the target has a custom expander for it.
487 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
488 if (VT.isExtended()) return Expand;
489 // If a target-specific SDNode requires legalization, require the target
490 // to provide custom legalization for it.
491 if (Op > array_lengthof(OpActions[0])) return Custom;
492 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
493 return (LegalizeAction)OpActions[I][Op];
496 /// Return true if the specified operation is legal on this target or can be
497 /// made legal with custom lowering. This is used to help guide high-level
498 /// lowering decisions.
499 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
500 return (VT == MVT::Other || isTypeLegal(VT)) &&
501 (getOperationAction(Op, VT) == Legal ||
502 getOperationAction(Op, VT) == Custom);
505 /// Return true if the specified operation is legal on this target or can be
506 /// made legal using promotion. This is used to help guide high-level lowering
508 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
509 return (VT == MVT::Other || isTypeLegal(VT)) &&
510 (getOperationAction(Op, VT) == Legal ||
511 getOperationAction(Op, VT) == Promote);
514 /// Return true if the specified operation is illegal on this target or
515 /// unlikely to be made legal with custom lowering. This is used to help guide
516 /// high-level lowering decisions.
517 bool isOperationExpand(unsigned Op, EVT VT) const {
518 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
521 /// Return true if the specified operation is legal on this target.
522 bool isOperationLegal(unsigned Op, EVT VT) const {
523 return (VT == MVT::Other || isTypeLegal(VT)) &&
524 getOperationAction(Op, VT) == Legal;
527 /// Return how this load with extension should be treated: either it is legal,
528 /// needs to be promoted to a larger size, needs to be expanded to some other
529 /// code sequence, or the target has a custom expander for it.
530 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const {
531 if (VT.isExtended()) return Expand;
532 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
533 assert(ExtType < ISD::LAST_LOADEXT_TYPE && I < MVT::LAST_VALUETYPE &&
534 "Table isn't big enough!");
535 return (LegalizeAction)LoadExtActions[I][ExtType];
538 /// Return true if the specified load with extension is legal on this target.
539 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
540 return VT.isSimple() &&
541 getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
544 /// Return how this store with truncation should be treated: either it is
545 /// legal, needs to be promoted to a larger size, needs to be expanded to some
546 /// other code sequence, or the target has a custom expander for it.
547 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
548 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
549 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
550 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
551 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
552 "Table isn't big enough!");
553 return (LegalizeAction)TruncStoreActions[ValI][MemI];
556 /// Return true if the specified store with truncation is legal on this
558 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
559 return isTypeLegal(ValVT) && MemVT.isSimple() &&
560 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
563 /// Return how the indexed load should be treated: either it is legal, needs
564 /// to be promoted to a larger size, needs to be expanded to some other code
565 /// sequence, or the target has a custom expander for it.
567 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
568 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
569 "Table isn't big enough!");
570 unsigned Ty = (unsigned)VT.SimpleTy;
571 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
574 /// Return true if the specified indexed load is legal on this target.
575 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
576 return VT.isSimple() &&
577 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
578 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
581 /// Return how the indexed store should be treated: either it is legal, needs
582 /// to be promoted to a larger size, needs to be expanded to some other code
583 /// sequence, or the target has a custom expander for it.
585 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
586 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
587 "Table isn't big enough!");
588 unsigned Ty = (unsigned)VT.SimpleTy;
589 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
592 /// Return true if the specified indexed load is legal on this target.
593 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
594 return VT.isSimple() &&
595 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
596 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
599 /// Return how the condition code should be treated: either it is legal, needs
600 /// to be expanded to some other code sequence, or the target has a custom
603 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
604 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
605 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
606 "Table isn't big enough!");
607 // See setCondCodeAction for how this is encoded.
608 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
609 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
610 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
611 assert(Action != Promote && "Can't promote condition code!");
615 /// Return true if the specified condition code is legal on this target.
616 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
618 getCondCodeAction(CC, VT) == Legal ||
619 getCondCodeAction(CC, VT) == Custom;
623 /// If the action for this operation is to promote, this method returns the
624 /// ValueType to promote to.
625 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
626 assert(getOperationAction(Op, VT) == Promote &&
627 "This operation isn't promoted!");
629 // See if this has an explicit type specified.
630 std::map<std::pair<unsigned, MVT::SimpleValueType>,
631 MVT::SimpleValueType>::const_iterator PTTI =
632 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
633 if (PTTI != PromoteToType.end()) return PTTI->second;
635 assert((VT.isInteger() || VT.isFloatingPoint()) &&
636 "Cannot autopromote this type, add it with AddPromotedToType.");
640 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
641 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
642 "Didn't find type to promote to!");
643 } while (!isTypeLegal(NVT) ||
644 getOperationAction(Op, NVT) == Promote);
648 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
649 /// operations except for the pointer size. If AllowUnknown is true, this
650 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
651 /// otherwise it will assert.
652 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
653 // Lower scalar pointers to native pointer types.
654 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
655 return getPointerTy(PTy->getAddressSpace());
657 if (Ty->isVectorTy()) {
658 VectorType *VTy = cast<VectorType>(Ty);
659 Type *Elm = VTy->getElementType();
660 // Lower vectors of pointers to native pointer types.
661 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
662 EVT PointerTy(getPointerTy(PT->getAddressSpace()));
663 Elm = PointerTy.getTypeForEVT(Ty->getContext());
666 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
667 VTy->getNumElements());
669 return EVT::getEVT(Ty, AllowUnknown);
672 /// Return the MVT corresponding to this LLVM type. See getValueType.
673 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
674 return getValueType(Ty, AllowUnknown).getSimpleVT();
677 /// Return the desired alignment for ByVal or InAlloca aggregate function
678 /// arguments in the caller parameter area. This is the actual alignment, not
680 virtual unsigned getByValTypeAlignment(Type *Ty) const;
682 /// Return the type of registers that this ValueType will eventually require.
683 MVT getRegisterType(MVT VT) const {
684 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
685 return RegisterTypeForVT[VT.SimpleTy];
688 /// Return the type of registers that this ValueType will eventually require.
689 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
691 assert((unsigned)VT.getSimpleVT().SimpleTy <
692 array_lengthof(RegisterTypeForVT));
693 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
698 unsigned NumIntermediates;
699 (void)getVectorTypeBreakdown(Context, VT, VT1,
700 NumIntermediates, RegisterVT);
703 if (VT.isInteger()) {
704 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
706 llvm_unreachable("Unsupported extended type!");
709 /// Return the number of registers that this ValueType will eventually
712 /// This is one for any types promoted to live in larger registers, but may be
713 /// more than one for types (like i64) that are split into pieces. For types
714 /// like i140, which are first promoted then expanded, it is the number of
715 /// registers needed to hold all the bits of the original type. For an i140
716 /// on a 32 bit machine this means 5 registers.
717 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
719 assert((unsigned)VT.getSimpleVT().SimpleTy <
720 array_lengthof(NumRegistersForVT));
721 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
726 unsigned NumIntermediates;
727 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
729 if (VT.isInteger()) {
730 unsigned BitWidth = VT.getSizeInBits();
731 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
732 return (BitWidth + RegWidth - 1) / RegWidth;
734 llvm_unreachable("Unsupported extended type!");
737 /// If true, then instruction selection should seek to shrink the FP constant
738 /// of the specified type to a smaller type in order to save space and / or
740 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
742 /// When splitting a value of the specified type into parts, does the Lo
743 /// or Hi part come first? This usually follows the endianness, except
744 /// for ppcf128, where the Hi part always comes first.
745 bool hasBigEndianPartOrdering(EVT VT) const {
746 return isBigEndian() || VT == MVT::ppcf128;
749 /// If true, the target has custom DAG combine transformations that it can
750 /// perform for the specified node.
751 bool hasTargetDAGCombine(ISD::NodeType NT) const {
752 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
753 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
756 /// \brief Get maximum # of store operations permitted for llvm.memset
758 /// This function returns the maximum number of store operations permitted
759 /// to replace a call to llvm.memset. The value is set by the target at the
760 /// performance threshold for such a replacement. If OptSize is true,
761 /// return the limit for functions that have OptSize attribute.
762 unsigned getMaxStoresPerMemset(bool OptSize) const {
763 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
766 /// \brief Get maximum # of store operations permitted for llvm.memcpy
768 /// This function returns the maximum number of store operations permitted
769 /// to replace a call to llvm.memcpy. The value is set by the target at the
770 /// performance threshold for such a replacement. If OptSize is true,
771 /// return the limit for functions that have OptSize attribute.
772 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
773 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
776 /// \brief Get maximum # of store operations permitted for llvm.memmove
778 /// This function returns the maximum number of store operations permitted
779 /// to replace a call to llvm.memmove. The value is set by the target at the
780 /// performance threshold for such a replacement. If OptSize is true,
781 /// return the limit for functions that have OptSize attribute.
782 unsigned getMaxStoresPerMemmove(bool OptSize) const {
783 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
786 /// \brief Determine if the target supports unaligned memory accesses.
788 /// This function returns true if the target allows unaligned memory accesses
789 /// of the specified type in the given address space. If true, it also returns
790 /// whether the unaligned memory access is "fast" in the last argument by
791 /// reference. This is used, for example, in situations where an array
792 /// copy/move/set is converted to a sequence of store operations. Its use
793 /// helps to ensure that such replacements don't generate code that causes an
794 /// alignment error (trap) on the target machine.
795 virtual bool allowsMisalignedMemoryAccesses(EVT,
796 unsigned AddrSpace = 0,
798 bool * /*Fast*/ = nullptr) const {
802 /// Returns the target specific optimal type for load and store operations as
803 /// a result of memset, memcpy, and memmove lowering.
805 /// If DstAlign is zero that means it's safe to destination alignment can
806 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
807 /// a need to check it against alignment requirement, probably because the
808 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
809 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
810 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
811 /// does not need to be loaded. It returns EVT::Other if the type should be
812 /// determined using generic target-independent logic.
813 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
814 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
817 bool /*MemcpyStrSrc*/,
818 MachineFunction &/*MF*/) const {
822 /// Returns true if it's safe to use load / store of the specified type to
823 /// expand memcpy / memset inline.
825 /// This is mostly true for all types except for some special cases. For
826 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
827 /// fstpl which also does type conversion. Note the specified type doesn't
828 /// have to be legal as the hook is used before type legalization.
829 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
831 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
832 bool usesUnderscoreSetJmp() const {
833 return UseUnderscoreSetJmp;
836 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
837 bool usesUnderscoreLongJmp() const {
838 return UseUnderscoreLongJmp;
841 /// Return whether the target can generate code for jump tables.
842 bool supportJumpTables() const {
843 return SupportJumpTables;
846 /// Return integer threshold on number of blocks to use jump tables rather
847 /// than if sequence.
848 int getMinimumJumpTableEntries() const {
849 return MinimumJumpTableEntries;
852 /// If a physical register, this specifies the register that
853 /// llvm.savestack/llvm.restorestack should save and restore.
854 unsigned getStackPointerRegisterToSaveRestore() const {
855 return StackPointerRegisterToSaveRestore;
858 /// If a physical register, this returns the register that receives the
859 /// exception address on entry to a landing pad.
860 unsigned getExceptionPointerRegister() const {
861 return ExceptionPointerRegister;
864 /// If a physical register, this returns the register that receives the
865 /// exception typeid on entry to a landing pad.
866 unsigned getExceptionSelectorRegister() const {
867 return ExceptionSelectorRegister;
870 /// Returns the target's jmp_buf size in bytes (if never set, the default is
872 unsigned getJumpBufSize() const {
876 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
878 unsigned getJumpBufAlignment() const {
879 return JumpBufAlignment;
882 /// Return the minimum stack alignment of an argument.
883 unsigned getMinStackArgumentAlignment() const {
884 return MinStackArgumentAlignment;
887 /// Return the minimum function alignment.
888 unsigned getMinFunctionAlignment() const {
889 return MinFunctionAlignment;
892 /// Return the preferred function alignment.
893 unsigned getPrefFunctionAlignment() const {
894 return PrefFunctionAlignment;
897 /// Return the preferred loop alignment.
898 unsigned getPrefLoopAlignment() const {
899 return PrefLoopAlignment;
902 /// Return whether the DAG builder should automatically insert fences and
903 /// reduce ordering for atomics.
904 bool getInsertFencesForAtomic() const {
905 return InsertFencesForAtomic;
908 /// Return true if the target stores stack protector cookies at a fixed offset
909 /// in some non-standard address space, and populates the address space and
910 /// offset as appropriate.
911 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
912 unsigned &/*Offset*/) const {
916 /// Returns the maximal possible offset which can be used for loads / stores
918 virtual unsigned getMaximalGlobalOffset() const {
922 /// Returns true if a cast between SrcAS and DestAS is a noop.
923 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
927 //===--------------------------------------------------------------------===//
928 /// \name Helpers for TargetTransformInfo implementations
931 /// Get the ISD node that corresponds to the Instruction class opcode.
932 int InstructionOpcodeToISD(unsigned Opcode) const;
934 /// Estimate the cost of type-legalization and the legalized type.
935 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;
939 //===--------------------------------------------------------------------===//
940 /// \name Helpers for atomic expansion.
943 /// Perform a load-linked operation on Addr, returning a "Value *" with the
944 /// corresponding pointee type. This may entail some non-trivial operations to
945 /// truncate or reconstruct types that will be illegal in the backend. See
946 /// ARMISelLowering for an example implementation.
947 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
948 AtomicOrdering Ord) const {
949 llvm_unreachable("Load linked unimplemented on this target");
952 /// Perform a store-conditional operation to Addr. Return the status of the
953 /// store. This should be 0 if the store succeeded, non-zero otherwise.
954 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
955 Value *Addr, AtomicOrdering Ord) const {
956 llvm_unreachable("Store conditional unimplemented on this target");
959 /// Return true if the given (atomic) instruction should be expanded by the
960 /// IR-level AtomicExpand pass into a loop involving
961 /// load-linked/store-conditional pairs. Atomic stores will be expanded in the
962 /// same way as "atomic xchg" operations which ignore their output if needed.
963 virtual bool shouldExpandAtomicInIR(Instruction *Inst) const {
968 //===--------------------------------------------------------------------===//
969 // TargetLowering Configuration Methods - These methods should be invoked by
970 // the derived class constructor to configure this object for the target.
973 /// \brief Reset the operation actions based on target options.
974 virtual void resetOperationActions() {}
977 /// Specify how the target extends the result of integer and floating point
978 /// boolean values from i1 to a wider type. See getBooleanContents.
979 void setBooleanContents(BooleanContent Ty) {
980 BooleanContents = Ty;
981 BooleanFloatContents = Ty;
984 /// Specify how the target extends the result of integer and floating point
985 /// boolean values from i1 to a wider type. See getBooleanContents.
986 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
987 BooleanContents = IntTy;
988 BooleanFloatContents = FloatTy;
991 /// Specify how the target extends the result of a vector boolean value from a
992 /// vector of i1 to a wider type. See getBooleanContents.
993 void setBooleanVectorContents(BooleanContent Ty) {
994 BooleanVectorContents = Ty;
997 /// Specify the target scheduling preference.
998 void setSchedulingPreference(Sched::Preference Pref) {
999 SchedPreferenceInfo = Pref;
1002 /// Indicate whether this target prefers to use _setjmp to implement
1003 /// llvm.setjmp or the version without _. Defaults to false.
1004 void setUseUnderscoreSetJmp(bool Val) {
1005 UseUnderscoreSetJmp = Val;
1008 /// Indicate whether this target prefers to use _longjmp to implement
1009 /// llvm.longjmp or the version without _. Defaults to false.
1010 void setUseUnderscoreLongJmp(bool Val) {
1011 UseUnderscoreLongJmp = Val;
1014 /// Indicate whether the target can generate code for jump tables.
1015 void setSupportJumpTables(bool Val) {
1016 SupportJumpTables = Val;
1019 /// Indicate the number of blocks to generate jump tables rather than if
1021 void setMinimumJumpTableEntries(int Val) {
1022 MinimumJumpTableEntries = Val;
1025 /// If set to a physical register, this specifies the register that
1026 /// llvm.savestack/llvm.restorestack should save and restore.
1027 void setStackPointerRegisterToSaveRestore(unsigned R) {
1028 StackPointerRegisterToSaveRestore = R;
1031 /// If set to a physical register, this sets the register that receives the
1032 /// exception address on entry to a landing pad.
1033 void setExceptionPointerRegister(unsigned R) {
1034 ExceptionPointerRegister = R;
1037 /// If set to a physical register, this sets the register that receives the
1038 /// exception typeid on entry to a landing pad.
1039 void setExceptionSelectorRegister(unsigned R) {
1040 ExceptionSelectorRegister = R;
1043 /// Tells the code generator not to expand operations into sequences that use
1044 /// the select operations if possible.
1045 void setSelectIsExpensive(bool isExpensive = true) {
1046 SelectIsExpensive = isExpensive;
1049 /// Tells the code generator that the target has multiple (allocatable)
1050 /// condition registers that can be used to store the results of comparisons
1051 /// for use by selects and conditional branches. With multiple condition
1052 /// registers, the code generator will not aggressively sink comparisons into
1053 /// the blocks of their users.
1054 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1055 HasMultipleConditionRegisters = hasManyRegs;
1058 /// Tells the code generator that the target has BitExtract instructions.
1059 /// The code generator will aggressively sink "shift"s into the blocks of
1060 /// their users if the users will generate "and" instructions which can be
1061 /// combined with "shift" to BitExtract instructions.
1062 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1063 HasExtractBitsInsn = hasExtractInsn;
1066 /// Tells the code generator not to expand sequence of operations into a
1067 /// separate sequences that increases the amount of flow control.
1068 void setJumpIsExpensive(bool isExpensive = true) {
1069 JumpIsExpensive = isExpensive;
1072 /// Tells the code generator that integer divide is expensive, and if
1073 /// possible, should be replaced by an alternate sequence of instructions not
1074 /// containing an integer divide.
1075 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1077 /// Tells the code generator that this target supports floating point
1078 /// exceptions and cares about preserving floating point exception behavior.
1079 void setHasFloatingPointExceptions(bool FPExceptions = true) {
1080 HasFloatingPointExceptions = FPExceptions;
1083 /// Tells the code generator which bitwidths to bypass.
1084 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1085 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1088 /// Tells the code generator that it shouldn't generate srl/add/sra for a
1089 /// signed divide by power of two, and let the target handle it.
1090 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
1092 /// Add the specified register class as an available regclass for the
1093 /// specified value type. This indicates the selector can handle values of
1094 /// that class natively.
1095 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1096 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1097 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1098 RegClassForVT[VT.SimpleTy] = RC;
1101 /// Remove all register classes.
1102 void clearRegisterClasses() {
1103 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1105 AvailableRegClasses.clear();
1108 /// \brief Remove all operation actions.
1109 void clearOperationActions() {
1112 /// Return the largest legal super-reg register class of the register class
1113 /// for the specified type and its associated "cost".
1114 virtual std::pair<const TargetRegisterClass*, uint8_t>
1115 findRepresentativeClass(MVT VT) const;
1117 /// Once all of the register classes are added, this allows us to compute
1118 /// derived properties we expose.
1119 void computeRegisterProperties();
1121 /// Indicate that the specified operation does not work with the specified
1122 /// type and indicate what to do about it.
1123 void setOperationAction(unsigned Op, MVT VT,
1124 LegalizeAction Action) {
1125 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1126 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1129 /// Indicate that the specified load with extension does not work with the
1130 /// specified type and indicate what to do about it.
1131 void setLoadExtAction(unsigned ExtType, MVT VT,
1132 LegalizeAction Action) {
1133 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
1134 "Table isn't big enough!");
1135 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1138 /// Indicate that the specified truncating store does not work with the
1139 /// specified type and indicate what to do about it.
1140 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1141 LegalizeAction Action) {
1142 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
1143 "Table isn't big enough!");
1144 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1147 /// Indicate that the specified indexed load does or does not work with the
1148 /// specified type and indicate what to do abort it.
1150 /// NOTE: All indexed mode loads are initialized to Expand in
1151 /// TargetLowering.cpp
1152 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1153 LegalizeAction Action) {
1154 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1155 (unsigned)Action < 0xf && "Table isn't big enough!");
1156 // Load action are kept in the upper half.
1157 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1158 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1161 /// Indicate that the specified indexed store does or does not work with the
1162 /// specified type and indicate what to do about it.
1164 /// NOTE: All indexed mode stores are initialized to Expand in
1165 /// TargetLowering.cpp
1166 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1167 LegalizeAction Action) {
1168 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1169 (unsigned)Action < 0xf && "Table isn't big enough!");
1170 // Store action are kept in the lower half.
1171 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1172 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1175 /// Indicate that the specified condition code is or isn't supported on the
1176 /// target and indicate what to do about it.
1177 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1178 LegalizeAction Action) {
1179 assert(VT < MVT::LAST_VALUETYPE &&
1180 (unsigned)CC < array_lengthof(CondCodeActions) &&
1181 "Table isn't big enough!");
1182 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1183 /// value and the upper 27 bits index into the second dimension of the array
1184 /// to select what 32-bit value to use.
1185 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1186 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1187 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1190 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1191 /// to trying a larger integer/fp until it can find one that works. If that
1192 /// default is insufficient, this method can be used by the target to override
1194 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1195 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1198 /// Targets should invoke this method for each target independent node that
1199 /// they want to provide a custom DAG combiner for by implementing the
1200 /// PerformDAGCombine virtual method.
1201 void setTargetDAGCombine(ISD::NodeType NT) {
1202 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1203 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1206 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1207 void setJumpBufSize(unsigned Size) {
1211 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1213 void setJumpBufAlignment(unsigned Align) {
1214 JumpBufAlignment = Align;
1217 /// Set the target's minimum function alignment (in log2(bytes))
1218 void setMinFunctionAlignment(unsigned Align) {
1219 MinFunctionAlignment = Align;
1222 /// Set the target's preferred function alignment. This should be set if
1223 /// there is a performance benefit to higher-than-minimum alignment (in
1225 void setPrefFunctionAlignment(unsigned Align) {
1226 PrefFunctionAlignment = Align;
1229 /// Set the target's preferred loop alignment. Default alignment is zero, it
1230 /// means the target does not care about loop alignment. The alignment is
1231 /// specified in log2(bytes).
1232 void setPrefLoopAlignment(unsigned Align) {
1233 PrefLoopAlignment = Align;
1236 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1237 void setMinStackArgumentAlignment(unsigned Align) {
1238 MinStackArgumentAlignment = Align;
1241 /// Set if the DAG builder should automatically insert fences and reduce the
1242 /// order of atomic memory operations to Monotonic.
1243 void setInsertFencesForAtomic(bool fence) {
1244 InsertFencesForAtomic = fence;
1248 //===--------------------------------------------------------------------===//
1249 // Addressing mode description hooks (used by LSR etc).
1252 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1253 /// instructions reading the address. This allows as much computation as
1254 /// possible to be done in the address mode for that operand. This hook lets
1255 /// targets also pass back when this should be done on intrinsics which
1257 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1258 SmallVectorImpl<Value*> &/*Ops*/,
1259 Type *&/*AccessTy*/) const {
1263 /// This represents an addressing mode of:
1264 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1265 /// If BaseGV is null, there is no BaseGV.
1266 /// If BaseOffs is zero, there is no base offset.
1267 /// If HasBaseReg is false, there is no base register.
1268 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1271 GlobalValue *BaseGV;
1275 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1278 /// Return true if the addressing mode represented by AM is legal for this
1279 /// target, for a load/store of the specified type.
1281 /// The type may be VoidTy, in which case only return true if the addressing
1282 /// mode is legal for a load/store of any legal type. TODO: Handle
1283 /// pre/postinc as well.
1284 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1286 /// \brief Return the cost of the scaling factor used in the addressing mode
1287 /// represented by AM for this target, for a load/store of the specified type.
1289 /// If the AM is supported, the return value must be >= 0.
1290 /// If the AM is not supported, it returns a negative value.
1291 /// TODO: Handle pre/postinc as well.
1292 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const {
1293 // Default: assume that any scaling factor used in a legal AM is free.
1294 if (isLegalAddressingMode(AM, Ty)) return 0;
1298 /// Return true if the specified immediate is legal icmp immediate, that is
1299 /// the target has icmp instructions which can compare a register against the
1300 /// immediate without having to materialize the immediate into a register.
1301 virtual bool isLegalICmpImmediate(int64_t) const {
1305 /// Return true if the specified immediate is legal add immediate, that is the
1306 /// target has add instructions which can add a register with the immediate
1307 /// without having to materialize the immediate into a register.
1308 virtual bool isLegalAddImmediate(int64_t) const {
1312 /// Return true if it's significantly cheaper to shift a vector by a uniform
1313 /// scalar than by an amount which will vary across each lane. On x86, for
1314 /// example, there is a "psllw" instruction for the former case, but no simple
1315 /// instruction for a general "a << b" operation on vectors.
1316 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1320 /// Return true if it's free to truncate a value of type Ty1 to type
1321 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1322 /// by referencing its sub-register AX.
1323 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1327 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding
1328 /// whether a call is in tail position. Typically this means that both results
1329 /// would be assigned to the same register or stack slot, but it could mean
1330 /// the target performs adequate checks of its own before proceeding with the
1332 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const {
1336 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1340 /// Return true if any actual instruction that defines a value of type Ty1
1341 /// implicitly zero-extends the value to Ty2 in the result register.
1343 /// This does not necessarily include registers defined in unknown ways, such
1344 /// as incoming arguments, or copies from unknown virtual registers. Also, if
1345 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
1346 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit
1347 /// values implicit zero-extend the result out to 64 bits.
1348 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1352 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1356 /// Return true if the target supplies and combines to a paired load
1357 /// two loaded values of type LoadedType next to each other in memory.
1358 /// RequiredAlignment gives the minimal alignment constraints that must be met
1359 /// to be able to select this paired load.
1361 /// This information is *not* used to generate actual paired loads, but it is
1362 /// used to generate a sequence of loads that is easier to combine into a
1364 /// For instance, something like this:
1365 /// a = load i64* addr
1366 /// b = trunc i64 a to i32
1367 /// c = lshr i64 a, 32
1368 /// d = trunc i64 c to i32
1369 /// will be optimized into:
1370 /// b = load i32* addr1
1371 /// d = load i32* addr2
1372 /// Where addr1 = addr2 +/- sizeof(i32).
1374 /// In other words, unless the target performs a post-isel load combining,
1375 /// this information should not be provided because it will generate more
1377 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1378 unsigned & /*RequiredAligment*/) const {
1382 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1383 unsigned & /*RequiredAligment*/) const {
1387 /// Return true if zero-extending the specific node Val to type VT2 is free
1388 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1389 /// because it's folded such as X86 zero-extending loads).
1390 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1391 return isZExtFree(Val.getValueType(), VT2);
1394 /// Return true if an fneg operation is free to the point where it is never
1395 /// worthwhile to replace it with a bitwise operation.
1396 virtual bool isFNegFree(EVT VT) const {
1397 assert(VT.isFloatingPoint());
1401 /// Return true if an fabs operation is free to the point where it is never
1402 /// worthwhile to replace it with a bitwise operation.
1403 virtual bool isFAbsFree(EVT VT) const {
1404 assert(VT.isFloatingPoint());
1408 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1409 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1410 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1412 /// NOTE: This may be called before legalization on types for which FMAs are
1413 /// not legal, but should return true if those types will eventually legalize
1414 /// to types that support FMAs. After legalization, it will only be called on
1415 /// types that support FMAs (via Legal or Custom actions)
1416 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1420 /// Return true if it's profitable to narrow operations of type VT1 to
1421 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1423 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1427 /// \brief Return true if it is beneficial to convert a load of a constant to
1428 /// just the constant itself.
1429 /// On some targets it might be more efficient to use a combination of
1430 /// arithmetic instructions to materialize the constant instead of loading it
1431 /// from a constant pool.
1432 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1436 //===--------------------------------------------------------------------===//
1437 // Runtime Library hooks
1440 /// Rename the default libcall routine name for the specified libcall.
1441 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1442 LibcallRoutineNames[Call] = Name;
1445 /// Get the libcall routine name for the specified libcall.
1446 const char *getLibcallName(RTLIB::Libcall Call) const {
1447 return LibcallRoutineNames[Call];
1450 /// Override the default CondCode to be used to test the result of the
1451 /// comparison libcall against zero.
1452 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1453 CmpLibcallCCs[Call] = CC;
1456 /// Get the CondCode that's to be used to test the result of the comparison
1457 /// libcall against zero.
1458 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1459 return CmpLibcallCCs[Call];
1462 /// Set the CallingConv that should be used for the specified libcall.
1463 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1464 LibcallCallingConvs[Call] = CC;
1467 /// Get the CallingConv that should be used for the specified libcall.
1468 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1469 return LibcallCallingConvs[Call];
1473 const TargetMachine &TM;
1474 const DataLayout *DL;
1475 const TargetLoweringObjectFile &TLOF;
1477 /// True if this is a little endian target.
1478 bool IsLittleEndian;
1480 /// Tells the code generator not to expand operations into sequences that use
1481 /// the select operations if possible.
1482 bool SelectIsExpensive;
1484 /// Tells the code generator that the target has multiple (allocatable)
1485 /// condition registers that can be used to store the results of comparisons
1486 /// for use by selects and conditional branches. With multiple condition
1487 /// registers, the code generator will not aggressively sink comparisons into
1488 /// the blocks of their users.
1489 bool HasMultipleConditionRegisters;
1491 /// Tells the code generator that the target has BitExtract instructions.
1492 /// The code generator will aggressively sink "shift"s into the blocks of
1493 /// their users if the users will generate "and" instructions which can be
1494 /// combined with "shift" to BitExtract instructions.
1495 bool HasExtractBitsInsn;
1497 /// Tells the code generator not to expand integer divides by constants into a
1498 /// sequence of muls, adds, and shifts. This is a hack until a real cost
1499 /// model is in place. If we ever optimize for size, this will be set to true
1500 /// unconditionally.
1503 /// Tells the code generator to bypass slow divide or remainder
1504 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1505 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1506 /// div/rem when the operands are positive and less than 256.
1507 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1509 /// Tells the code generator that it shouldn't generate srl/add/sra for a
1510 /// signed divide by power of two, and let the target handle it.
1511 bool Pow2DivIsCheap;
1513 /// Tells the code generator that it shouldn't generate extra flow control
1514 /// instructions and should attempt to combine flow control instructions via
1516 bool JumpIsExpensive;
1518 /// Whether the target supports or cares about preserving floating point
1519 /// exception behavior.
1520 bool HasFloatingPointExceptions;
1522 /// This target prefers to use _setjmp to implement llvm.setjmp.
1524 /// Defaults to false.
1525 bool UseUnderscoreSetJmp;
1527 /// This target prefers to use _longjmp to implement llvm.longjmp.
1529 /// Defaults to false.
1530 bool UseUnderscoreLongJmp;
1532 /// Whether the target can generate code for jumptables. If it's not true,
1533 /// then each jumptable must be lowered into if-then-else's.
1534 bool SupportJumpTables;
1536 /// Number of blocks threshold to use jump tables.
1537 int MinimumJumpTableEntries;
1539 /// Information about the contents of the high-bits in boolean values held in
1540 /// a type wider than i1. See getBooleanContents.
1541 BooleanContent BooleanContents;
1543 /// Information about the contents of the high-bits in boolean values held in
1544 /// a type wider than i1. See getBooleanContents.
1545 BooleanContent BooleanFloatContents;
1547 /// Information about the contents of the high-bits in boolean vector values
1548 /// when the element type is wider than i1. See getBooleanContents.
1549 BooleanContent BooleanVectorContents;
1551 /// The target scheduling preference: shortest possible total cycles or lowest
1553 Sched::Preference SchedPreferenceInfo;
1555 /// The size, in bytes, of the target's jmp_buf buffers
1556 unsigned JumpBufSize;
1558 /// The alignment, in bytes, of the target's jmp_buf buffers
1559 unsigned JumpBufAlignment;
1561 /// The minimum alignment that any argument on the stack needs to have.
1562 unsigned MinStackArgumentAlignment;
1564 /// The minimum function alignment (used when optimizing for size, and to
1565 /// prevent explicitly provided alignment from leading to incorrect code).
1566 unsigned MinFunctionAlignment;
1568 /// The preferred function alignment (used when alignment unspecified and
1569 /// optimizing for speed).
1570 unsigned PrefFunctionAlignment;
1572 /// The preferred loop alignment.
1573 unsigned PrefLoopAlignment;
1575 /// Whether the DAG builder should automatically insert fences and reduce
1576 /// ordering for atomics. (This will be set for for most architectures with
1577 /// weak memory ordering.)
1578 bool InsertFencesForAtomic;
1580 /// If set to a physical register, this specifies the register that
1581 /// llvm.savestack/llvm.restorestack should save and restore.
1582 unsigned StackPointerRegisterToSaveRestore;
1584 /// If set to a physical register, this specifies the register that receives
1585 /// the exception address on entry to a landing pad.
1586 unsigned ExceptionPointerRegister;
1588 /// If set to a physical register, this specifies the register that receives
1589 /// the exception typeid on entry to a landing pad.
1590 unsigned ExceptionSelectorRegister;
1592 /// This indicates the default register class to use for each ValueType the
1593 /// target supports natively.
1594 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1595 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1596 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1598 /// This indicates the "representative" register class to use for each
1599 /// ValueType the target supports natively. This information is used by the
1600 /// scheduler to track register pressure. By default, the representative
1601 /// register class is the largest legal super-reg register class of the
1602 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1603 /// representative class would be GR32.
1604 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1606 /// This indicates the "cost" of the "representative" register class for each
1607 /// ValueType. The cost is used by the scheduler to approximate register
1609 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1611 /// For any value types we are promoting or expanding, this contains the value
1612 /// type that we are changing to. For Expanded types, this contains one step
1613 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1614 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1615 /// the same type (e.g. i32 -> i32).
1616 MVT TransformToType[MVT::LAST_VALUETYPE];
1618 /// For each operation and each value type, keep a LegalizeAction that
1619 /// indicates how instruction selection should deal with the operation. Most
1620 /// operations are Legal (aka, supported natively by the target), but
1621 /// operations that are not should be described. Note that operations on
1622 /// non-legal value types are not described here.
1623 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1625 /// For each load extension type and each value type, keep a LegalizeAction
1626 /// that indicates how instruction selection should deal with a load of a
1627 /// specific value type and extension type.
1628 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1630 /// For each value type pair keep a LegalizeAction that indicates whether a
1631 /// truncating store of a specific value type and truncating type is legal.
1632 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1634 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1635 /// that indicates how instruction selection should deal with the load /
1638 /// The first dimension is the value_type for the reference. The second
1639 /// dimension represents the various modes for load store.
1640 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1642 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1643 /// indicates how instruction selection should deal with the condition code.
1645 /// Because each CC action takes up 2 bits, we need to have the array size be
1646 /// large enough to fit all of the value types. This can be done by rounding
1647 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1648 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1650 ValueTypeActionImpl ValueTypeActions;
1654 getTypeConversion(LLVMContext &Context, EVT VT) const {
1655 // If this is a simple type, use the ComputeRegisterProp mechanism.
1656 if (VT.isSimple()) {
1657 MVT SVT = VT.getSimpleVT();
1658 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1659 MVT NVT = TransformToType[SVT.SimpleTy];
1660 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1663 (LA == TypeLegal || LA == TypeSoftenFloat ||
1664 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)
1665 && "Promote may not follow Expand or Promote");
1667 if (LA == TypeSplitVector)
1668 return LegalizeKind(LA, EVT::getVectorVT(Context,
1669 SVT.getVectorElementType(),
1670 SVT.getVectorNumElements()/2));
1671 if (LA == TypeScalarizeVector)
1672 return LegalizeKind(LA, SVT.getVectorElementType());
1673 return LegalizeKind(LA, NVT);
1676 // Handle Extended Scalar Types.
1677 if (!VT.isVector()) {
1678 assert(VT.isInteger() && "Float types must be simple");
1679 unsigned BitSize = VT.getSizeInBits();
1680 // First promote to a power-of-two size, then expand if necessary.
1681 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1682 EVT NVT = VT.getRoundIntegerType(Context);
1683 assert(NVT != VT && "Unable to round integer VT");
1684 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1685 // Avoid multi-step promotion.
1686 if (NextStep.first == TypePromoteInteger) return NextStep;
1687 // Return rounded integer type.
1688 return LegalizeKind(TypePromoteInteger, NVT);
1691 return LegalizeKind(TypeExpandInteger,
1692 EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
1695 // Handle vector types.
1696 unsigned NumElts = VT.getVectorNumElements();
1697 EVT EltVT = VT.getVectorElementType();
1699 // Vectors with only one element are always scalarized.
1701 return LegalizeKind(TypeScalarizeVector, EltVT);
1703 // Try to widen vector elements until the element type is a power of two and
1704 // promote it to a legal type later on, for example:
1705 // <3 x i8> -> <4 x i8> -> <4 x i32>
1706 if (EltVT.isInteger()) {
1707 // Vectors with a number of elements that is not a power of two are always
1708 // widened, for example <3 x i8> -> <4 x i8>.
1709 if (!VT.isPow2VectorType()) {
1710 NumElts = (unsigned)NextPowerOf2(NumElts);
1711 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1712 return LegalizeKind(TypeWidenVector, NVT);
1715 // Examine the element type.
1716 LegalizeKind LK = getTypeConversion(Context, EltVT);
1718 // If type is to be expanded, split the vector.
1719 // <4 x i140> -> <2 x i140>
1720 if (LK.first == TypeExpandInteger)
1721 return LegalizeKind(TypeSplitVector,
1722 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1724 // Promote the integer element types until a legal vector type is found
1725 // or until the element integer type is too big. If a legal type was not
1726 // found, fallback to the usual mechanism of widening/splitting the
1728 EVT OldEltVT = EltVT;
1730 // Increase the bitwidth of the element to the next pow-of-two
1731 // (which is greater than 8 bits).
1732 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
1733 ).getRoundIntegerType(Context);
1735 // Stop trying when getting a non-simple element type.
1736 // Note that vector elements may be greater than legal vector element
1737 // types. Example: X86 XMM registers hold 64bit element on 32bit
1739 if (!EltVT.isSimple()) break;
1741 // Build a new vector type and check if it is legal.
1742 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1743 // Found a legal promoted vector type.
1744 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1745 return LegalizeKind(TypePromoteInteger,
1746 EVT::getVectorVT(Context, EltVT, NumElts));
1749 // Reset the type to the unexpanded type if we did not find a legal vector
1750 // type with a promoted vector element type.
1754 // Try to widen the vector until a legal type is found.
1755 // If there is no wider legal type, split the vector.
1757 // Round up to the next power of 2.
1758 NumElts = (unsigned)NextPowerOf2(NumElts);
1760 // If there is no simple vector type with this many elements then there
1761 // cannot be a larger legal vector type. Note that this assumes that
1762 // there are no skipped intermediate vector types in the simple types.
1763 if (!EltVT.isSimple()) break;
1764 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1765 if (LargerVector == MVT()) break;
1767 // If this type is legal then widen the vector.
1768 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1769 return LegalizeKind(TypeWidenVector, LargerVector);
1772 // Widen odd vectors to next power of two.
1773 if (!VT.isPow2VectorType()) {
1774 EVT NVT = VT.getPow2VectorType(Context);
1775 return LegalizeKind(TypeWidenVector, NVT);
1778 // Vectors with illegal element types are expanded.
1779 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1780 return LegalizeKind(TypeSplitVector, NVT);
1784 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1786 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1787 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1790 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1792 /// For operations that must be promoted to a specific type, this holds the
1793 /// destination type. This map should be sparse, so don't hold it as an
1796 /// Targets add entries to this map with AddPromotedToType(..), clients access
1797 /// this with getTypeToPromoteTo(..).
1798 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1801 /// Stores the name each libcall.
1802 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1804 /// The ISD::CondCode that should be used to test the result of each of the
1805 /// comparison libcall against zero.
1806 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1808 /// Stores the CallingConv that should be used for each libcall.
1809 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1812 /// \brief Specify maximum number of store instructions per memset call.
1814 /// When lowering \@llvm.memset this field specifies the maximum number of
1815 /// store operations that may be substituted for the call to memset. Targets
1816 /// must set this value based on the cost threshold for that target. Targets
1817 /// should assume that the memset will be done using as many of the largest
1818 /// store operations first, followed by smaller ones, if necessary, per
1819 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1820 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1821 /// store. This only applies to setting a constant array of a constant size.
1822 unsigned MaxStoresPerMemset;
1824 /// Maximum number of stores operations that may be substituted for the call
1825 /// to memset, used for functions with OptSize attribute.
1826 unsigned MaxStoresPerMemsetOptSize;
1828 /// \brief Specify maximum bytes of store instructions per memcpy call.
1830 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1831 /// store operations that may be substituted for a call to memcpy. Targets
1832 /// must set this value based on the cost threshold for that target. Targets
1833 /// should assume that the memcpy will be done using as many of the largest
1834 /// store operations first, followed by smaller ones, if necessary, per
1835 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1836 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1837 /// and one 1-byte store. This only applies to copying a constant array of
1839 unsigned MaxStoresPerMemcpy;
1841 /// Maximum number of store operations that may be substituted for a call to
1842 /// memcpy, used for functions with OptSize attribute.
1843 unsigned MaxStoresPerMemcpyOptSize;
1845 /// \brief Specify maximum bytes of store instructions per memmove call.
1847 /// When lowering \@llvm.memmove this field specifies the maximum number of
1848 /// store instructions that may be substituted for a call to memmove. Targets
1849 /// must set this value based on the cost threshold for that target. Targets
1850 /// should assume that the memmove will be done using as many of the largest
1851 /// store operations first, followed by smaller ones, if necessary, per
1852 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1853 /// with 8-bit alignment would result in nine 1-byte stores. This only
1854 /// applies to copying a constant array of constant size.
1855 unsigned MaxStoresPerMemmove;
1857 /// Maximum number of store instructions that may be substituted for a call to
1858 /// memmove, used for functions with OpSize attribute.
1859 unsigned MaxStoresPerMemmoveOptSize;
1861 /// Tells the code generator that select is more expensive than a branch if
1862 /// the branch is usually predicted right.
1863 bool PredictableSelectIsExpensive;
1865 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
1866 /// a mask of a single bit, a compare, and a branch into a single instruction.
1867 bool MaskAndBranchFoldingIsLegal;
1870 /// Return true if the value types that can be represented by the specified
1871 /// register class are all legal.
1872 bool isLegalRC(const TargetRegisterClass *RC) const;
1874 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1875 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1876 MachineBasicBlock *emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const;
1879 /// This class defines information used to lower LLVM code to legal SelectionDAG
1880 /// operators that the target instruction selector can accept natively.
1882 /// This class also defines callbacks that targets must implement to lower
1883 /// target-specific constructs to SelectionDAG operators.
1884 class TargetLowering : public TargetLoweringBase {
1885 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
1886 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
1889 /// NOTE: The constructor takes ownership of TLOF.
1890 explicit TargetLowering(const TargetMachine &TM,
1891 const TargetLoweringObjectFile *TLOF);
1893 /// Returns true by value, base pointer and offset pointer and addressing mode
1894 /// by reference if the node's address can be legally represented as
1895 /// pre-indexed load / store address.
1896 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
1897 SDValue &/*Offset*/,
1898 ISD::MemIndexedMode &/*AM*/,
1899 SelectionDAG &/*DAG*/) const {
1903 /// Returns true by value, base pointer and offset pointer and addressing mode
1904 /// by reference if this node can be combined with a load / store to form a
1905 /// post-indexed load / store.
1906 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
1908 SDValue &/*Offset*/,
1909 ISD::MemIndexedMode &/*AM*/,
1910 SelectionDAG &/*DAG*/) const {
1914 /// Return the entry encoding for a jump table in the current function. The
1915 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
1916 virtual unsigned getJumpTableEncoding() const;
1918 virtual const MCExpr *
1919 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
1920 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
1921 MCContext &/*Ctx*/) const {
1922 llvm_unreachable("Need to implement this hook if target has custom JTIs");
1925 /// Returns relocation base for the given PIC jumptable.
1926 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
1927 SelectionDAG &DAG) const;
1929 /// This returns the relocation base for the given PIC jumptable, the same as
1930 /// getPICJumpTableRelocBase, but as an MCExpr.
1931 virtual const MCExpr *
1932 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1933 unsigned JTI, MCContext &Ctx) const;
1935 /// Return true if folding a constant offset with the given GlobalAddress is
1936 /// legal. It is frequently not legal in PIC relocation models.
1937 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
1939 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
1940 SDValue &Chain) const;
1942 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
1943 SDValue &NewLHS, SDValue &NewRHS,
1944 ISD::CondCode &CCCode, SDLoc DL) const;
1946 /// Returns a pair of (return value, chain).
1947 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
1948 EVT RetVT, const SDValue *Ops,
1949 unsigned NumOps, bool isSigned,
1950 SDLoc dl, bool doesNotReturn = false,
1951 bool isReturnValueUsed = true) const;
1953 //===--------------------------------------------------------------------===//
1954 // TargetLowering Optimization Methods
1957 /// A convenience struct that encapsulates a DAG, and two SDValues for
1958 /// returning information from TargetLowering to its clients that want to
1960 struct TargetLoweringOpt {
1967 explicit TargetLoweringOpt(SelectionDAG &InDAG,
1969 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
1971 bool LegalTypes() const { return LegalTys; }
1972 bool LegalOperations() const { return LegalOps; }
1974 bool CombineTo(SDValue O, SDValue N) {
1980 /// Check to see if the specified operand of the specified instruction is a
1981 /// constant integer. If so, check to see if there are any bits set in the
1982 /// constant that are not demanded. If so, shrink the constant and return
1984 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
1986 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
1987 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
1988 /// generalized for targets with other types of implicit widening casts.
1989 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
1993 /// Look at Op. At this point, we know that only the DemandedMask bits of the
1994 /// result of Op are ever used downstream. If we can use this information to
1995 /// simplify Op, create a new simplified DAG node and return true, returning
1996 /// the original and new nodes in Old and New. Otherwise, analyze the
1997 /// expression and return a mask of KnownOne and KnownZero bits for the
1998 /// expression (used to simplify the caller). The KnownZero/One bits may only
1999 /// be accurate for those bits in the DemandedMask.
2000 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2001 APInt &KnownZero, APInt &KnownOne,
2002 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2004 /// Determine which of the bits specified in Mask are known to be either zero
2005 /// or one and return them in the KnownZero/KnownOne bitsets.
2006 virtual void computeKnownBitsForTargetNode(const SDValue Op,
2009 const SelectionDAG &DAG,
2010 unsigned Depth = 0) const;
2012 /// This method can be implemented by targets that want to expose additional
2013 /// information about sign bits to the DAG Combiner.
2014 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2015 const SelectionDAG &DAG,
2016 unsigned Depth = 0) const;
2018 struct DAGCombinerInfo {
2019 void *DC; // The DAG Combiner object.
2021 bool CalledByLegalizer;
2025 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2026 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2028 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2029 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2030 bool isAfterLegalizeVectorOps() const {
2031 return Level == AfterLegalizeDAG;
2033 CombineLevel getDAGCombineLevel() { return Level; }
2034 bool isCalledByLegalizer() const { return CalledByLegalizer; }
2036 void AddToWorklist(SDNode *N);
2037 void RemoveFromWorklist(SDNode *N);
2038 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
2040 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2041 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2043 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2046 /// Return if the N is a constant or constant vector equal to the true value
2047 /// from getBooleanContents().
2048 bool isConstTrueVal(const SDNode *N) const;
2050 /// Return if the N is a constant or constant vector equal to the false value
2051 /// from getBooleanContents().
2052 bool isConstFalseVal(const SDNode *N) const;
2054 /// Try to simplify a setcc built with the specified operands and cc. If it is
2055 /// unable to simplify it, return a null SDValue.
2056 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2057 ISD::CondCode Cond, bool foldBooleans,
2058 DAGCombinerInfo &DCI, SDLoc dl) const;
2060 /// Returns true (and the GlobalValue and the offset) if the node is a
2061 /// GlobalAddress + offset.
2063 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2065 /// This method will be invoked for all target nodes and for any
2066 /// target-independent nodes that the target has registered with invoke it
2069 /// The semantics are as follows:
2071 /// SDValue.Val == 0 - No change was made
2072 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2073 /// otherwise - N should be replaced by the returned Operand.
2075 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2076 /// more complex transformations.
2078 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2080 /// Return true if it is profitable to move a following shift through this
2081 // node, adjusting any immediate operands as necessary to preserve semantics.
2082 // This transformation may not be desirable if it disrupts a particularly
2083 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2084 // By default, it returns true.
2085 virtual bool isDesirableToCommuteWithShift(const SDNode *N /*Op*/) const {
2089 /// Return true if the target has native support for the specified value type
2090 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2091 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2092 /// and some i16 instructions are slow.
2093 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2094 // By default, assume all legal types are desirable.
2095 return isTypeLegal(VT);
2098 /// Return true if it is profitable for dag combiner to transform a floating
2099 /// point op of specified opcode to a equivalent op of an integer
2100 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2101 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2106 /// This method query the target whether it is beneficial for dag combiner to
2107 /// promote the specified node. If true, it should return the desired
2108 /// promotion type by reference.
2109 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2113 //===--------------------------------------------------------------------===//
2114 // Lowering methods - These methods must be implemented by targets so that
2115 // the SelectionDAGBuilder code knows how to lower these.
2118 /// This hook must be implemented to lower the incoming (formal) arguments,
2119 /// described by the Ins array, into the specified DAG. The implementation
2120 /// should fill in the InVals array with legal-type argument values, and
2121 /// return the resulting token chain value.
2124 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2126 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
2127 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
2128 SmallVectorImpl<SDValue> &/*InVals*/) const {
2129 llvm_unreachable("Not Implemented");
2132 struct ArgListEntry {
2141 bool isInAlloca : 1;
2142 bool isReturned : 1;
2145 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2146 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2147 isReturned(false), Alignment(0) { }
2149 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2151 typedef std::vector<ArgListEntry> ArgListTy;
2153 /// This structure contains all information that is necessary for lowering
2154 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2155 /// needs to lower a call, and targets will see this struct in their LowerCall
2157 struct CallLoweringInfo {
2164 bool DoesNotReturn : 1;
2165 bool IsReturnValueUsed : 1;
2167 // IsTailCall should be modified by implementations of
2168 // TargetLowering::LowerCall that perform tail call conversions.
2171 unsigned NumFixedArgs;
2172 CallingConv::ID CallConv;
2177 ImmutableCallSite *CS;
2178 SmallVector<ISD::OutputArg, 32> Outs;
2179 SmallVector<SDValue, 32> OutVals;
2180 SmallVector<ISD::InputArg, 32> Ins;
2182 CallLoweringInfo(SelectionDAG &DAG)
2183 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
2184 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
2185 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
2186 DAG(DAG), CS(nullptr) {}
2188 CallLoweringInfo &setDebugLoc(SDLoc dl) {
2193 CallLoweringInfo &setChain(SDValue InChain) {
2198 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
2199 SDValue Target, ArgListTy &&ArgsList,
2200 unsigned FixedArgs = -1) {
2205 (FixedArgs == static_cast<unsigned>(-1) ? Args.size() : FixedArgs);
2206 Args = std::move(ArgsList);
2210 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
2211 SDValue Target, ArgListTy &&ArgsList,
2212 ImmutableCallSite &Call) {
2215 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
2216 DoesNotReturn = Call.doesNotReturn();
2217 IsVarArg = FTy->isVarArg();
2218 IsReturnValueUsed = !Call.getInstruction()->use_empty();
2219 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
2220 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
2224 CallConv = Call.getCallingConv();
2225 NumFixedArgs = FTy->getNumParams();
2226 Args = std::move(ArgsList);
2233 CallLoweringInfo &setInRegister(bool Value = true) {
2238 CallLoweringInfo &setNoReturn(bool Value = true) {
2239 DoesNotReturn = Value;
2243 CallLoweringInfo &setVarArg(bool Value = true) {
2248 CallLoweringInfo &setTailCall(bool Value = true) {
2253 CallLoweringInfo &setDiscardResult(bool Value = true) {
2254 IsReturnValueUsed = !Value;
2258 CallLoweringInfo &setSExtResult(bool Value = true) {
2263 CallLoweringInfo &setZExtResult(bool Value = true) {
2268 ArgListTy &getArgs() {
2273 /// This function lowers an abstract call to a function into an actual call.
2274 /// This returns a pair of operands. The first element is the return value
2275 /// for the function (if RetTy is not VoidTy). The second element is the
2276 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2277 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2279 /// This hook must be implemented to lower calls into the the specified
2280 /// DAG. The outgoing arguments to the call are described by the Outs array,
2281 /// and the values to be returned by the call are described by the Ins
2282 /// array. The implementation should fill in the InVals array with legal-type
2283 /// return values from the call, and return the resulting token chain value.
2285 LowerCall(CallLoweringInfo &/*CLI*/,
2286 SmallVectorImpl<SDValue> &/*InVals*/) const {
2287 llvm_unreachable("Not Implemented");
2290 /// Target-specific cleanup for formal ByVal parameters.
2291 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2293 /// This hook should be implemented to check whether the return values
2294 /// described by the Outs array can fit into the return registers. If false
2295 /// is returned, an sret-demotion is performed.
2296 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2297 MachineFunction &/*MF*/, bool /*isVarArg*/,
2298 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2299 LLVMContext &/*Context*/) const
2301 // Return true by default to get preexisting behavior.
2305 /// This hook must be implemented to lower outgoing return values, described
2306 /// by the Outs array, into the specified DAG. The implementation should
2307 /// return the resulting token chain value.
2309 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2311 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2312 const SmallVectorImpl<SDValue> &/*OutVals*/,
2313 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2314 llvm_unreachable("Not Implemented");
2317 /// Return true if result of the specified node is used by a return node
2318 /// only. It also compute and return the input chain for the tail call.
2320 /// This is used to determine whether it is possible to codegen a libcall as
2321 /// tail call at legalization time.
2322 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2326 /// Return true if the target may be able emit the call instruction as a tail
2327 /// call. This is used by optimization passes to determine if it's profitable
2328 /// to duplicate return instructions to enable tailcall optimization.
2329 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2333 /// Return the builtin name for the __builtin___clear_cache intrinsic
2334 /// Default is to invoke the clear cache library call
2335 virtual const char * getClearCacheBuiltinName() const {
2336 return "__clear_cache";
2339 /// Return the register ID of the name passed in. Used by named register
2340 /// global variables extension. There is no target-independent behaviour
2341 /// so the default action is to bail.
2342 virtual unsigned getRegisterByName(const char* RegName, EVT VT) const {
2343 report_fatal_error("Named registers not implemented for this target");
2346 /// Return the type that should be used to zero or sign extend a
2347 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2348 /// convention requires the return type to be promoted, but this is not true
2349 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2350 /// calling conventions. The frontend should handle this and include all of
2351 /// the necessary information.
2352 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2353 ISD::NodeType /*ExtendKind*/) const {
2354 EVT MinVT = getRegisterType(Context, MVT::i32);
2355 return VT.bitsLT(MinVT) ? MinVT : VT;
2358 /// For some targets, an LLVM struct type must be broken down into multiple
2359 /// simple types, but the calling convention specifies that the entire struct
2360 /// must be passed in a block of consecutive registers.
2362 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
2363 bool isVarArg) const {
2367 /// Returns a 0 terminated array of registers that can be safely used as
2368 /// scratch registers.
2369 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
2373 /// This callback is used to prepare for a volatile or atomic load.
2374 /// It takes a chain node as input and returns the chain for the load itself.
2376 /// Having a callback like this is necessary for targets like SystemZ,
2377 /// which allows a CPU to reuse the result of a previous load indefinitely,
2378 /// even if a cache-coherent store is performed by another CPU. The default
2379 /// implementation does nothing.
2380 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2381 SelectionDAG &DAG) const {
2385 /// This callback is invoked by the type legalizer to legalize nodes with an
2386 /// illegal operand type but legal result types. It replaces the
2387 /// LowerOperation callback in the type Legalizer. The reason we can not do
2388 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2389 /// use this callback.
2391 /// TODO: Consider merging with ReplaceNodeResults.
2393 /// The target places new result values for the node in Results (their number
2394 /// and types must exactly match those of the original return values of
2395 /// the node), or leaves Results empty, which indicates that the node is not
2396 /// to be custom lowered after all.
2397 /// The default implementation calls LowerOperation.
2398 virtual void LowerOperationWrapper(SDNode *N,
2399 SmallVectorImpl<SDValue> &Results,
2400 SelectionDAG &DAG) const;
2402 /// This callback is invoked for operations that are unsupported by the
2403 /// target, which are registered to use 'custom' lowering, and whose defined
2404 /// values are all legal. If the target has no operations that require custom
2405 /// lowering, it need not implement this. The default implementation of this
2407 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2409 /// This callback is invoked when a node result type is illegal for the
2410 /// target, and the operation was registered to use 'custom' lowering for that
2411 /// result type. The target places new result values for the node in Results
2412 /// (their number and types must exactly match those of the original return
2413 /// values of the node), or leaves Results empty, which indicates that the
2414 /// node is not to be custom lowered after all.
2416 /// If the target has no operations that require custom lowering, it need not
2417 /// implement this. The default implementation aborts.
2418 virtual void ReplaceNodeResults(SDNode * /*N*/,
2419 SmallVectorImpl<SDValue> &/*Results*/,
2420 SelectionDAG &/*DAG*/) const {
2421 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2424 /// This method returns the name of a target specific DAG node.
2425 virtual const char *getTargetNodeName(unsigned Opcode) const;
2427 /// This method returns a target specific FastISel object, or null if the
2428 /// target does not support "fast" ISel.
2429 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2430 const TargetLibraryInfo *) const {
2435 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2436 SelectionDAG &DAG) const;
2438 //===--------------------------------------------------------------------===//
2439 // Inline Asm Support hooks
2442 /// This hook allows the target to expand an inline asm call to be explicit
2443 /// llvm code if it wants to. This is useful for turning simple inline asms
2444 /// into LLVM intrinsics, which gives the compiler more information about the
2445 /// behavior of the code.
2446 virtual bool ExpandInlineAsm(CallInst *) const {
2450 enum ConstraintType {
2451 C_Register, // Constraint represents specific register(s).
2452 C_RegisterClass, // Constraint represents any of register(s) in class.
2453 C_Memory, // Memory constraint.
2454 C_Other, // Something else.
2455 C_Unknown // Unsupported constraint.
2458 enum ConstraintWeight {
2460 CW_Invalid = -1, // No match.
2461 CW_Okay = 0, // Acceptable.
2462 CW_Good = 1, // Good weight.
2463 CW_Better = 2, // Better weight.
2464 CW_Best = 3, // Best weight.
2466 // Well-known weights.
2467 CW_SpecificReg = CW_Okay, // Specific register operands.
2468 CW_Register = CW_Good, // Register operands.
2469 CW_Memory = CW_Better, // Memory operands.
2470 CW_Constant = CW_Best, // Constant operand.
2471 CW_Default = CW_Okay // Default or don't know type.
2474 /// This contains information for each constraint that we are lowering.
2475 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2476 /// This contains the actual string for the code, like "m". TargetLowering
2477 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2478 /// matches the operand.
2479 std::string ConstraintCode;
2481 /// Information about the constraint code, e.g. Register, RegisterClass,
2482 /// Memory, Other, Unknown.
2483 TargetLowering::ConstraintType ConstraintType;
2485 /// If this is the result output operand or a clobber, this is null,
2486 /// otherwise it is the incoming operand to the CallInst. This gets
2487 /// modified as the asm is processed.
2488 Value *CallOperandVal;
2490 /// The ValueType for the operand value.
2493 /// Return true of this is an input operand that is a matching constraint
2495 bool isMatchingInputConstraint() const;
2497 /// If this is an input matching constraint, this method returns the output
2498 /// operand it matches.
2499 unsigned getMatchedOperand() const;
2501 /// Copy constructor for copying from a ConstraintInfo.
2502 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
2503 : InlineAsm::ConstraintInfo(info),
2504 ConstraintType(TargetLowering::C_Unknown),
2505 CallOperandVal(nullptr), ConstraintVT(MVT::Other) {
2509 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2511 /// Split up the constraint string from the inline assembly value into the
2512 /// specific constraints and their prefixes, and also tie in the associated
2513 /// operand values. If this returns an empty vector, and if the constraint
2514 /// string itself isn't empty, there was an error parsing.
2515 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
2517 /// Examine constraint type and operand type and determine a weight value.
2518 /// The operand object must already have been set up with the operand type.
2519 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2520 AsmOperandInfo &info, int maIndex) const;
2522 /// Examine constraint string and operand type and determine a weight value.
2523 /// The operand object must already have been set up with the operand type.
2524 virtual ConstraintWeight getSingleConstraintMatchWeight(
2525 AsmOperandInfo &info, const char *constraint) const;
2527 /// Determines the constraint code and constraint type to use for the specific
2528 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2529 /// If the actual operand being passed in is available, it can be passed in as
2530 /// Op, otherwise an empty SDValue can be passed.
2531 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2533 SelectionDAG *DAG = nullptr) const;
2535 /// Given a constraint, return the type of constraint it is for this target.
2536 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
2538 /// Given a physical register constraint (e.g. {edx}), return the register
2539 /// number and the register class for the register.
2541 /// Given a register class constraint, like 'r', if this corresponds directly
2542 /// to an LLVM register class, return a register of 0 and the register class
2545 /// This should only be used for C_Register constraints. On error, this
2546 /// returns a register number of 0 and a null register class pointer..
2547 virtual std::pair<unsigned, const TargetRegisterClass*>
2548 getRegForInlineAsmConstraint(const std::string &Constraint,
2551 /// Try to replace an X constraint, which matches anything, with another that
2552 /// has more specific requirements based on the type of the corresponding
2553 /// operand. This returns null if there is no replacement to make.
2554 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2556 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2557 /// add anything to Ops.
2558 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2559 std::vector<SDValue> &Ops,
2560 SelectionDAG &DAG) const;
2562 //===--------------------------------------------------------------------===//
2563 // Div utility functions
2565 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2566 SelectionDAG &DAG) const;
2567 SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2568 bool IsAfterLegalization,
2569 std::vector<SDNode *> *Created) const;
2570 SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2571 bool IsAfterLegalization,
2572 std::vector<SDNode *> *Created) const;
2573 virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
2575 std::vector<SDNode *> *Created) const {
2579 //===--------------------------------------------------------------------===//
2580 // Legalization utility functions
2583 /// Expand a MUL into two nodes. One that computes the high bits of
2584 /// the result and one that computes the low bits.
2585 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
2586 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
2587 /// if you want to control how low bits are extracted from the LHS.
2588 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
2589 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
2590 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
2591 /// \returns true if the node has been expanded. false if it has not
2592 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2593 SelectionDAG &DAG, SDValue LL = SDValue(),
2594 SDValue LH = SDValue(), SDValue RL = SDValue(),
2595 SDValue RH = SDValue()) const;
2597 /// Expand float(f32) to SINT(i64) conversion
2598 /// \param N Node to expand
2599 /// \param Result output after conversion
2600 /// \returns True, if the expansion was successful, false otherwise
2601 bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
2603 //===--------------------------------------------------------------------===//
2604 // Instruction Emitting Hooks
2607 /// This method should be implemented by targets that mark instructions with
2608 /// the 'usesCustomInserter' flag. These instructions are special in various
2609 /// ways, which require special support to insert. The specified MachineInstr
2610 /// is created but not inserted into any basic blocks, and this method is
2611 /// called to expand it into a sequence of instructions, potentially also
2612 /// creating new basic blocks and control flow.
2613 virtual MachineBasicBlock *
2614 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2616 /// This method should be implemented by targets that mark instructions with
2617 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2618 /// instruction selection by target hooks. e.g. To fill in optional defs for
2619 /// ARM 's' setting instructions.
2621 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2623 /// If this function returns true, SelectionDAGBuilder emits a
2624 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
2625 virtual bool useLoadStackGuardNode() const {
2630 /// Given an LLVM IR type and return type attributes, compute the return value
2631 /// EVTs and flags, and optionally also the offsets, if the return value is
2632 /// being lowered to memory.
2633 void GetReturnInfo(Type* ReturnType, AttributeSet attr,
2634 SmallVectorImpl<ISD::OutputArg> &Outs,
2635 const TargetLowering &TLI);
2637 } // end llvm namespace