1 //===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==//
3 // This file describes the target machine instructions to the code generator.
5 //===---------------------------------------------------------------------===//
7 #ifndef LLVM_TARGET_MACHINEINSTRINFO_H
8 #define LLVM_TARGET_MACHINEINSTRINFO_H
10 #include "Support/DataTypes.h"
13 class MachineInstrDescriptor;
20 class MachineCodeForInstruction;
22 //---------------------------------------------------------------------------
23 // Data types used to define information about a single machine instruction
24 //---------------------------------------------------------------------------
26 typedef int MachineOpCode;
27 typedef unsigned InstrSchedClass;
29 const MachineOpCode INVALID_MACHINE_OPCODE = -1;
32 //---------------------------------------------------------------------------
33 // struct MachineInstrDescriptor:
34 // Predefined information about each machine instruction.
35 // Designed to initialized statically.
37 // class MachineInstructionInfo
38 // Interface to description of machine instructions
40 //---------------------------------------------------------------------------
42 const unsigned M_NOP_FLAG = 1 << 0;
43 const unsigned M_BRANCH_FLAG = 1 << 1;
44 const unsigned M_CALL_FLAG = 1 << 2;
45 const unsigned M_RET_FLAG = 1 << 3;
46 const unsigned M_ARITH_FLAG = 1 << 4;
47 const unsigned M_CC_FLAG = 1 << 6;
48 const unsigned M_LOGICAL_FLAG = 1 << 6;
49 const unsigned M_INT_FLAG = 1 << 7;
50 const unsigned M_FLOAT_FLAG = 1 << 8;
51 const unsigned M_CONDL_FLAG = 1 << 9;
52 const unsigned M_LOAD_FLAG = 1 << 10;
53 const unsigned M_PREFETCH_FLAG = 1 << 11;
54 const unsigned M_STORE_FLAG = 1 << 12;
55 const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
56 const unsigned M_PSEUDO_FLAG = 1 << 14;
59 struct MachineInstrDescriptor {
60 const char * Name; // Assembly language mnemonic for the opcode.
61 int numOperands; // Number of args; -1 if variable #args
62 int resultPos; // Position of the result; -1 if no result
63 unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0.
64 bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
65 // smallest -ve value is -(maxImmedConst+1).
66 unsigned numDelaySlots; // Number of delay slots after instruction
67 unsigned latency; // Latency in machine cycles
68 InstrSchedClass schedClass; // enum identifying instr sched class
69 unsigned Flags; // flags identifying machine instr class
70 unsigned TSFlags; // Target Specific Flag values
74 class MachineInstrInfo {
75 const MachineInstrDescriptor* desc; // raw array to allow static init'n
76 unsigned descSize; // number of entries in the desc array
77 unsigned numRealOpCodes; // number of non-dummy op codes
79 MachineInstrInfo(const MachineInstrInfo &); // DO NOT IMPLEMENT
80 void operator=(const MachineInstrInfo &); // DO NOT IMPLEMENT
82 MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize,
83 unsigned numRealOpCodes);
84 virtual ~MachineInstrInfo();
86 unsigned getNumRealOpCodes() const { return numRealOpCodes; }
87 unsigned getNumTotalOpCodes() const { return descSize; }
89 /// get - Return the machine instruction descriptor that corresponds to the
90 /// specified instruction opcode.
92 const MachineInstrDescriptor& get(MachineOpCode opCode) const {
93 assert(opCode >= 0 && opCode < (int)descSize);
97 /// print - Print out the specified machine instruction in the appropriate
98 /// target specific assembly language. If this method is not overridden, the
99 /// default implementation uses the crummy machine independant printer.
101 virtual void print(const MachineInstr *MI, std::ostream &O,
102 const TargetMachine &TM) const;
104 const char *getName(MachineOpCode opCode) const {
105 return get(opCode).Name;
108 int getNumOperands(MachineOpCode opCode) const {
109 return get(opCode).numOperands;
112 int getResultPos(MachineOpCode opCode) const {
113 return get(opCode).resultPos;
116 unsigned getNumDelaySlots(MachineOpCode opCode) const {
117 return get(opCode).numDelaySlots;
120 InstrSchedClass getSchedClass(MachineOpCode opCode) const {
121 return get(opCode).schedClass;
125 // Query instruction class flags according to the machine-independent
126 // flags listed above.
128 bool isNop(MachineOpCode opCode) const {
129 return get(opCode).Flags & M_NOP_FLAG;
131 bool isBranch(MachineOpCode opCode) const {
132 return get(opCode).Flags & M_BRANCH_FLAG;
134 bool isCall(MachineOpCode opCode) const {
135 return get(opCode).Flags & M_CALL_FLAG;
137 bool isReturn(MachineOpCode opCode) const {
138 return get(opCode).Flags & M_RET_FLAG;
140 bool isControlFlow(MachineOpCode opCode) const {
141 return get(opCode).Flags & M_BRANCH_FLAG
142 || get(opCode).Flags & M_CALL_FLAG
143 || get(opCode).Flags & M_RET_FLAG;
145 bool isArith(MachineOpCode opCode) const {
146 return get(opCode).Flags & M_ARITH_FLAG;
148 bool isCCInstr(MachineOpCode opCode) const {
149 return get(opCode).Flags & M_CC_FLAG;
151 bool isLogical(MachineOpCode opCode) const {
152 return get(opCode).Flags & M_LOGICAL_FLAG;
154 bool isIntInstr(MachineOpCode opCode) const {
155 return get(opCode).Flags & M_INT_FLAG;
157 bool isFloatInstr(MachineOpCode opCode) const {
158 return get(opCode).Flags & M_FLOAT_FLAG;
160 bool isConditional(MachineOpCode opCode) const {
161 return get(opCode).Flags & M_CONDL_FLAG;
163 bool isLoad(MachineOpCode opCode) const {
164 return get(opCode).Flags & M_LOAD_FLAG;
166 bool isPrefetch(MachineOpCode opCode) const {
167 return get(opCode).Flags & M_PREFETCH_FLAG;
169 bool isLoadOrPrefetch(MachineOpCode opCode) const {
170 return get(opCode).Flags & M_LOAD_FLAG
171 || get(opCode).Flags & M_PREFETCH_FLAG;
173 bool isStore(MachineOpCode opCode) const {
174 return get(opCode).Flags & M_STORE_FLAG;
176 bool isMemoryAccess(MachineOpCode opCode) const {
177 return get(opCode).Flags & M_LOAD_FLAG
178 || get(opCode).Flags & M_PREFETCH_FLAG
179 || get(opCode).Flags & M_STORE_FLAG;
181 bool isDummyPhiInstr(const MachineOpCode opCode) const {
182 return get(opCode).Flags & M_DUMMY_PHI_FLAG;
184 bool isPseudoInstr(const MachineOpCode opCode) const {
185 return get(opCode).Flags & M_PSEUDO_FLAG;
188 // Check if an instruction can be issued before its operands are ready,
189 // or if a subsequent instruction that uses its result can be issued
190 // before the results are ready.
191 // Default to true since most instructions on many architectures allow this.
193 virtual bool hasOperandInterlock(MachineOpCode opCode) const {
197 virtual bool hasResultInterlock(MachineOpCode opCode) const {
202 // Latencies for individual instructions and instruction pairs
204 virtual int minLatency(MachineOpCode opCode) const {
205 return get(opCode).latency;
208 virtual int maxLatency(MachineOpCode opCode) const {
209 return get(opCode).latency;
213 // Which operand holds an immediate constant? Returns -1 if none
215 virtual int getImmedConstantPos(MachineOpCode opCode) const {
216 return -1; // immediate position is machine specific, so say -1 == "none"
219 // Check if the specified constant fits in the immediate field
220 // of this machine instruction
222 virtual bool constantFitsInImmedField(MachineOpCode opCode,
223 int64_t intValue) const;
225 // Return the largest +ve constant that can be held in the IMMMED field
226 // of this machine instruction.
227 // isSignExtended is set to true if the value is sign-extended before use
228 // (this is true for all immediate fields in SPARC instructions).
229 // Return 0 if the instruction has no IMMED field.
231 virtual uint64_t maxImmedConstant(MachineOpCode opCode,
232 bool &isSignExtended) const {
233 isSignExtended = get(opCode).immedIsSignExtended;
234 return get(opCode).maxImmedConst;
237 //-------------------------------------------------------------------------
238 // Queries about representation of LLVM quantities (e.g., constants)
239 //-------------------------------------------------------------------------
241 /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded
242 /// from memory into a register, i.e., cannot be set bitwise in register and
243 /// cannot use immediate fields of instructions. Note that this only makes
244 /// sense for primitive types.
246 virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const;
248 // Test if this constant may not fit in the immediate field of the
249 // machine instructions (probably) generated for this instruction.
251 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
252 const Instruction* I) const {
253 return true; // safe but very conservative
256 //-------------------------------------------------------------------------
257 // Code generation support for creating individual machine instructions
258 //-------------------------------------------------------------------------
260 // Get certain common op codes for the current target. this and all the
261 // Create* methods below should be moved to a machine code generation class
263 virtual MachineOpCode getNOPOpCode() const = 0;
265 // Create an instruction sequence to put the constant `val' into
266 // the virtual register `dest'. `val' may be a Constant or a
267 // GlobalValue, viz., the constant address of a global variable or function.
268 // The generated instructions are returned in `mvec'.
269 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
270 // Symbolic constants or constants that must be accessed from memory
271 // are added to the constant pool via MachineFunction::get(F).
273 virtual void CreateCodeToLoadConst(const TargetMachine& target,
277 std::vector<MachineInstr*>& mvec,
278 MachineCodeForInstruction& mcfi) const=0;
280 // Create an instruction sequence to copy an integer value `val'
281 // to a floating point value `dest' by copying to memory and back.
282 // val must be an integral type. dest must be a Float or Double.
283 // The generated instructions are returned in `mvec'.
284 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
285 // Any stack space required is allocated via mcff.
287 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
291 std::vector<MachineInstr*>& mvec,
292 MachineCodeForInstruction& mcfi)const=0;
294 // Similarly, create an instruction sequence to copy an FP value
295 // `val' to an integer value `dest' by copying to memory and back.
296 // The generated instructions are returned in `mvec'.
297 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
298 // Any stack space required is allocated via mcff.
300 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
304 std::vector<MachineInstr*>& mvec,
305 MachineCodeForInstruction& mcfi)const=0;
307 // Create instruction(s) to copy src to dest, for arbitrary types
308 // The generated instructions are returned in `mvec'.
309 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
310 // Any stack space required is allocated via mcff.
312 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
316 std::vector<MachineInstr*>& mvec,
317 MachineCodeForInstruction& mcfi)const=0;
319 // Create instruction sequence to produce a sign-extended register value
320 // from an arbitrary sized value (sized in bits, not bytes).
321 // The generated instructions are appended to `mvec'.
322 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
323 // Any stack space required is allocated via mcff.
325 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
330 std::vector<MachineInstr*>& mvec,
331 MachineCodeForInstruction& mcfi) const=0;
333 // Create instruction sequence to produce a zero-extended register value
334 // from an arbitrary sized value (sized in bits, not bytes).
335 // The generated instructions are appended to `mvec'.
336 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
337 // Any stack space required is allocated via mcff.
339 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
343 unsigned srcSizeInBits,
344 std::vector<MachineInstr*>& mvec,
345 MachineCodeForInstruction& mcfi) const=0;