1 //===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==//
3 // This file describes the target machine instructions to the code generator.
5 //===---------------------------------------------------------------------===//
7 #ifndef LLVM_TARGET_MACHINEINSTRINFO_H
8 #define LLVM_TARGET_MACHINEINSTRINFO_H
10 #include "Support/DataTypes.h"
13 class MachineInstrDescriptor;
20 class MachineCodeForInstruction;
22 //---------------------------------------------------------------------------
23 // Data types used to define information about a single machine instruction
24 //---------------------------------------------------------------------------
26 typedef int MachineOpCode;
27 typedef unsigned InstrSchedClass;
29 const MachineOpCode INVALID_MACHINE_OPCODE = -1;
32 //---------------------------------------------------------------------------
33 // struct MachineInstrDescriptor:
34 // Predefined information about each machine instruction.
35 // Designed to initialized statically.
37 // class MachineInstructionInfo
38 // Interface to description of machine instructions
40 //---------------------------------------------------------------------------
42 const unsigned M_NOP_FLAG = 1 << 0;
43 const unsigned M_BRANCH_FLAG = 1 << 1;
44 const unsigned M_CALL_FLAG = 1 << 2;
45 const unsigned M_RET_FLAG = 1 << 3;
46 const unsigned M_ARITH_FLAG = 1 << 4;
47 const unsigned M_CC_FLAG = 1 << 6;
48 const unsigned M_LOGICAL_FLAG = 1 << 6;
49 const unsigned M_INT_FLAG = 1 << 7;
50 const unsigned M_FLOAT_FLAG = 1 << 8;
51 const unsigned M_CONDL_FLAG = 1 << 9;
52 const unsigned M_LOAD_FLAG = 1 << 10;
53 const unsigned M_PREFETCH_FLAG = 1 << 11;
54 const unsigned M_STORE_FLAG = 1 << 12;
55 const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
56 const unsigned M_PSEUDO_FLAG = 1 << 14;
59 struct MachineInstrDescriptor {
60 const char * Name; // Assembly language mnemonic for the opcode.
61 int numOperands; // Number of args; -1 if variable #args
62 int resultPos; // Position of the result; -1 if no result
63 unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0.
64 bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
65 // smallest -ve value is -(maxImmedConst+1).
66 unsigned numDelaySlots; // Number of delay slots after instruction
67 unsigned latency; // Latency in machine cycles
68 InstrSchedClass schedClass; // enum identifying instr sched class
69 unsigned Flags; // flags identifying machine instr class
70 unsigned TSFlags; // Target Specific Flag values
74 class MachineInstrInfo {
75 const MachineInstrDescriptor* desc; // raw array to allow static init'n
76 unsigned descSize; // number of entries in the desc array
77 unsigned numRealOpCodes; // number of non-dummy op codes
79 MachineInstrInfo(const MachineInstrInfo &); // DO NOT IMPLEMENT
80 void operator=(const MachineInstrInfo &); // DO NOT IMPLEMENT
82 MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize,
83 unsigned numRealOpCodes);
84 virtual ~MachineInstrInfo();
86 unsigned getNumRealOpCodes() const { return numRealOpCodes; }
87 unsigned getNumTotalOpCodes() const { return descSize; }
89 /// get - Return the machine instruction descriptor that corresponds to the
90 /// specified instruction opcode.
92 const MachineInstrDescriptor& get(MachineOpCode opCode) const {
93 assert(opCode >= 0 && opCode < (int)descSize);
97 /// print - Print out the specified machine instruction in the appropriate
98 /// target specific assembly language. If this method is not overridden, the
99 /// default implementation uses the crummy machine independant printer.
101 virtual void print(const MachineInstr *MI, std::ostream &O) const;
103 const char *getName(MachineOpCode opCode) const {
104 return get(opCode).Name;
107 int getNumOperands(MachineOpCode opCode) const {
108 return get(opCode).numOperands;
111 int getResultPos(MachineOpCode opCode) const {
112 return get(opCode).resultPos;
115 unsigned getNumDelaySlots(MachineOpCode opCode) const {
116 return get(opCode).numDelaySlots;
119 InstrSchedClass getSchedClass(MachineOpCode opCode) const {
120 return get(opCode).schedClass;
124 // Query instruction class flags according to the machine-independent
125 // flags listed above.
127 bool isNop(MachineOpCode opCode) const {
128 return get(opCode).Flags & M_NOP_FLAG;
130 bool isBranch(MachineOpCode opCode) const {
131 return get(opCode).Flags & M_BRANCH_FLAG;
133 bool isCall(MachineOpCode opCode) const {
134 return get(opCode).Flags & M_CALL_FLAG;
136 bool isReturn(MachineOpCode opCode) const {
137 return get(opCode).Flags & M_RET_FLAG;
139 bool isControlFlow(MachineOpCode opCode) const {
140 return get(opCode).Flags & M_BRANCH_FLAG
141 || get(opCode).Flags & M_CALL_FLAG
142 || get(opCode).Flags & M_RET_FLAG;
144 bool isArith(MachineOpCode opCode) const {
145 return get(opCode).Flags & M_ARITH_FLAG;
147 bool isCCInstr(MachineOpCode opCode) const {
148 return get(opCode).Flags & M_CC_FLAG;
150 bool isLogical(MachineOpCode opCode) const {
151 return get(opCode).Flags & M_LOGICAL_FLAG;
153 bool isIntInstr(MachineOpCode opCode) const {
154 return get(opCode).Flags & M_INT_FLAG;
156 bool isFloatInstr(MachineOpCode opCode) const {
157 return get(opCode).Flags & M_FLOAT_FLAG;
159 bool isConditional(MachineOpCode opCode) const {
160 return get(opCode).Flags & M_CONDL_FLAG;
162 bool isLoad(MachineOpCode opCode) const {
163 return get(opCode).Flags & M_LOAD_FLAG;
165 bool isPrefetch(MachineOpCode opCode) const {
166 return get(opCode).Flags & M_PREFETCH_FLAG;
168 bool isLoadOrPrefetch(MachineOpCode opCode) const {
169 return get(opCode).Flags & M_LOAD_FLAG
170 || get(opCode).Flags & M_PREFETCH_FLAG;
172 bool isStore(MachineOpCode opCode) const {
173 return get(opCode).Flags & M_STORE_FLAG;
175 bool isMemoryAccess(MachineOpCode opCode) const {
176 return get(opCode).Flags & M_LOAD_FLAG
177 || get(opCode).Flags & M_PREFETCH_FLAG
178 || get(opCode).Flags & M_STORE_FLAG;
180 bool isDummyPhiInstr(const MachineOpCode opCode) const {
181 return get(opCode).Flags & M_DUMMY_PHI_FLAG;
183 bool isPseudoInstr(const MachineOpCode opCode) const {
184 return get(opCode).Flags & M_PSEUDO_FLAG;
187 // Check if an instruction can be issued before its operands are ready,
188 // or if a subsequent instruction that uses its result can be issued
189 // before the results are ready.
190 // Default to true since most instructions on many architectures allow this.
192 virtual bool hasOperandInterlock(MachineOpCode opCode) const {
196 virtual bool hasResultInterlock(MachineOpCode opCode) const {
201 // Latencies for individual instructions and instruction pairs
203 virtual int minLatency(MachineOpCode opCode) const {
204 return get(opCode).latency;
207 virtual int maxLatency(MachineOpCode opCode) const {
208 return get(opCode).latency;
212 // Which operand holds an immediate constant? Returns -1 if none
214 virtual int getImmedConstantPos(MachineOpCode opCode) const {
215 return -1; // immediate position is machine specific, so say -1 == "none"
218 // Check if the specified constant fits in the immediate field
219 // of this machine instruction
221 virtual bool constantFitsInImmedField(MachineOpCode opCode,
222 int64_t intValue) const;
224 // Return the largest +ve constant that can be held in the IMMMED field
225 // of this machine instruction.
226 // isSignExtended is set to true if the value is sign-extended before use
227 // (this is true for all immediate fields in SPARC instructions).
228 // Return 0 if the instruction has no IMMED field.
230 virtual uint64_t maxImmedConstant(MachineOpCode opCode,
231 bool &isSignExtended) const {
232 isSignExtended = get(opCode).immedIsSignExtended;
233 return get(opCode).maxImmedConst;
236 //-------------------------------------------------------------------------
237 // Queries about representation of LLVM quantities (e.g., constants)
238 //-------------------------------------------------------------------------
240 /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded
241 /// from memory into a register, i.e., cannot be set bitwise in register and
242 /// cannot use immediate fields of instructions. Note that this only makes
243 /// sense for primitive types.
245 virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const;
247 // Test if this constant may not fit in the immediate field of the
248 // machine instructions (probably) generated for this instruction.
250 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
251 const Instruction* I) const {
252 return true; // safe but very conservative
255 //-------------------------------------------------------------------------
256 // Code generation support for creating individual machine instructions
257 //-------------------------------------------------------------------------
259 // Get certain common op codes for the current target. this and all the
260 // Create* methods below should be moved to a machine code generation class
262 virtual MachineOpCode getNOPOpCode() const = 0;
264 // Create an instruction sequence to put the constant `val' into
265 // the virtual register `dest'. `val' may be a Constant or a
266 // GlobalValue, viz., the constant address of a global variable or function.
267 // The generated instructions are returned in `mvec'.
268 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
269 // Symbolic constants or constants that must be accessed from memory
270 // are added to the constant pool via MachineFunction::get(F).
272 virtual void CreateCodeToLoadConst(const TargetMachine& target,
276 std::vector<MachineInstr*>& mvec,
277 MachineCodeForInstruction& mcfi) const=0;
279 // Create an instruction sequence to copy an integer value `val'
280 // to a floating point value `dest' by copying to memory and back.
281 // val must be an integral type. dest must be a Float or Double.
282 // The generated instructions are returned in `mvec'.
283 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
284 // Any stack space required is allocated via mcff.
286 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
290 std::vector<MachineInstr*>& mvec,
291 MachineCodeForInstruction& mcfi)const=0;
293 // Similarly, create an instruction sequence to copy an FP value
294 // `val' to an integer value `dest' by copying to memory and back.
295 // The generated instructions are returned in `mvec'.
296 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
297 // Any stack space required is allocated via mcff.
299 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
303 std::vector<MachineInstr*>& mvec,
304 MachineCodeForInstruction& mcfi)const=0;
306 // Create instruction(s) to copy src to dest, for arbitrary types
307 // The generated instructions are returned in `mvec'.
308 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
309 // Any stack space required is allocated via mcff.
311 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
315 std::vector<MachineInstr*>& mvec,
316 MachineCodeForInstruction& mcfi)const=0;
318 // Create instruction sequence to produce a sign-extended register value
319 // from an arbitrary sized value (sized in bits, not bytes).
320 // The generated instructions are appended to `mvec'.
321 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
322 // Any stack space required is allocated via mcff.
324 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
329 std::vector<MachineInstr*>& mvec,
330 MachineCodeForInstruction& mcfi) const=0;
332 // Create instruction sequence to produce a zero-extended register value
333 // from an arbitrary sized value (sized in bits, not bytes).
334 // The generated instructions are appended to `mvec'.
335 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
336 // Any stack space required is allocated via mcff.
338 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
342 unsigned srcSizeInBits,
343 std::vector<MachineInstr*>& mvec,
344 MachineCodeForInstruction& mcfi) const=0;