1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
22 class TargetRegisterClass;
24 class CalleeSavedInfo;
28 template<class T> class SmallVectorImpl;
31 //---------------------------------------------------------------------------
33 /// TargetInstrInfo - Interface to description of machine instruction set
35 class TargetInstrInfo {
36 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
37 unsigned NumOpcodes; // Number of entries in the desc array
39 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
40 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
42 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
43 virtual ~TargetInstrInfo();
45 // Invariant opcodes: All instruction sets have these as their low opcodes.
59 unsigned getNumOpcodes() const { return NumOpcodes; }
61 /// get - Return the machine instruction descriptor that corresponds to the
62 /// specified instruction opcode.
64 const TargetInstrDesc &get(unsigned Opcode) const {
65 assert(Opcode < NumOpcodes && "Invalid opcode!");
66 return Descriptors[Opcode];
69 /// isTriviallyReMaterializable - Return true if the instruction is trivially
70 /// rematerializable, meaning it has no side effects and requires no operands
71 /// that aren't always available.
72 bool isTriviallyReMaterializable(const MachineInstr *MI) const {
73 return MI->getDesc().isRematerializable() &&
74 isReallyTriviallyReMaterializable(MI);
78 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
79 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
80 /// instruction itself is actually trivially rematerializable, considering
81 /// its operands. This is used for targets that have instructions that are
82 /// only trivially rematerializable for specific uses. This predicate must
83 /// return false if the instruction has any side effects other than
84 /// producing a value, or if it requres any address registers that are not
86 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
91 /// Return true if the instruction is a register to register move
92 /// and leave the source and dest operands in the passed parameters.
93 virtual bool isMoveInstr(const MachineInstr& MI,
95 unsigned& destReg) const {
99 /// isLoadFromStackSlot - If the specified machine instruction is a direct
100 /// load from a stack slot, return the virtual or physical register number of
101 /// the destination along with the FrameIndex of the loaded stack slot. If
102 /// not, return 0. This predicate must return 0 if the instruction has
103 /// any side effects other than loading from the stack slot.
104 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
108 /// isStoreToStackSlot - If the specified machine instruction is a direct
109 /// store to a stack slot, return the virtual or physical register number of
110 /// the source reg along with the FrameIndex of the loaded stack slot. If
111 /// not, return 0. This predicate must return 0 if the instruction has
112 /// any side effects other than storing to the stack slot.
113 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
117 /// reMaterialize - Re-issue the specified 'original' instruction at the
118 /// specific location targeting a new destination register.
119 virtual void reMaterialize(MachineBasicBlock &MBB,
120 MachineBasicBlock::iterator MI,
122 const MachineInstr *Orig) const = 0;
124 /// isInvariantLoad - Return true if the specified instruction (which is
125 /// marked mayLoad) is loading from a location whose value is invariant across
126 /// the function. For example, loading a value from the constant pool or from
127 /// from the argument area of a function if it does not change. This should
128 /// only return true of *all* loads the instruction does are invariant (if it
129 /// does multiple loads).
130 virtual bool isInvariantLoad(MachineInstr *MI) const {
134 /// convertToThreeAddress - This method must be implemented by targets that
135 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
136 /// may be able to convert a two-address instruction into one or more true
137 /// three-address instructions on demand. This allows the X86 target (for
138 /// example) to convert ADD and SHL instructions into LEA instructions if they
139 /// would require register copies due to two-addressness.
141 /// This method returns a null pointer if the transformation cannot be
142 /// performed, otherwise it returns the last new instruction.
144 virtual MachineInstr *
145 convertToThreeAddress(MachineFunction::iterator &MFI,
146 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
150 /// commuteInstruction - If a target has any instructions that are commutable,
151 /// but require converting to a different instruction or making non-trivial
152 /// changes to commute them, this method can overloaded to do this. The
153 /// default implementation of this method simply swaps the first two operands
154 /// of MI and returns it.
156 /// If a target wants to make more aggressive changes, they can construct and
157 /// return a new machine instruction. If an instruction cannot commute, it
158 /// can also return null.
160 /// If NewMI is true, then a new machine instruction must be created.
162 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
163 bool NewMI = false) const = 0;
165 /// CommuteChangesDestination - Return true if commuting the specified
166 /// instruction will also changes the destination operand. Also return the
167 /// current operand index of the would be new destination register by
168 /// reference. This can happen when the commutable instruction is also a
169 /// two-address instruction.
170 virtual bool CommuteChangesDestination(MachineInstr *MI,
171 unsigned &OpIdx) const = 0;
173 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
174 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
175 /// implemented for a target). Upon success, this returns false and returns
176 /// with the following information in various cases:
178 /// 1. If this block ends with no branches (it just falls through to its succ)
179 /// just return false, leaving TBB/FBB null.
180 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
181 /// the destination block.
182 /// 3. If this block ends with an conditional branch and it falls through to
183 /// an successor block, it sets TBB to be the branch destination block and a
184 /// list of operands that evaluate the condition. These
185 /// operands can be passed to other TargetInstrInfo methods to create new
187 /// 4. If this block ends with an conditional branch and an unconditional
188 /// block, it returns the 'true' destination in TBB, the 'false' destination
189 /// in FBB, and a list of operands that evaluate the condition. These
190 /// operands can be passed to other TargetInstrInfo methods to create new
193 /// Note that RemoveBranch and InsertBranch must be implemented to support
194 /// cases where this method returns success.
196 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
197 MachineBasicBlock *&FBB,
198 SmallVectorImpl<MachineOperand> &Cond) const {
202 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
203 /// this is only invoked in cases where AnalyzeBranch returns success. It
204 /// returns the number of instructions that were removed.
205 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
206 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
210 /// InsertBranch - Insert a branch into the end of the specified
211 /// MachineBasicBlock. This operands to this method are the same as those
212 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
213 /// returns success and when an unconditional branch (TBB is non-null, FBB is
214 /// null, Cond is empty) needs to be inserted. It returns the number of
215 /// instructions inserted.
216 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
217 MachineBasicBlock *FBB,
218 const SmallVectorImpl<MachineOperand> &Cond) const {
219 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
223 /// copyRegToReg - Add a copy between a pair of registers
224 virtual bool copyRegToReg(MachineBasicBlock &MBB,
225 MachineBasicBlock::iterator MI,
226 unsigned DestReg, unsigned SrcReg,
227 const TargetRegisterClass *DestRC,
228 const TargetRegisterClass *SrcRC) const {
229 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
233 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
234 MachineBasicBlock::iterator MI,
235 unsigned SrcReg, bool isKill, int FrameIndex,
236 const TargetRegisterClass *RC) const {
237 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
240 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
241 SmallVectorImpl<MachineOperand> &Addr,
242 const TargetRegisterClass *RC,
243 SmallVectorImpl<MachineInstr*> &NewMIs) const {
244 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
247 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
248 MachineBasicBlock::iterator MI,
249 unsigned DestReg, int FrameIndex,
250 const TargetRegisterClass *RC) const {
251 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
254 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
255 SmallVectorImpl<MachineOperand> &Addr,
256 const TargetRegisterClass *RC,
257 SmallVectorImpl<MachineInstr*> &NewMIs) const {
258 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
261 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
262 /// saved registers and returns true if it isn't possible / profitable to do
263 /// so by issuing a series of store instructions via
264 /// storeRegToStackSlot(). Returns false otherwise.
265 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
266 MachineBasicBlock::iterator MI,
267 const std::vector<CalleeSavedInfo> &CSI) const {
271 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
272 /// saved registers and returns true if it isn't possible / profitable to do
273 /// so by issuing a series of load instructions via loadRegToStackSlot().
274 /// Returns false otherwise.
275 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
276 MachineBasicBlock::iterator MI,
277 const std::vector<CalleeSavedInfo> &CSI) const {
281 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
282 /// slot into the specified machine instruction for the specified operand(s).
283 /// If this is possible, a new instruction is returned with the specified
284 /// operand folded, otherwise NULL is returned. The client is responsible for
285 /// removing the old instruction and adding the new one in the instruction
287 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
289 SmallVectorImpl<unsigned> &Ops,
290 int FrameIndex) const {
294 /// foldMemoryOperand - Same as the previous version except it allows folding
295 /// of any load and store from / to any address, not just from a specific
297 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
299 SmallVectorImpl<unsigned> &Ops,
300 MachineInstr* LoadMI) const {
304 /// canFoldMemoryOperand - Returns true if the specified load / store is
305 /// folding is possible.
307 bool canFoldMemoryOperand(MachineInstr *MI,
308 SmallVectorImpl<unsigned> &Ops) const{
312 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
313 /// a store or a load and a store into two or more instruction. If this is
314 /// possible, returns true as well as the new instructions by reference.
315 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
316 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
317 SmallVectorImpl<MachineInstr*> &NewMIs) const{
321 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
322 SmallVectorImpl<SDNode*> &NewNodes) const {
326 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
327 /// instruction after load / store are unfolded from an instruction of the
328 /// specified opcode. It returns zero if the specified unfolding is not
330 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
331 bool UnfoldLoad, bool UnfoldStore) const {
335 /// BlockHasNoFallThrough - Return true if the specified block does not
336 /// fall-through into its successor block. This is primarily used when a
337 /// branch is unanalyzable. It is useful for things like unconditional
338 /// indirect branches (jump tables).
339 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
343 /// ReverseBranchCondition - Reverses the branch condition of the specified
344 /// condition list, returning false on success and true if it cannot be
347 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
351 /// insertNoop - Insert a noop into the instruction stream at the specified
353 virtual void insertNoop(MachineBasicBlock &MBB,
354 MachineBasicBlock::iterator MI) const {
355 assert(0 && "Target didn't implement insertNoop!");
359 /// isPredicated - Returns true if the instruction is already predicated.
361 virtual bool isPredicated(const MachineInstr *MI) const {
365 /// isUnpredicatedTerminator - Returns true if the instruction is a
366 /// terminator instruction that has not been predicated.
367 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
369 /// PredicateInstruction - Convert the instruction into a predicated
370 /// instruction. It returns true if the operation was successful.
372 bool PredicateInstruction(MachineInstr *MI,
373 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
375 /// SubsumesPredicate - Returns true if the first specified predicate
376 /// subsumes the second, e.g. GE subsumes GT.
378 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
379 const SmallVectorImpl<MachineOperand> &Pred2) const {
383 /// DefinesPredicate - If the specified instruction defines any predicate
384 /// or condition code register(s) used for predication, returns true as well
385 /// as the definition predicate(s) by reference.
386 virtual bool DefinesPredicate(MachineInstr *MI,
387 std::vector<MachineOperand> &Pred) const {
391 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
393 virtual const TargetRegisterClass *getPointerRegClass() const {
394 assert(0 && "Target didn't implement getPointerRegClass!");
396 return 0; // Must return a value in order to compile with VS 2005
399 /// GetInstSize - Returns the size of the specified Instruction.
401 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
402 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
406 /// GetFunctionSizeInBytes - Returns the size of the specified MachineFunction.
408 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
412 /// TargetInstrInfoImpl - This is the default implementation of
413 /// TargetInstrInfo, which just provides a couple of default implementations
414 /// for various methods. This separated out because it is implemented in
415 /// libcodegen, not in libtarget.
416 class TargetInstrInfoImpl : public TargetInstrInfo {
418 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
419 : TargetInstrInfo(desc, NumOpcodes) {}
421 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
422 bool NewMI = false) const;
423 virtual bool CommuteChangesDestination(MachineInstr *MI,
424 unsigned &OpIdx) const;
425 virtual bool PredicateInstruction(MachineInstr *MI,
426 const SmallVectorImpl<MachineOperand> &Pred) const;
427 virtual void reMaterialize(MachineBasicBlock &MBB,
428 MachineBasicBlock::iterator MI,
430 const MachineInstr *Orig) const;
431 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
434 } // End llvm namespace