1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
22 class TargetRegisterClass;
24 class CalleeSavedInfo;
28 template<class T> class SmallVectorImpl;
31 //---------------------------------------------------------------------------
33 /// TargetInstrInfo - Interface to description of machine instructions
35 class TargetInstrInfo {
36 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
37 unsigned NumOpcodes; // Number of entries in the desc array
39 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
40 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
42 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
43 virtual ~TargetInstrInfo();
45 // Invariant opcodes: All instruction sets have these as their low opcodes.
55 unsigned getNumOpcodes() const { return NumOpcodes; }
57 /// get - Return the machine instruction descriptor that corresponds to the
58 /// specified instruction opcode.
60 const TargetInstrDesc &get(unsigned Opcode) const {
61 assert(Opcode < NumOpcodes && "Invalid opcode!");
62 return Descriptors[Opcode];
65 /// isTriviallyReMaterializable - Return true if the instruction is trivially
66 /// rematerializable, meaning it has no side effects and requires no operands
67 /// that aren't always available.
68 bool isTriviallyReMaterializable(MachineInstr *MI) const {
69 return MI->getDesc().isRematerializable() &&
70 isReallyTriviallyReMaterializable(MI);
74 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
75 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
76 /// instruction itself is actually trivially rematerializable, considering
77 /// its operands. This is used for targets that have instructions that are
78 /// only trivially rematerializable for specific uses. This predicate must
79 /// return false if the instruction has any side effects other than
80 /// producing a value, or if it requres any address registers that are not
82 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
87 /// Return true if the instruction is a register to register move
88 /// and leave the source and dest operands in the passed parameters.
89 virtual bool isMoveInstr(const MachineInstr& MI,
91 unsigned& destReg) const {
95 /// isLoadFromStackSlot - If the specified machine instruction is a direct
96 /// load from a stack slot, return the virtual or physical register number of
97 /// the destination along with the FrameIndex of the loaded stack slot. If
98 /// not, return 0. This predicate must return 0 if the instruction has
99 /// any side effects other than loading from the stack slot.
100 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
104 /// isStoreToStackSlot - If the specified machine instruction is a direct
105 /// store to a stack slot, return the virtual or physical register number of
106 /// the source reg along with the FrameIndex of the loaded stack slot. If
107 /// not, return 0. This predicate must return 0 if the instruction has
108 /// any side effects other than storing to the stack slot.
109 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
113 /// isInvariantLoad - Return true if the specified instruction (which is
114 /// marked mayLoad) is loading from a location whose value is invariant across
115 /// the function. For example, loading a value from the constant pool or from
116 /// from the argument area of a function if it does not change. This should
117 /// only return true of *all* loads the instruction does are invariant (if it
118 /// does multiple loads).
119 virtual bool isInvariantLoad(MachineInstr *MI) const {
124 /// convertToThreeAddress - This method must be implemented by targets that
125 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
126 /// may be able to convert a two-address instruction into one or more true
127 /// three-address instructions on demand. This allows the X86 target (for
128 /// example) to convert ADD and SHL instructions into LEA instructions if they
129 /// would require register copies due to two-addressness.
131 /// This method returns a null pointer if the transformation cannot be
132 /// performed, otherwise it returns the last new instruction.
134 virtual MachineInstr *
135 convertToThreeAddress(MachineFunction::iterator &MFI,
136 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
140 /// commuteInstruction - If a target has any instructions that are commutable,
141 /// but require converting to a different instruction or making non-trivial
142 /// changes to commute them, this method can overloaded to do this. The
143 /// default implementation of this method simply swaps the first two operands
144 /// of MI and returns it.
146 /// If a target wants to make more aggressive changes, they can construct and
147 /// return a new machine instruction. If an instruction cannot commute, it
148 /// can also return null.
150 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0;
152 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
153 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
154 /// implemented for a target). Upon success, this returns false and returns
155 /// with the following information in various cases:
157 /// 1. If this block ends with no branches (it just falls through to its succ)
158 /// just return false, leaving TBB/FBB null.
159 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
160 /// the destination block.
161 /// 3. If this block ends with an conditional branch and it falls through to
162 /// an successor block, it sets TBB to be the branch destination block and a
163 /// list of operands that evaluate the condition. These
164 /// operands can be passed to other TargetInstrInfo methods to create new
166 /// 4. If this block ends with an conditional branch and an unconditional
167 /// block, it returns the 'true' destination in TBB, the 'false' destination
168 /// in FBB, and a list of operands that evaluate the condition. These
169 /// operands can be passed to other TargetInstrInfo methods to create new
172 /// Note that RemoveBranch and InsertBranch must be implemented to support
173 /// cases where this method returns success.
175 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
176 MachineBasicBlock *&FBB,
177 std::vector<MachineOperand> &Cond) const {
181 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
182 /// this is only invoked in cases where AnalyzeBranch returns success. It
183 /// returns the number of instructions that were removed.
184 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
185 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
189 /// InsertBranch - Insert a branch into the end of the specified
190 /// MachineBasicBlock. This operands to this method are the same as those
191 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
192 /// returns success and when an unconditional branch (TBB is non-null, FBB is
193 /// null, Cond is empty) needs to be inserted. It returns the number of
194 /// instructions inserted.
195 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
196 MachineBasicBlock *FBB,
197 const std::vector<MachineOperand> &Cond) const {
198 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
202 /// copyRegToReg - Add a copy between a pair of registers
203 virtual void copyRegToReg(MachineBasicBlock &MBB,
204 MachineBasicBlock::iterator MI,
205 unsigned DestReg, unsigned SrcReg,
206 const TargetRegisterClass *DestRC,
207 const TargetRegisterClass *SrcRC) const {
208 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
211 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
212 MachineBasicBlock::iterator MI,
213 unsigned SrcReg, bool isKill, int FrameIndex,
214 const TargetRegisterClass *RC) const {
215 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
218 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
219 SmallVectorImpl<MachineOperand> &Addr,
220 const TargetRegisterClass *RC,
221 SmallVectorImpl<MachineInstr*> &NewMIs) const {
222 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
225 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
226 MachineBasicBlock::iterator MI,
227 unsigned DestReg, int FrameIndex,
228 const TargetRegisterClass *RC) const {
229 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
232 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
233 SmallVectorImpl<MachineOperand> &Addr,
234 const TargetRegisterClass *RC,
235 SmallVectorImpl<MachineInstr*> &NewMIs) const {
236 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
239 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
240 /// saved registers and returns true if it isn't possible / profitable to do
241 /// so by issuing a series of store instructions via
242 /// storeRegToStackSlot(). Returns false otherwise.
243 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
244 MachineBasicBlock::iterator MI,
245 const std::vector<CalleeSavedInfo> &CSI) const {
249 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
250 /// saved registers and returns true if it isn't possible / profitable to do
251 /// so by issuing a series of load instructions via loadRegToStackSlot().
252 /// Returns false otherwise.
253 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
254 MachineBasicBlock::iterator MI,
255 const std::vector<CalleeSavedInfo> &CSI) const {
259 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
260 /// slot into the specified machine instruction for the specified operand(s).
261 /// If this is possible, a new instruction is returned with the specified
262 /// operand folded, otherwise NULL is returned. The client is responsible for
263 /// removing the old instruction and adding the new one in the instruction
265 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
267 SmallVectorImpl<unsigned> &Ops,
268 int FrameIndex) const {
272 /// foldMemoryOperand - Same as the previous version except it allows folding
273 /// of any load and store from / to any address, not just from a specific
275 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
277 SmallVectorImpl<unsigned> &Ops,
278 MachineInstr* LoadMI) const {
282 /// canFoldMemoryOperand - Returns true if the specified load / store is
283 /// folding is possible.
285 bool canFoldMemoryOperand(MachineInstr *MI,
286 SmallVectorImpl<unsigned> &Ops) const{
290 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
291 /// a store or a load and a store into two or more instruction. If this is
292 /// possible, returns true as well as the new instructions by reference.
293 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
294 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
295 SmallVectorImpl<MachineInstr*> &NewMIs) const{
299 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
300 SmallVectorImpl<SDNode*> &NewNodes) const {
304 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
305 /// instruction after load / store are unfolded from an instruction of the
306 /// specified opcode. It returns zero if the specified unfolding is not
308 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
309 bool UnfoldLoad, bool UnfoldStore) const {
313 /// BlockHasNoFallThrough - Return true if the specified block does not
314 /// fall-through into its successor block. This is primarily used when a
315 /// branch is unanalyzable. It is useful for things like unconditional
316 /// indirect branches (jump tables).
317 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
321 /// ReverseBranchCondition - Reverses the branch condition of the specified
322 /// condition list, returning false on success and true if it cannot be
324 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
328 /// insertNoop - Insert a noop into the instruction stream at the specified
330 virtual void insertNoop(MachineBasicBlock &MBB,
331 MachineBasicBlock::iterator MI) const {
332 assert(0 && "Target didn't implement insertNoop!");
336 /// isPredicated - Returns true if the instruction is already predicated.
338 virtual bool isPredicated(const MachineInstr *MI) const {
342 /// isUnpredicatedTerminator - Returns true if the instruction is a
343 /// terminator instruction that has not been predicated.
344 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
346 /// PredicateInstruction - Convert the instruction into a predicated
347 /// instruction. It returns true if the operation was successful.
349 bool PredicateInstruction(MachineInstr *MI,
350 const std::vector<MachineOperand> &Pred) const = 0;
352 /// SubsumesPredicate - Returns true if the first specified predicate
353 /// subsumes the second, e.g. GE subsumes GT.
355 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
356 const std::vector<MachineOperand> &Pred2) const {
360 /// DefinesPredicate - If the specified instruction defines any predicate
361 /// or condition code register(s) used for predication, returns true as well
362 /// as the definition predicate(s) by reference.
363 virtual bool DefinesPredicate(MachineInstr *MI,
364 std::vector<MachineOperand> &Pred) const {
368 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
370 virtual const TargetRegisterClass *getPointerRegClass() const {
371 assert(0 && "Target didn't implement getPointerRegClass!");
373 return 0; // Must return a value in order to compile with VS 2005
377 /// TargetInstrInfoImpl - This is the default implementation of
378 /// TargetInstrInfo, which just provides a couple of default implementations
379 /// for various methods. This separated out because it is implemented in
380 /// libcodegen, not in libtarget.
381 class TargetInstrInfoImpl : public TargetInstrInfo {
383 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
384 : TargetInstrInfo(desc, NumOpcodes) {}
386 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
387 virtual bool PredicateInstruction(MachineInstr *MI,
388 const std::vector<MachineOperand> &Pred) const;
392 } // End llvm namespace