1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "Support/DataTypes.h"
30 class MachineCodeForInstruction;
32 //---------------------------------------------------------------------------
33 // Data types used to define information about a single machine instruction
34 //---------------------------------------------------------------------------
36 typedef short MachineOpCode;
37 typedef unsigned InstrSchedClass;
39 //---------------------------------------------------------------------------
40 // struct TargetInstrDescriptor:
41 // Predefined information about each machine instruction.
42 // Designed to initialized statically.
45 const unsigned M_NOP_FLAG = 1 << 0;
46 const unsigned M_BRANCH_FLAG = 1 << 1;
47 const unsigned M_CALL_FLAG = 1 << 2;
48 const unsigned M_RET_FLAG = 1 << 3;
49 const unsigned M_CC_FLAG = 1 << 6;
50 const unsigned M_LOAD_FLAG = 1 << 10;
51 const unsigned M_STORE_FLAG = 1 << 12;
52 const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
53 const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction
54 // 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub
55 const unsigned M_2_ADDR_FLAG = 1 << 15;
57 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
58 // block? Typically this is things like return and branch instructions.
59 // Various passes use this to insert code into the bottom of a basic block, but
60 // before control flow occurs.
61 const unsigned M_TERMINATOR_FLAG = 1 << 16;
63 struct TargetInstrDescriptor {
64 const char * Name; // Assembly language mnemonic for the opcode.
65 int numOperands; // Number of args; -1 if variable #args
66 int resultPos; // Position of the result; -1 if no result
67 unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0.
68 bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
69 // smallest -ve value is -(maxImmedConst+1).
70 unsigned numDelaySlots; // Number of delay slots after instruction
71 unsigned latency; // Latency in machine cycles
72 InstrSchedClass schedClass; // enum identifying instr sched class
73 unsigned Flags; // flags identifying machine instr class
74 unsigned TSFlags; // Target Specific Flag values
75 const unsigned *ImplicitUses; // Registers implicitly read by this instr
76 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
80 //---------------------------------------------------------------------------
82 /// TargetInstrInfo - Interface to description of machine instructions
84 class TargetInstrInfo {
85 const TargetInstrDescriptor* desc; // raw array to allow static init'n
86 unsigned NumOpcodes; // number of entries in the desc array
87 unsigned numRealOpCodes; // number of non-dummy op codes
89 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
90 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
92 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
93 virtual ~TargetInstrInfo();
95 // Invariant: All instruction sets use opcode #0 as the PHI instruction
98 unsigned getNumOpcodes() const { return NumOpcodes; }
100 /// get - Return the machine instruction descriptor that corresponds to the
101 /// specified instruction opcode.
103 const TargetInstrDescriptor& get(MachineOpCode opCode) const {
104 assert((unsigned)opCode < NumOpcodes);
108 const char *getName(MachineOpCode opCode) const {
109 return get(opCode).Name;
112 int getNumOperands(MachineOpCode opCode) const {
113 return get(opCode).numOperands;
117 InstrSchedClass getSchedClass(MachineOpCode opCode) const {
118 return get(opCode).schedClass;
121 const unsigned *getImplicitUses(MachineOpCode opCode) const {
122 return get(opCode).ImplicitUses;
125 const unsigned *getImplicitDefs(MachineOpCode opCode) const {
126 return get(opCode).ImplicitDefs;
131 // Query instruction class flags according to the machine-independent
132 // flags listed above.
134 bool isReturn(MachineOpCode opCode) const {
135 return get(opCode).Flags & M_RET_FLAG;
138 bool isPseudoInstr(MachineOpCode opCode) const {
139 return get(opCode).Flags & M_PSEUDO_FLAG;
141 bool isTwoAddrInstr(MachineOpCode opCode) const {
142 return get(opCode).Flags & M_2_ADDR_FLAG;
144 bool isTerminatorInstr(unsigned Opcode) const {
145 return get(Opcode).Flags & M_TERMINATOR_FLAG;
149 // Return true if the instruction is a register to register move and
150 // leave the source and dest operands in the passed parameters.
152 virtual bool isMoveInstr(const MachineInstr& MI,
154 unsigned& destReg) const {
161 //-------------------------------------------------------------------------
162 // Code generation support for creating individual machine instructions
164 // WARNING: These methods are Sparc specific
166 // DO NOT USE ANY OF THESE METHODS THEY ARE DEPRECATED!
168 //-------------------------------------------------------------------------
170 int getResultPos(MachineOpCode opCode) const {
171 return get(opCode).resultPos;
173 unsigned getNumDelaySlots(MachineOpCode opCode) const {
174 return get(opCode).numDelaySlots;
176 bool isCCInstr(MachineOpCode opCode) const {
177 return get(opCode).Flags & M_CC_FLAG;
179 bool isNop(MachineOpCode opCode) const {
180 return get(opCode).Flags & M_NOP_FLAG;
182 bool isBranch(MachineOpCode opCode) const {
183 return get(opCode).Flags & M_BRANCH_FLAG;
185 bool isCall(MachineOpCode opCode) const {
186 return get(opCode).Flags & M_CALL_FLAG;
188 bool isLoad(MachineOpCode opCode) const {
189 return get(opCode).Flags & M_LOAD_FLAG;
191 bool isStore(MachineOpCode opCode) const {
192 return get(opCode).Flags & M_STORE_FLAG;
194 bool isDummyPhiInstr(MachineOpCode opCode) const {
195 return get(opCode).Flags & M_DUMMY_PHI_FLAG;
198 virtual bool hasResultInterlock(MachineOpCode opCode) const {
203 // Latencies for individual instructions and instruction pairs
205 virtual int minLatency(MachineOpCode opCode) const {
206 return get(opCode).latency;
209 virtual int maxLatency(MachineOpCode opCode) const {
210 return get(opCode).latency;
214 // Which operand holds an immediate constant? Returns -1 if none
216 virtual int getImmedConstantPos(MachineOpCode opCode) const {
217 return -1; // immediate position is machine specific, so say -1 == "none"
220 // Check if the specified constant fits in the immediate field
221 // of this machine instruction
223 virtual bool constantFitsInImmedField(MachineOpCode opCode,
224 int64_t intValue) const;
226 // Return the largest positive constant that can be held in the IMMED field
227 // of this machine instruction.
228 // isSignExtended is set to true if the value is sign-extended before use
229 // (this is true for all immediate fields in SPARC instructions).
230 // Return 0 if the instruction has no IMMED field.
232 virtual uint64_t maxImmedConstant(MachineOpCode opCode,
233 bool &isSignExtended) const {
234 isSignExtended = get(opCode).immedIsSignExtended;
235 return get(opCode).maxImmedConst;
239 } // End llvm namespace