1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/Support/DataTypes.h"
31 class MachineCodeForInstruction;
32 class TargetRegisterClass;
34 //---------------------------------------------------------------------------
35 // Data types used to define information about a single machine instruction
36 //---------------------------------------------------------------------------
38 typedef short MachineOpCode;
39 typedef unsigned InstrSchedClass;
41 //---------------------------------------------------------------------------
42 // struct TargetInstrDescriptor:
43 // Predefined information about each machine instruction.
44 // Designed to initialized statically.
47 const unsigned M_BRANCH_FLAG = 1 << 0;
48 const unsigned M_CALL_FLAG = 1 << 1;
49 const unsigned M_RET_FLAG = 1 << 2;
50 const unsigned M_BARRIER_FLAG = 1 << 3;
51 const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
52 const unsigned M_LOAD_FLAG = 1 << 5;
53 const unsigned M_STORE_FLAG = 1 << 6;
55 // M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
56 // changed into a 3-address instruction if the first two operands cannot be
57 // assigned to the same register. The target must implement the
58 // TargetInstrInfo::convertToThreeAddress method for this instruction.
59 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 7;
61 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
62 // Z), which produces the same result if Y and Z are exchanged.
63 const unsigned M_COMMUTABLE = 1 << 8;
65 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
66 // block? Typically this is things like return and branch instructions.
67 // Various passes use this to insert code into the bottom of a basic block, but
68 // before control flow occurs.
69 const unsigned M_TERMINATOR_FLAG = 1 << 9;
71 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
72 // insertion support when the DAG scheduler is inserting it into a machine basic
74 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10;
76 // M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
77 // operands in addition to the minimum number operands specified.
78 const unsigned M_VARIABLE_OPS = 1 << 11;
80 // M_PREDICATED - Set if this instruction has a predicate that controls its
82 const unsigned M_PREDICATED = 1 << 12;
85 // Machine operand flags
86 // M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
87 // requires a callback to look up its register class.
88 const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
90 /// M_PREDICATE_OPERAND - Set if this is the first operand of a predicate
91 /// operand that controls an M_PREDICATED instruction.
92 const unsigned M_PREDICATE_OPERAND = 1 << 1;
95 /// TargetOperandInfo - This holds information about one operand of a machine
96 /// instruction, indicating the register class for register operands, etc.
98 class TargetOperandInfo {
100 /// RegClass - This specifies the register class enumeration of the operand
101 /// if the operand is a register. If not, this contains 0.
102 unsigned short RegClass;
103 unsigned short Flags;
104 /// Lower 16 bits are used to specify which constraints are set. The higher 16
105 /// bits are used to specify the value of constraints (4 bits each).
106 unsigned int Constraints;
107 /// Currently no other information.
111 class TargetInstrDescriptor {
113 const char * Name; // Assembly language mnemonic for the opcode.
114 unsigned numOperands; // Num of args (may be more if variable_ops).
115 InstrSchedClass schedClass; // enum identifying instr sched class
116 unsigned Flags; // flags identifying machine instr class
117 unsigned TSFlags; // Target Specific Flag values
118 const unsigned *ImplicitUses; // Registers implicitly read by this instr
119 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
120 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
124 //---------------------------------------------------------------------------
126 /// TargetInstrInfo - Interface to description of machine instructions
128 class TargetInstrInfo {
129 const TargetInstrDescriptor* desc; // raw array to allow static init'n
130 unsigned NumOpcodes; // number of entries in the desc array
131 unsigned numRealOpCodes; // number of non-dummy op codes
133 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
134 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
136 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
137 virtual ~TargetInstrInfo();
139 // Invariant opcodes: All instruction sets have these as their low opcodes.
145 unsigned getNumOpcodes() const { return NumOpcodes; }
147 /// get - Return the machine instruction descriptor that corresponds to the
148 /// specified instruction opcode.
150 const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
151 assert((unsigned)Opcode < NumOpcodes);
155 const char *getName(MachineOpCode Opcode) const {
156 return get(Opcode).Name;
159 int getNumOperands(MachineOpCode Opcode) const {
160 return get(Opcode).numOperands;
163 InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
164 return get(Opcode).schedClass;
167 const unsigned *getImplicitUses(MachineOpCode Opcode) const {
168 return get(Opcode).ImplicitUses;
171 const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
172 return get(Opcode).ImplicitDefs;
177 // Query instruction class flags according to the machine-independent
178 // flags listed above.
180 bool isReturn(MachineOpCode Opcode) const {
181 return get(Opcode).Flags & M_RET_FLAG;
184 bool isPredicated(MachineOpCode Opcode) const {
185 return get(Opcode).Flags & M_PREDICATED;
187 bool isCommutableInstr(MachineOpCode Opcode) const {
188 return get(Opcode).Flags & M_COMMUTABLE;
190 bool isTerminatorInstr(unsigned Opcode) const {
191 return get(Opcode).Flags & M_TERMINATOR_FLAG;
194 bool isBranch(MachineOpCode Opcode) const {
195 return get(Opcode).Flags & M_BRANCH_FLAG;
198 /// isBarrier - Returns true if the specified instruction stops control flow
199 /// from executing the instruction immediately following it. Examples include
200 /// unconditional branches and return instructions.
201 bool isBarrier(MachineOpCode Opcode) const {
202 return get(Opcode).Flags & M_BARRIER_FLAG;
205 bool isCall(MachineOpCode Opcode) const {
206 return get(Opcode).Flags & M_CALL_FLAG;
208 bool isLoad(MachineOpCode Opcode) const {
209 return get(Opcode).Flags & M_LOAD_FLAG;
211 bool isStore(MachineOpCode Opcode) const {
212 return get(Opcode).Flags & M_STORE_FLAG;
215 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
216 /// which must be filled by the code generator.
217 bool hasDelaySlot(unsigned Opcode) const {
218 return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
221 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
222 /// custom insertion support when the DAG scheduler is inserting it into a
223 /// machine basic block.
224 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
225 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
228 bool hasVariableOperands(MachineOpCode Opcode) const {
229 return get(Opcode).Flags & M_VARIABLE_OPS;
232 // Operand constraints: only "tied_to" for now.
233 enum OperandConstraint {
234 TIED_TO = 0 // Must be allocated the same register as.
237 /// getOperandConstraint - Returns the value of the specific constraint if
238 /// it is set. Returns -1 if it is not set.
239 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum,
240 OperandConstraint Constraint) const {
241 assert(OpNum < get(Opcode).numOperands &&
242 "Invalid operand # of TargetInstrInfo");
243 if (get(Opcode).OpInfo[OpNum].Constraints & (1 << Constraint)) {
244 unsigned Pos = 16 + Constraint * 4;
245 return (int)(get(Opcode).OpInfo[OpNum].Constraints >> Pos) & 0xf;
250 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
251 /// dest operand. Returns -1 if there isn't one.
252 int findTiedToSrcOperand(MachineOpCode Opcode, unsigned OpNum) const;
254 /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
255 /// instruction if it has one. This is used by codegen passes that update
256 /// DWARF line number info as they modify the code.
257 virtual unsigned getDWARF_LABELOpcode() const {
261 /// Return true if the instruction is a register to register move
262 /// and leave the source and dest operands in the passed parameters.
263 virtual bool isMoveInstr(const MachineInstr& MI,
265 unsigned& destReg) const {
269 /// isLoadFromStackSlot - If the specified machine instruction is a direct
270 /// load from a stack slot, return the virtual or physical register number of
271 /// the destination along with the FrameIndex of the loaded stack slot. If
272 /// not, return 0. This predicate must return 0 if the instruction has
273 /// any side effects other than loading from the stack slot.
274 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
278 /// isStoreToStackSlot - If the specified machine instruction is a direct
279 /// store to a stack slot, return the virtual or physical register number of
280 /// the source reg along with the FrameIndex of the loaded stack slot. If
281 /// not, return 0. This predicate must return 0 if the instruction has
282 /// any side effects other than storing to the stack slot.
283 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
287 /// convertToThreeAddress - This method must be implemented by targets that
288 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
289 /// may be able to convert a two-address instruction into a true
290 /// three-address instruction on demand. This allows the X86 target (for
291 /// example) to convert ADD and SHL instructions into LEA instructions if they
292 /// would require register copies due to two-addressness.
294 /// This method returns a null pointer if the transformation cannot be
295 /// performed, otherwise it returns the new instruction.
297 virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const {
301 /// commuteInstruction - If a target has any instructions that are commutable,
302 /// but require converting to a different instruction or making non-trivial
303 /// changes to commute them, this method can overloaded to do this. The
304 /// default implementation of this method simply swaps the first two operands
305 /// of MI and returns it.
307 /// If a target wants to make more aggressive changes, they can construct and
308 /// return a new machine instruction. If an instruction cannot commute, it
309 /// can also return null.
311 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
313 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
314 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
315 /// implemented for a target). Upon success, this returns false and returns
316 /// with the following information in various cases:
318 /// 1. If this block ends with no branches (it just falls through to its succ)
319 /// just return false, leaving TBB/FBB null.
320 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
321 /// the destination block.
322 /// 3. If this block ends with an conditional branch, it returns the 'true'
323 /// destination in TBB, the 'false' destination in FBB, and a list of
324 /// operands that evaluate the condition. These operands can be passed to
325 /// other TargetInstrInfo methods to create new branches.
327 /// Note that RemoveBranch and InsertBranch must be implemented to support
328 /// cases where this method returns success.
330 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
331 MachineBasicBlock *&FBB,
332 std::vector<MachineOperand> &Cond) const {
336 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
337 /// this is only invoked in cases where AnalyzeBranch returns success.
338 virtual void RemoveBranch(MachineBasicBlock &MBB) const {
339 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
342 /// InsertBranch - Insert a branch into the end of the specified
343 /// MachineBasicBlock. This operands to this method are the same as those
344 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
345 /// returns success and when an unconditional branch (TBB is non-null, FBB is
346 /// null, Cond is empty) needs to be inserted.
347 virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
348 MachineBasicBlock *FBB,
349 const std::vector<MachineOperand> &Cond) const {
350 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
353 /// BlockHasNoFallThrough - Return true if the specified block does not
354 /// fall-through into its successor block. This is primarily used when a
355 /// branch is unanalyzable. It is useful for things like unconditional
356 /// indirect branches (jump tables).
357 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
361 /// ReverseBranchCondition - Reverses the branch condition of the specified
362 /// condition list, returning false on success and true if it cannot be
364 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
368 /// insertNoop - Insert a noop into the instruction stream at the specified
370 virtual void insertNoop(MachineBasicBlock &MBB,
371 MachineBasicBlock::iterator MI) const {
372 assert(0 && "Target didn't implement insertNoop!");
376 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
378 virtual const TargetRegisterClass *getPointerRegClass() const {
379 assert(0 && "Target didn't implement getPointerRegClass!");
384 } // End llvm namespace