1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
22 class CalleeSavedInfo;
23 class InstrItineraryData;
26 class MachineMemOperand;
30 class ScheduleHazardRecognizer;
32 class TargetRegisterClass;
33 class TargetRegisterInfo;
35 template<class T> class SmallVectorImpl;
38 //---------------------------------------------------------------------------
40 /// TargetInstrInfo - Interface to description of machine instruction set
42 class TargetInstrInfo {
43 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
44 unsigned NumOpcodes; // Number of entries in the desc array
46 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
47 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
49 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
50 virtual ~TargetInstrInfo();
52 unsigned getNumOpcodes() const { return NumOpcodes; }
54 /// get - Return the machine instruction descriptor that corresponds to the
55 /// specified instruction opcode.
57 const TargetInstrDesc &get(unsigned Opcode) const {
58 assert(Opcode < NumOpcodes && "Invalid opcode!");
59 return Descriptors[Opcode];
62 /// isTriviallyReMaterializable - Return true if the instruction is trivially
63 /// rematerializable, meaning it has no side effects and requires no operands
64 /// that aren't always available.
65 bool isTriviallyReMaterializable(const MachineInstr *MI,
66 AliasAnalysis *AA = 0) const {
67 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
68 (MI->getDesc().isRematerializable() &&
69 (isReallyTriviallyReMaterializable(MI, AA) ||
70 isReallyTriviallyReMaterializableGeneric(MI, AA)));
74 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
75 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
76 /// specify whether the instruction is actually trivially rematerializable,
77 /// taking into consideration its operands. This predicate must return false
78 /// if the instruction has any side effects other than producing a value, or
79 /// if it requres any address registers that are not always available.
80 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
81 AliasAnalysis *AA) const {
86 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
87 /// for which the M_REMATERIALIZABLE flag is set and the target hook
88 /// isReallyTriviallyReMaterializable returns false, this function does
89 /// target-independent tests to determine if the instruction is really
90 /// trivially rematerializable.
91 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
92 AliasAnalysis *AA) const;
95 /// isMoveInstr - Return true if the instruction is a register to register
96 /// move and return the source and dest operands and their sub-register
97 /// indices by reference.
98 virtual bool isMoveInstr(const MachineInstr& MI,
99 unsigned& SrcReg, unsigned& DstReg,
100 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
104 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
105 /// extension instruction. That is, it's like a copy where it's legal for the
106 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
107 /// true, then it's expected the pre-extension value is available as a subreg
108 /// of the result register. This also returns the sub-register index in
110 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
111 unsigned &SrcReg, unsigned &DstReg,
112 unsigned &SubIdx) const {
116 /// isIdentityCopy - Return true if the instruction is a copy (or
117 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and
118 /// destination registers are the same.
119 bool isIdentityCopy(const MachineInstr &MI) const {
120 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
121 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
125 if (MI.getOpcode() == TargetOpcode::EXTRACT_SUBREG &&
126 MI.getOperand(0).getReg() == MI.getOperand(1).getReg())
129 if ((MI.getOpcode() == TargetOpcode::INSERT_SUBREG ||
130 MI.getOpcode() == TargetOpcode::SUBREG_TO_REG) &&
131 MI.getOperand(0).getReg() == MI.getOperand(2).getReg())
136 /// isLoadFromStackSlot - If the specified machine instruction is a direct
137 /// load from a stack slot, return the virtual or physical register number of
138 /// the destination along with the FrameIndex of the loaded stack slot. If
139 /// not, return 0. This predicate must return 0 if the instruction has
140 /// any side effects other than loading from the stack slot.
141 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
142 int &FrameIndex) const {
146 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
147 /// stack locations as well. This uses a heuristic so it isn't
148 /// reliable for correctness.
149 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
150 int &FrameIndex) const {
154 /// hasLoadFromStackSlot - If the specified machine instruction has
155 /// a load from a stack slot, return true along with the FrameIndex
156 /// of the loaded stack slot and the machine mem operand containing
157 /// the reference. If not, return false. Unlike
158 /// isLoadFromStackSlot, this returns true for any instructions that
159 /// loads from the stack. This is just a hint, as some cases may be
161 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
162 const MachineMemOperand *&MMO,
163 int &FrameIndex) const {
167 /// isStoreToStackSlot - If the specified machine instruction is a direct
168 /// store to a stack slot, return the virtual or physical register number of
169 /// the source reg along with the FrameIndex of the loaded stack slot. If
170 /// not, return 0. This predicate must return 0 if the instruction has
171 /// any side effects other than storing to the stack slot.
172 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
173 int &FrameIndex) const {
177 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
178 /// stack locations as well. This uses a heuristic so it isn't
179 /// reliable for correctness.
180 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
181 int &FrameIndex) const {
185 /// hasStoreToStackSlot - If the specified machine instruction has a
186 /// store to a stack slot, return true along with the FrameIndex of
187 /// the loaded stack slot and the machine mem operand containing the
188 /// reference. If not, return false. Unlike isStoreToStackSlot,
189 /// this returns true for any instructions that stores to the
190 /// stack. This is just a hint, as some cases may be missed.
191 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
192 const MachineMemOperand *&MMO,
193 int &FrameIndex) const {
197 /// reMaterialize - Re-issue the specified 'original' instruction at the
198 /// specific location targeting a new destination register.
199 /// The register in Orig->getOperand(0).getReg() will be substituted by
200 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
202 virtual void reMaterialize(MachineBasicBlock &MBB,
203 MachineBasicBlock::iterator MI,
204 unsigned DestReg, unsigned SubIdx,
205 const MachineInstr *Orig,
206 const TargetRegisterInfo &TRI) const = 0;
208 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
209 /// two-addrss instruction inserted by two-address pass.
210 virtual void scheduleTwoAddrSource(MachineInstr *SrcMI,
212 const TargetRegisterInfo &TRI) const {
216 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
217 /// MachineFunction::CloneMachineInstr(), but the target may update operands
218 /// that are required to be unique.
220 /// The instruction must be duplicable as indicated by isNotDuplicable().
221 virtual MachineInstr *duplicate(MachineInstr *Orig,
222 MachineFunction &MF) const = 0;
224 /// convertToThreeAddress - This method must be implemented by targets that
225 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
226 /// may be able to convert a two-address instruction into one or more true
227 /// three-address instructions on demand. This allows the X86 target (for
228 /// example) to convert ADD and SHL instructions into LEA instructions if they
229 /// would require register copies due to two-addressness.
231 /// This method returns a null pointer if the transformation cannot be
232 /// performed, otherwise it returns the last new instruction.
234 virtual MachineInstr *
235 convertToThreeAddress(MachineFunction::iterator &MFI,
236 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
240 /// commuteInstruction - If a target has any instructions that are commutable,
241 /// but require converting to a different instruction or making non-trivial
242 /// changes to commute them, this method can overloaded to do this. The
243 /// default implementation of this method simply swaps the first two operands
244 /// of MI and returns it.
246 /// If a target wants to make more aggressive changes, they can construct and
247 /// return a new machine instruction. If an instruction cannot commute, it
248 /// can also return null.
250 /// If NewMI is true, then a new machine instruction must be created.
252 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
253 bool NewMI = false) const = 0;
255 /// findCommutedOpIndices - If specified MI is commutable, return the two
256 /// operand indices that would swap value. Return true if the instruction
257 /// is not in a form which this routine understands.
258 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
259 unsigned &SrcOpIdx2) const = 0;
261 /// produceSameValue - Return true if two machine instructions would produce
262 /// identical values. By default, this is only true when the two instructions
263 /// are deemed identical except for defs.
264 virtual bool produceSameValue(const MachineInstr *MI0,
265 const MachineInstr *MI1) const = 0;
267 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
268 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
269 /// implemented for a target). Upon success, this returns false and returns
270 /// with the following information in various cases:
272 /// 1. If this block ends with no branches (it just falls through to its succ)
273 /// just return false, leaving TBB/FBB null.
274 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
275 /// the destination block.
276 /// 3. If this block ends with a conditional branch and it falls through to a
277 /// successor block, it sets TBB to be the branch destination block and a
278 /// list of operands that evaluate the condition. These operands can be
279 /// passed to other TargetInstrInfo methods to create new branches.
280 /// 4. If this block ends with a conditional branch followed by an
281 /// unconditional branch, it returns the 'true' destination in TBB, the
282 /// 'false' destination in FBB, and a list of operands that evaluate the
283 /// condition. These operands can be passed to other TargetInstrInfo
284 /// methods to create new branches.
286 /// Note that RemoveBranch and InsertBranch must be implemented to support
287 /// cases where this method returns success.
289 /// If AllowModify is true, then this routine is allowed to modify the basic
290 /// block (e.g. delete instructions after the unconditional branch).
292 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
293 MachineBasicBlock *&FBB,
294 SmallVectorImpl<MachineOperand> &Cond,
295 bool AllowModify = false) const {
299 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
300 /// This is only invoked in cases where AnalyzeBranch returns success. It
301 /// returns the number of instructions that were removed.
302 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
303 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
307 /// InsertBranch - Insert branch code into the end of the specified
308 /// MachineBasicBlock. The operands to this method are the same as those
309 /// returned by AnalyzeBranch. This is only invoked in cases where
310 /// AnalyzeBranch returns success. It returns the number of instructions
313 /// It is also invoked by tail merging to add unconditional branches in
314 /// cases where AnalyzeBranch doesn't apply because there was no original
315 /// branch to analyze. At least this much must be implemented, else tail
316 /// merging needs to be disabled.
317 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
318 MachineBasicBlock *FBB,
319 const SmallVectorImpl<MachineOperand> &Cond,
321 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
325 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
326 /// after it, replacing it with an unconditional branch to NewDest. This is
327 /// used by the tail merging pass.
328 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
329 MachineBasicBlock *NewDest) const = 0;
331 /// copyRegToReg - Emit instructions to copy between a pair of registers. It
332 /// returns false if the target does not how to copy between the specified
334 virtual bool copyRegToReg(MachineBasicBlock &MBB,
335 MachineBasicBlock::iterator MI,
336 unsigned DestReg, unsigned SrcReg,
337 const TargetRegisterClass *DestRC,
338 const TargetRegisterClass *SrcRC,
340 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
344 /// storeRegToStackSlot - Store the specified register of the given register
345 /// class to the specified stack frame index. The store instruction is to be
346 /// added to the given machine basic block before the specified machine
347 /// instruction. If isKill is true, the register operand is the last use and
348 /// must be marked kill.
349 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
350 MachineBasicBlock::iterator MI,
351 unsigned SrcReg, bool isKill, int FrameIndex,
352 const TargetRegisterClass *RC,
353 const TargetRegisterInfo *TRI) const {
354 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
357 /// loadRegFromStackSlot - Load the specified register of the given register
358 /// class from the specified stack frame index. The load instruction is to be
359 /// added to the given machine basic block before the specified machine
361 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
362 MachineBasicBlock::iterator MI,
363 unsigned DestReg, int FrameIndex,
364 const TargetRegisterClass *RC,
365 const TargetRegisterInfo *TRI) const {
366 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
369 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
370 /// saved registers and returns true if it isn't possible / profitable to do
371 /// so by issuing a series of store instructions via
372 /// storeRegToStackSlot(). Returns false otherwise.
373 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
374 MachineBasicBlock::iterator MI,
375 const std::vector<CalleeSavedInfo> &CSI,
376 const TargetRegisterInfo *TRI) const {
380 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
381 /// saved registers and returns true if it isn't possible / profitable to do
382 /// so by issuing a series of load instructions via loadRegToStackSlot().
383 /// Returns false otherwise.
384 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
385 MachineBasicBlock::iterator MI,
386 const std::vector<CalleeSavedInfo> &CSI,
387 const TargetRegisterInfo *TRI) const {
391 /// emitFrameIndexDebugValue - Emit a target-dependent form of
392 /// DBG_VALUE encoding the address of a frame index. Addresses would
393 /// normally be lowered the same way as other addresses on the target,
394 /// e.g. in load instructions. For targets that do not support this
395 /// the debug info is simply lost.
396 /// If you add this for a target you should handle this DBG_VALUE in the
397 /// target-specific AsmPrinter code as well; you will probably get invalid
398 /// assembly output if you don't.
399 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
407 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
408 /// slot into the specified machine instruction for the specified operand(s).
409 /// If this is possible, a new instruction is returned with the specified
410 /// operand folded, otherwise NULL is returned. The client is responsible for
411 /// removing the old instruction and adding the new one in the instruction
413 MachineInstr* foldMemoryOperand(MachineFunction &MF,
415 const SmallVectorImpl<unsigned> &Ops,
416 int FrameIndex) const;
418 /// foldMemoryOperand - Same as the previous version except it allows folding
419 /// of any load and store from / to any address, not just from a specific
421 MachineInstr* foldMemoryOperand(MachineFunction &MF,
423 const SmallVectorImpl<unsigned> &Ops,
424 MachineInstr* LoadMI) const;
427 /// foldMemoryOperandImpl - Target-dependent implementation for
428 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
429 /// take care of adding a MachineMemOperand to the newly created instruction.
430 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
432 const SmallVectorImpl<unsigned> &Ops,
433 int FrameIndex) const {
437 /// foldMemoryOperandImpl - Target-dependent implementation for
438 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
439 /// take care of adding a MachineMemOperand to the newly created instruction.
440 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
442 const SmallVectorImpl<unsigned> &Ops,
443 MachineInstr* LoadMI) const {
448 /// canFoldMemoryOperand - Returns true for the specified load / store if
449 /// folding is possible.
451 bool canFoldMemoryOperand(const MachineInstr *MI,
452 const SmallVectorImpl<unsigned> &Ops) const {
456 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
457 /// a store or a load and a store into two or more instruction. If this is
458 /// possible, returns true as well as the new instructions by reference.
459 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
460 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
461 SmallVectorImpl<MachineInstr*> &NewMIs) const{
465 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
466 SmallVectorImpl<SDNode*> &NewNodes) const {
470 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
471 /// instruction after load / store are unfolded from an instruction of the
472 /// specified opcode. It returns zero if the specified unfolding is not
473 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
474 /// index of the operand which will hold the register holding the loaded
476 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
477 bool UnfoldLoad, bool UnfoldStore,
478 unsigned *LoadRegIndex = 0) const {
482 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
483 /// to determine if two loads are loading from the same base address. It
484 /// should only return true if the base pointers are the same and the
485 /// only differences between the two addresses are the offset. It also returns
486 /// the offsets by reference.
487 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
488 int64_t &Offset1, int64_t &Offset2) const {
492 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
493 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
494 /// be scheduled togther. On some targets if two loads are loading from
495 /// addresses in the same cache line, it's better if they are scheduled
496 /// together. This function takes two integers that represent the load offsets
497 /// from the common base address. It returns true if it decides it's desirable
498 /// to schedule the two loads together. "NumLoads" is the number of loads that
499 /// have already been scheduled after Load1.
500 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
501 int64_t Offset1, int64_t Offset2,
502 unsigned NumLoads) const {
506 /// ReverseBranchCondition - Reverses the branch condition of the specified
507 /// condition list, returning false on success and true if it cannot be
510 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
514 /// insertNoop - Insert a noop into the instruction stream at the specified
516 virtual void insertNoop(MachineBasicBlock &MBB,
517 MachineBasicBlock::iterator MI) const;
520 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
521 virtual void getNoopForMachoTarget(MCInst &NopInst) const {
522 // Default to just using 'nop' string.
526 /// isPredicated - Returns true if the instruction is already predicated.
528 virtual bool isPredicated(const MachineInstr *MI) const {
532 /// isUnpredicatedTerminator - Returns true if the instruction is a
533 /// terminator instruction that has not been predicated.
534 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
536 /// PredicateInstruction - Convert the instruction into a predicated
537 /// instruction. It returns true if the operation was successful.
539 bool PredicateInstruction(MachineInstr *MI,
540 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
542 /// SubsumesPredicate - Returns true if the first specified predicate
543 /// subsumes the second, e.g. GE subsumes GT.
545 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
546 const SmallVectorImpl<MachineOperand> &Pred2) const {
550 /// DefinesPredicate - If the specified instruction defines any predicate
551 /// or condition code register(s) used for predication, returns true as well
552 /// as the definition predicate(s) by reference.
553 virtual bool DefinesPredicate(MachineInstr *MI,
554 std::vector<MachineOperand> &Pred) const {
558 /// isPredicable - Return true if the specified instruction can be predicated.
559 /// By default, this returns true for every instruction with a
560 /// PredicateOperand.
561 virtual bool isPredicable(MachineInstr *MI) const {
562 return MI->getDesc().isPredicable();
565 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
566 /// instruction that defines the specified register class.
567 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
571 /// isSchedulingBoundary - Test if the given instruction should be
572 /// considered a scheduling boundary. This primarily includes labels and
574 virtual bool isSchedulingBoundary(const MachineInstr *MI,
575 const MachineBasicBlock *MBB,
576 const MachineFunction &MF) const = 0;
578 /// GetInstSize - Returns the size of the specified Instruction.
580 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
581 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
585 /// GetFunctionSizeInBytes - Returns the size of the specified
588 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
590 /// Measure the specified inline asm to determine an approximation of its
592 virtual unsigned getInlineAsmLength(const char *Str,
593 const MCAsmInfo &MAI) const;
595 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer
596 /// to use for this target when scheduling the machine instructions after
597 /// register allocation.
598 virtual ScheduleHazardRecognizer*
599 CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const = 0;
602 /// TargetInstrInfoImpl - This is the default implementation of
603 /// TargetInstrInfo, which just provides a couple of default implementations
604 /// for various methods. This separated out because it is implemented in
605 /// libcodegen, not in libtarget.
606 class TargetInstrInfoImpl : public TargetInstrInfo {
608 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
609 : TargetInstrInfo(desc, NumOpcodes) {}
611 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
612 MachineBasicBlock *NewDest) const;
613 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
614 bool NewMI = false) const;
615 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
616 unsigned &SrcOpIdx2) const;
617 virtual bool PredicateInstruction(MachineInstr *MI,
618 const SmallVectorImpl<MachineOperand> &Pred) const;
619 virtual void reMaterialize(MachineBasicBlock &MBB,
620 MachineBasicBlock::iterator MI,
621 unsigned DestReg, unsigned SubReg,
622 const MachineInstr *Orig,
623 const TargetRegisterInfo &TRI) const;
624 virtual MachineInstr *duplicate(MachineInstr *Orig,
625 MachineFunction &MF) const;
626 virtual bool produceSameValue(const MachineInstr *MI0,
627 const MachineInstr *MI1) const;
628 virtual bool isSchedulingBoundary(const MachineInstr *MI,
629 const MachineBasicBlock *MBB,
630 const MachineFunction &MF) const;
631 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
633 virtual ScheduleHazardRecognizer *
634 CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const;
637 } // End llvm namespace