1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/CodeGen/MachineCombinerPattern.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
26 class InstrItineraryData;
29 class MachineMemOperand;
30 class MachineRegisterInfo;
34 class MCSymbolRefExpr;
36 class ScheduleHazardRecognizer;
39 class TargetRegisterClass;
40 class TargetRegisterInfo;
41 class BranchProbability;
42 class TargetSubtargetInfo;
45 template<class T> class SmallVectorImpl;
48 //---------------------------------------------------------------------------
50 /// TargetInstrInfo - Interface to description of machine instruction set
52 class TargetInstrInfo : public MCInstrInfo {
53 TargetInstrInfo(const TargetInstrInfo &) = delete;
54 void operator=(const TargetInstrInfo &) = delete;
56 TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u)
57 : CallFrameSetupOpcode(CFSetupOpcode),
58 CallFrameDestroyOpcode(CFDestroyOpcode) {
61 virtual ~TargetInstrInfo();
63 /// Given a machine instruction descriptor, returns the register
64 /// class constraint for OpNum, or NULL.
65 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
67 const TargetRegisterInfo *TRI,
68 const MachineFunction &MF) const;
70 /// Return true if the instruction is trivially rematerializable, meaning it
71 /// has no side effects and requires no operands that aren't always available.
72 /// This means the only allowed uses are constants and unallocatable physical
73 /// registers so that the instructions result is independent of the place
75 bool isTriviallyReMaterializable(const MachineInstr *MI,
76 AliasAnalysis *AA = nullptr) const {
77 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
78 (MI->getDesc().isRematerializable() &&
79 (isReallyTriviallyReMaterializable(MI, AA) ||
80 isReallyTriviallyReMaterializableGeneric(MI, AA)));
84 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
85 /// set, this hook lets the target specify whether the instruction is actually
86 /// trivially rematerializable, taking into consideration its operands. This
87 /// predicate must return false if the instruction has any side effects other
88 /// than producing a value, or if it requres any address registers that are
89 /// not always available.
90 /// Requirements must be check as stated in isTriviallyReMaterializable() .
91 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
92 AliasAnalysis *AA) const {
97 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
98 /// set and the target hook isReallyTriviallyReMaterializable returns false,
99 /// this function does target-independent tests to determine if the
100 /// instruction is really trivially rematerializable.
101 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
102 AliasAnalysis *AA) const;
105 /// These methods return the opcode of the frame setup/destroy instructions
106 /// if they exist (-1 otherwise). Some targets use pseudo instructions in
107 /// order to abstract away the difference between operating with a frame
108 /// pointer and operating without, through the use of these two instructions.
110 unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
111 unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
113 /// Returns the actual stack pointer adjustment made by an instruction
114 /// as part of a call sequence. By default, only call frame setup/destroy
115 /// instructions adjust the stack, but targets may want to override this
116 /// to enable more fine-grained adjustment, or adjust by a different value.
117 virtual int getSPAdjust(const MachineInstr *MI) const;
119 /// Return true if the instruction is a "coalescable" extension instruction.
120 /// That is, it's like a copy where it's legal for the source to overlap the
121 /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
122 /// expected the pre-extension value is available as a subreg of the result
123 /// register. This also returns the sub-register index in SubIdx.
124 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
125 unsigned &SrcReg, unsigned &DstReg,
126 unsigned &SubIdx) const {
130 /// If the specified machine instruction is a direct
131 /// load from a stack slot, return the virtual or physical register number of
132 /// the destination along with the FrameIndex of the loaded stack slot. If
133 /// not, return 0. This predicate must return 0 if the instruction has
134 /// any side effects other than loading from the stack slot.
135 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
136 int &FrameIndex) const {
140 /// Check for post-frame ptr elimination stack locations as well.
141 /// This uses a heuristic so it isn't reliable for correctness.
142 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
143 int &FrameIndex) const {
147 /// If the specified machine instruction has a load from a stack slot,
148 /// return true along with the FrameIndex of the loaded stack slot and the
149 /// machine mem operand containing the reference.
150 /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
151 /// any instructions that loads from the stack. This is just a hint, as some
152 /// cases may be missed.
153 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
154 const MachineMemOperand *&MMO,
155 int &FrameIndex) const;
157 /// If the specified machine instruction is a direct
158 /// store to a stack slot, return the virtual or physical register number of
159 /// the source reg along with the FrameIndex of the loaded stack slot. If
160 /// not, return 0. This predicate must return 0 if the instruction has
161 /// any side effects other than storing to the stack slot.
162 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
163 int &FrameIndex) const {
167 /// Check for post-frame ptr elimination stack locations as well.
168 /// This uses a heuristic, so it isn't reliable for correctness.
169 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
170 int &FrameIndex) const {
174 /// If the specified machine instruction has a store to a stack slot,
175 /// return true along with the FrameIndex of the loaded stack slot and the
176 /// machine mem operand containing the reference.
177 /// If not, return false. Unlike isStoreToStackSlot,
178 /// this returns true for any instructions that stores to the
179 /// stack. This is just a hint, as some cases may be missed.
180 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
181 const MachineMemOperand *&MMO,
182 int &FrameIndex) const;
184 /// Return true if the specified machine instruction
185 /// is a copy of one stack slot to another and has no other effect.
186 /// Provide the identity of the two frame indices.
187 virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
188 int &SrcFrameIndex) const {
192 /// Compute the size in bytes and offset within a stack slot of a spilled
193 /// register or subregister.
195 /// \param [out] Size in bytes of the spilled value.
196 /// \param [out] Offset in bytes within the stack slot.
197 /// \returns true if both Size and Offset are successfully computed.
199 /// Not all subregisters have computable spill slots. For example,
200 /// subregisters registers may not be byte-sized, and a pair of discontiguous
201 /// subregisters has no single offset.
203 /// Targets with nontrivial bigendian implementations may need to override
204 /// this, particularly to support spilled vector registers.
205 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
206 unsigned &Size, unsigned &Offset,
207 const MachineFunction &MF) const;
209 /// Return true if the instruction is as cheap as a move instruction.
211 /// Targets for different archs need to override this, and different
212 /// micro-architectures can also be finely tuned inside.
213 virtual bool isAsCheapAsAMove(const MachineInstr *MI) const {
214 return MI->isAsCheapAsAMove();
217 /// Re-issue the specified 'original' instruction at the
218 /// specific location targeting a new destination register.
219 /// The register in Orig->getOperand(0).getReg() will be substituted by
220 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
222 virtual void reMaterialize(MachineBasicBlock &MBB,
223 MachineBasicBlock::iterator MI,
224 unsigned DestReg, unsigned SubIdx,
225 const MachineInstr *Orig,
226 const TargetRegisterInfo &TRI) const;
228 /// Create a duplicate of the Orig instruction in MF. This is like
229 /// MachineFunction::CloneMachineInstr(), but the target may update operands
230 /// that are required to be unique.
232 /// The instruction must be duplicable as indicated by isNotDuplicable().
233 virtual MachineInstr *duplicate(MachineInstr *Orig,
234 MachineFunction &MF) const;
236 /// This method must be implemented by targets that
237 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
238 /// may be able to convert a two-address instruction into one or more true
239 /// three-address instructions on demand. This allows the X86 target (for
240 /// example) to convert ADD and SHL instructions into LEA instructions if they
241 /// would require register copies due to two-addressness.
243 /// This method returns a null pointer if the transformation cannot be
244 /// performed, otherwise it returns the last new instruction.
246 virtual MachineInstr *
247 convertToThreeAddress(MachineFunction::iterator &MFI,
248 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
252 /// If a target has any instructions that are commutable but require
253 /// converting to different instructions or making non-trivial changes to
254 /// commute them, this method can overloaded to do that.
255 /// The default implementation simply swaps the commutable operands.
256 /// If NewMI is false, MI is modified in place and returned; otherwise, a
257 /// new machine instruction is created and returned. Do not call this
258 /// method for a non-commutable instruction, but there may be some cases
259 /// where this method fails and returns null.
260 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
261 bool NewMI = false) const;
263 /// If specified MI is commutable, return the two operand indices that would
264 /// swap value. Return false if the instruction
265 /// is not in a form which this routine understands.
266 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
267 unsigned &SrcOpIdx2) const;
269 /// A pair composed of a register and a sub-register index.
270 /// Used to give some type checking when modeling Reg:SubReg.
271 struct RegSubRegPair {
274 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
275 : Reg(Reg), SubReg(SubReg) {}
277 /// A pair composed of a pair of a register and a sub-register index,
278 /// and another sub-register index.
279 /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
280 struct RegSubRegPairAndIdx : RegSubRegPair {
282 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
284 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
287 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
289 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
290 /// the list is modeled as <Reg:SubReg, SubIdx>.
291 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
293 /// - vreg1:sub1, sub0
294 /// - vreg2<:0>, sub1
296 /// \returns true if it is possible to build such an input sequence
297 /// with the pair \p MI, \p DefIdx. False otherwise.
299 /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
301 /// \note The generic implementation does not provide any support for
302 /// MI.isRegSequenceLike(). In other words, one has to override
303 /// getRegSequenceLikeInputs for target specific instructions.
305 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
306 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
308 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
310 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
311 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
312 /// - vreg1:sub1, sub0
314 /// \returns true if it is possible to build such an input sequence
315 /// with the pair \p MI, \p DefIdx. False otherwise.
317 /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
319 /// \note The generic implementation does not provide any support for
320 /// MI.isExtractSubregLike(). In other words, one has to override
321 /// getExtractSubregLikeInputs for target specific instructions.
323 getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
324 RegSubRegPairAndIdx &InputReg) const;
326 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
328 /// \p [out] BaseReg and \p [out] InsertedReg contain
329 /// the equivalent inputs of INSERT_SUBREG.
330 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
331 /// - BaseReg: vreg0:sub0
332 /// - InsertedReg: vreg1:sub1, sub3
334 /// \returns true if it is possible to build such an input sequence
335 /// with the pair \p MI, \p DefIdx. False otherwise.
337 /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
339 /// \note The generic implementation does not provide any support for
340 /// MI.isInsertSubregLike(). In other words, one has to override
341 /// getInsertSubregLikeInputs for target specific instructions.
343 getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
344 RegSubRegPair &BaseReg,
345 RegSubRegPairAndIdx &InsertedReg) const;
348 /// Return true if two machine instructions would produce identical values.
349 /// By default, this is only true when the two instructions
350 /// are deemed identical except for defs. If this function is called when the
351 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
352 /// aggressive checks.
353 virtual bool produceSameValue(const MachineInstr *MI0,
354 const MachineInstr *MI1,
355 const MachineRegisterInfo *MRI = nullptr) const;
357 /// Analyze the branching code at the end of MBB, returning
358 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
359 /// implemented for a target). Upon success, this returns false and returns
360 /// with the following information in various cases:
362 /// 1. If this block ends with no branches (it just falls through to its succ)
363 /// just return false, leaving TBB/FBB null.
364 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
365 /// the destination block.
366 /// 3. If this block ends with a conditional branch and it falls through to a
367 /// successor block, it sets TBB to be the branch destination block and a
368 /// list of operands that evaluate the condition. These operands can be
369 /// passed to other TargetInstrInfo methods to create new branches.
370 /// 4. If this block ends with a conditional branch followed by an
371 /// unconditional branch, it returns the 'true' destination in TBB, the
372 /// 'false' destination in FBB, and a list of operands that evaluate the
373 /// condition. These operands can be passed to other TargetInstrInfo
374 /// methods to create new branches.
376 /// Note that RemoveBranch and InsertBranch must be implemented to support
377 /// cases where this method returns success.
379 /// If AllowModify is true, then this routine is allowed to modify the basic
380 /// block (e.g. delete instructions after the unconditional branch).
382 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
383 MachineBasicBlock *&FBB,
384 SmallVectorImpl<MachineOperand> &Cond,
385 bool AllowModify = false) const {
389 /// Remove the branching code at the end of the specific MBB.
390 /// This is only invoked in cases where AnalyzeBranch returns success. It
391 /// returns the number of instructions that were removed.
392 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
393 llvm_unreachable("Target didn't implement TargetInstrInfo::RemoveBranch!");
396 /// Insert branch code into the end of the specified MachineBasicBlock.
397 /// The operands to this method are the same as those
398 /// returned by AnalyzeBranch. This is only invoked in cases where
399 /// AnalyzeBranch returns success. It returns the number of instructions
402 /// It is also invoked by tail merging to add unconditional branches in
403 /// cases where AnalyzeBranch doesn't apply because there was no original
404 /// branch to analyze. At least this much must be implemented, else tail
405 /// merging needs to be disabled.
406 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
407 MachineBasicBlock *FBB,
408 const SmallVectorImpl<MachineOperand> &Cond,
410 llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!");
413 /// Delete the instruction OldInst and everything after it, replacing it with
414 /// an unconditional branch to NewDest. This is used by the tail merging pass.
415 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
416 MachineBasicBlock *NewDest) const;
418 /// Get an instruction that performs an unconditional branch to the given
421 getUnconditionalBranch(MCInst &MI,
422 const MCSymbolRefExpr *BranchTarget) const {
423 llvm_unreachable("Target didn't implement "
424 "TargetInstrInfo::getUnconditionalBranch!");
427 /// Get a machine trap instruction.
428 virtual void getTrap(MCInst &MI) const {
429 llvm_unreachable("Target didn't implement TargetInstrInfo::getTrap!");
432 /// Get a number of bytes that suffices to hold
433 /// either the instruction returned by getUnconditionalBranch or the
434 /// instruction returned by getTrap. This only makes sense because
435 /// getUnconditionalBranch returns a single, specific instruction. This
436 /// information is needed by the jumptable construction code, since it must
437 /// decide how many bytes to use for a jumptable entry so it can generate the
440 /// Note that if the jumptable instruction requires alignment, then that
441 /// alignment should be factored into this required bound so that the
442 /// resulting bound gives the right alignment for the instruction.
443 virtual unsigned getJumpInstrTableEntryBound() const {
444 // This method gets called by LLVMTargetMachine always, so it can't fail
445 // just because there happens to be no implementation for this target.
446 // Any code that tries to use a jumptable annotation without defining
447 // getUnconditionalBranch on the appropriate Target will fail anyway, and
448 // the value returned here won't matter in that case.
452 /// Return true if it's legal to split the given basic
453 /// block at the specified instruction (i.e. instruction would be the start
454 /// of a new basic block).
455 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
456 MachineBasicBlock::iterator MBBI) const {
460 /// Return true if it's profitable to predicate
461 /// instructions with accumulated instruction latency of "NumCycles"
462 /// of the specified basic block, where the probability of the instructions
463 /// being executed is given by Probability, and Confidence is a measure
464 /// of our confidence that it will be properly predicted.
466 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
467 unsigned ExtraPredCycles,
468 const BranchProbability &Probability) const {
472 /// Second variant of isProfitableToIfCvt. This one
473 /// checks for the case where two basic blocks from true and false path
474 /// of a if-then-else (diamond) are predicated on mutally exclusive
475 /// predicates, where the probability of the true path being taken is given
476 /// by Probability, and Confidence is a measure of our confidence that it
477 /// will be properly predicted.
479 isProfitableToIfCvt(MachineBasicBlock &TMBB,
480 unsigned NumTCycles, unsigned ExtraTCycles,
481 MachineBasicBlock &FMBB,
482 unsigned NumFCycles, unsigned ExtraFCycles,
483 const BranchProbability &Probability) const {
487 /// Return true if it's profitable for if-converter to duplicate instructions
488 /// of specified accumulated instruction latencies in the specified MBB to
489 /// enable if-conversion.
490 /// The probability of the instructions being executed is given by
491 /// Probability, and Confidence is a measure of our confidence that it
492 /// will be properly predicted.
494 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
495 const BranchProbability &Probability) const {
499 /// Return true if it's profitable to unpredicate
500 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
501 /// exclusive predicates.
509 /// This may be profitable is conditional instructions are always executed.
510 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
511 MachineBasicBlock &FMBB) const {
515 /// Return true if it is possible to insert a select
516 /// instruction that chooses between TrueReg and FalseReg based on the
517 /// condition code in Cond.
519 /// When successful, also return the latency in cycles from TrueReg,
520 /// FalseReg, and Cond to the destination register. In most cases, a select
521 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
523 /// Some x86 implementations have 2-cycle cmov instructions.
525 /// @param MBB Block where select instruction would be inserted.
526 /// @param Cond Condition returned by AnalyzeBranch.
527 /// @param TrueReg Virtual register to select when Cond is true.
528 /// @param FalseReg Virtual register to select when Cond is false.
529 /// @param CondCycles Latency from Cond+Branch to select output.
530 /// @param TrueCycles Latency from TrueReg to select output.
531 /// @param FalseCycles Latency from FalseReg to select output.
532 virtual bool canInsertSelect(const MachineBasicBlock &MBB,
533 const SmallVectorImpl<MachineOperand> &Cond,
534 unsigned TrueReg, unsigned FalseReg,
536 int &TrueCycles, int &FalseCycles) const {
540 /// Insert a select instruction into MBB before I that will copy TrueReg to
541 /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
543 /// This function can only be called after canInsertSelect() returned true.
544 /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
545 /// that the same flags or registers required by Cond are available at the
548 /// @param MBB Block where select instruction should be inserted.
549 /// @param I Insertion point.
550 /// @param DL Source location for debugging.
551 /// @param DstReg Virtual register to be defined by select instruction.
552 /// @param Cond Condition as computed by AnalyzeBranch.
553 /// @param TrueReg Virtual register to copy when Cond is true.
554 /// @param FalseReg Virtual register to copy when Cons is false.
555 virtual void insertSelect(MachineBasicBlock &MBB,
556 MachineBasicBlock::iterator I, DebugLoc DL,
558 const SmallVectorImpl<MachineOperand> &Cond,
559 unsigned TrueReg, unsigned FalseReg) const {
560 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
563 /// Analyze the given select instruction, returning true if
564 /// it cannot be understood. It is assumed that MI->isSelect() is true.
566 /// When successful, return the controlling condition and the operands that
567 /// determine the true and false result values.
569 /// Result = SELECT Cond, TrueOp, FalseOp
571 /// Some targets can optimize select instructions, for example by predicating
572 /// the instruction defining one of the operands. Such targets should set
575 /// @param MI Select instruction to analyze.
576 /// @param Cond Condition controlling the select.
577 /// @param TrueOp Operand number of the value selected when Cond is true.
578 /// @param FalseOp Operand number of the value selected when Cond is false.
579 /// @param Optimizable Returned as true if MI is optimizable.
580 /// @returns False on success.
581 virtual bool analyzeSelect(const MachineInstr *MI,
582 SmallVectorImpl<MachineOperand> &Cond,
583 unsigned &TrueOp, unsigned &FalseOp,
584 bool &Optimizable) const {
585 assert(MI && MI->getDesc().isSelect() && "MI must be a select instruction");
589 /// Given a select instruction that was understood by
590 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
591 /// merging it with one of its operands. Returns NULL on failure.
593 /// When successful, returns the new select instruction. The client is
594 /// responsible for deleting MI.
596 /// If both sides of the select can be optimized, PreferFalse is used to pick
599 /// @param MI Optimizable select instruction.
600 /// @param NewMIs Set that record all MIs in the basic block up to \p
601 /// MI. Has to be updated with any newly created MI or deleted ones.
602 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
603 /// @returns Optimized instruction or NULL.
604 virtual MachineInstr *optimizeSelect(MachineInstr *MI,
605 SmallPtrSetImpl<MachineInstr *> &NewMIs,
606 bool PreferFalse = false) const {
607 // This function must be implemented if Optimizable is ever set.
608 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
611 /// Emit instructions to copy a pair of physical registers.
613 /// This function should support copies within any legal register class as
614 /// well as any cross-class copies created during instruction selection.
616 /// The source and destination registers may overlap, which may require a
617 /// careful implementation when multiple copy instructions are required for
618 /// large registers. See for example the ARM target.
619 virtual void copyPhysReg(MachineBasicBlock &MBB,
620 MachineBasicBlock::iterator MI, DebugLoc DL,
621 unsigned DestReg, unsigned SrcReg,
622 bool KillSrc) const {
623 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
626 /// Store the specified register of the given register class to the specified
627 /// stack frame index. The store instruction is to be added to the given
628 /// machine basic block before the specified machine instruction. If isKill
629 /// is true, the register operand is the last use and must be marked kill.
630 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
631 MachineBasicBlock::iterator MI,
632 unsigned SrcReg, bool isKill, int FrameIndex,
633 const TargetRegisterClass *RC,
634 const TargetRegisterInfo *TRI) const {
635 llvm_unreachable("Target didn't implement "
636 "TargetInstrInfo::storeRegToStackSlot!");
639 /// Load the specified register of the given register class from the specified
640 /// stack frame index. The load instruction is to be added to the given
641 /// machine basic block before the specified machine instruction.
642 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
643 MachineBasicBlock::iterator MI,
644 unsigned DestReg, int FrameIndex,
645 const TargetRegisterClass *RC,
646 const TargetRegisterInfo *TRI) const {
647 llvm_unreachable("Target didn't implement "
648 "TargetInstrInfo::loadRegFromStackSlot!");
651 /// This function is called for all pseudo instructions
652 /// that remain after register allocation. Many pseudo instructions are
653 /// created to help register allocation. This is the place to convert them
654 /// into real instructions. The target can edit MI in place, or it can insert
655 /// new instructions and erase MI. The function should return true if
656 /// anything was changed.
657 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
661 /// Attempt to fold a load or store of the specified stack
662 /// slot into the specified machine instruction for the specified operand(s).
663 /// If this is possible, a new instruction is returned with the specified
664 /// operand folded, otherwise NULL is returned.
665 /// The new instruction is inserted before MI, and the client is responsible
666 /// for removing the old instruction.
667 MachineInstr *foldMemoryOperand(MachineBasicBlock::iterator MI,
668 ArrayRef<unsigned> Ops, int FrameIndex) const;
670 /// Same as the previous version except it allows folding of any load and
671 /// store from / to any address, not just from a specific stack slot.
672 MachineInstr *foldMemoryOperand(MachineBasicBlock::iterator MI,
673 ArrayRef<unsigned> Ops,
674 MachineInstr *LoadMI) const;
676 /// Return true when there is potentially a faster code sequence
677 /// for an instruction chain ending in \p Root. All potential patterns are
678 /// returned in the \p Pattern vector. Pattern should be sorted in priority
679 /// order since the pattern evaluator stops checking as soon as it finds a
681 /// \param Root - Instruction that could be combined with one of its operands
682 /// \param Pattern - Vector of possible combination pattern
683 virtual bool hasPattern(
685 SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Pattern) const {
689 /// When hasPattern() finds a pattern this function generates the instructions
690 /// that could replace the original code sequence. The client has to decide
691 /// whether the actual replacement is beneficial or not.
692 /// \param Root - Instruction that could be combined with one of its operands
693 /// \param P - Combination pattern for Root
694 /// \param InsInstrs - Vector of new instructions that implement P
695 /// \param DelInstrs - Old instructions, including Root, that could be
696 /// replaced by InsInstr
697 /// \param InstrIdxForVirtReg - map of virtual register to instruction in
698 /// InsInstr that defines it
699 virtual void genAlternativeCodeSequence(
700 MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P,
701 SmallVectorImpl<MachineInstr *> &InsInstrs,
702 SmallVectorImpl<MachineInstr *> &DelInstrs,
703 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
707 /// Return true when a target supports MachineCombiner.
708 virtual bool useMachineCombiner() const { return false; }
711 /// Target-dependent implementation for foldMemoryOperand.
712 /// Target-independent code in foldMemoryOperand will
713 /// take care of adding a MachineMemOperand to the newly created instruction.
714 /// The instruction and any auxiliary instructions necessary will be inserted
716 virtual MachineInstr *foldMemoryOperandImpl(
717 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
718 MachineBasicBlock::iterator InsertPt, int FrameIndex) const {
722 /// Target-dependent implementation for foldMemoryOperand.
723 /// Target-independent code in foldMemoryOperand will
724 /// take care of adding a MachineMemOperand to the newly created instruction.
725 /// The instruction and any auxiliary instructions necessary will be inserted
727 virtual MachineInstr *foldMemoryOperandImpl(
728 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
729 MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const {
733 /// \brief Target-dependent implementation of getRegSequenceInputs.
735 /// \returns true if it is possible to build the equivalent
736 /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
738 /// \pre MI.isRegSequenceLike().
740 /// \see TargetInstrInfo::getRegSequenceInputs.
741 virtual bool getRegSequenceLikeInputs(
742 const MachineInstr &MI, unsigned DefIdx,
743 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
747 /// \brief Target-dependent implementation of getExtractSubregInputs.
749 /// \returns true if it is possible to build the equivalent
750 /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
752 /// \pre MI.isExtractSubregLike().
754 /// \see TargetInstrInfo::getExtractSubregInputs.
755 virtual bool getExtractSubregLikeInputs(
756 const MachineInstr &MI, unsigned DefIdx,
757 RegSubRegPairAndIdx &InputReg) const {
761 /// \brief Target-dependent implementation of getInsertSubregInputs.
763 /// \returns true if it is possible to build the equivalent
764 /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
766 /// \pre MI.isInsertSubregLike().
768 /// \see TargetInstrInfo::getInsertSubregInputs.
770 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
771 RegSubRegPair &BaseReg,
772 RegSubRegPairAndIdx &InsertedReg) const {
777 /// Returns true for the specified load / store if folding is possible.
778 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
779 ArrayRef<unsigned> Ops) const;
781 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
782 /// a store or a load and a store into two or more instruction. If this is
783 /// possible, returns true as well as the new instructions by reference.
784 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
785 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
786 SmallVectorImpl<MachineInstr*> &NewMIs) const{
790 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
791 SmallVectorImpl<SDNode*> &NewNodes) const {
795 /// Returns the opcode of the would be new
796 /// instruction after load / store are unfolded from an instruction of the
797 /// specified opcode. It returns zero if the specified unfolding is not
798 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
799 /// index of the operand which will hold the register holding the loaded
801 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
802 bool UnfoldLoad, bool UnfoldStore,
803 unsigned *LoadRegIndex = nullptr) const {
807 /// This is used by the pre-regalloc scheduler to determine if two loads are
808 /// loading from the same base address. It should only return true if the base
809 /// pointers are the same and the only differences between the two addresses
810 /// are the offset. It also returns the offsets by reference.
811 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
812 int64_t &Offset1, int64_t &Offset2) const {
816 /// This is a used by the pre-regalloc scheduler to determine (in conjunction
817 /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
818 /// On some targets if two loads are loading from
819 /// addresses in the same cache line, it's better if they are scheduled
820 /// together. This function takes two integers that represent the load offsets
821 /// from the common base address. It returns true if it decides it's desirable
822 /// to schedule the two loads together. "NumLoads" is the number of loads that
823 /// have already been scheduled after Load1.
824 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
825 int64_t Offset1, int64_t Offset2,
826 unsigned NumLoads) const {
830 /// Get the base register and byte offset of a load/store instr.
831 virtual bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
832 unsigned &BaseReg, unsigned &Offset,
833 const TargetRegisterInfo *TRI) const {
837 virtual bool enableClusterLoads() const { return false; }
839 virtual bool shouldClusterLoads(MachineInstr *FirstLdSt,
840 MachineInstr *SecondLdSt,
841 unsigned NumLoads) const {
845 /// Can this target fuse the given instructions if they are scheduled
847 virtual bool shouldScheduleAdjacent(MachineInstr* First,
848 MachineInstr *Second) const {
852 /// Reverses the branch condition of the specified condition list,
853 /// returning false on success and true if it cannot be reversed.
855 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
859 /// Insert a noop into the instruction stream at the specified point.
860 virtual void insertNoop(MachineBasicBlock &MBB,
861 MachineBasicBlock::iterator MI) const;
864 /// Return the noop instruction to use for a noop.
865 virtual void getNoopForMachoTarget(MCInst &NopInst) const;
868 /// Returns true if the instruction is already predicated.
869 virtual bool isPredicated(const MachineInstr *MI) const {
873 /// Returns true if the instruction is a
874 /// terminator instruction that has not been predicated.
875 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
877 /// Convert the instruction into a predicated instruction.
878 /// It returns true if the operation was successful.
880 bool PredicateInstruction(MachineInstr *MI,
881 const SmallVectorImpl<MachineOperand> &Pred) const;
883 /// Returns true if the first specified predicate
884 /// subsumes the second, e.g. GE subsumes GT.
886 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
887 const SmallVectorImpl<MachineOperand> &Pred2) const {
891 /// If the specified instruction defines any predicate
892 /// or condition code register(s) used for predication, returns true as well
893 /// as the definition predicate(s) by reference.
894 virtual bool DefinesPredicate(MachineInstr *MI,
895 std::vector<MachineOperand> &Pred) const {
899 /// Return true if the specified instruction can be predicated.
900 /// By default, this returns true for every instruction with a
901 /// PredicateOperand.
902 virtual bool isPredicable(MachineInstr *MI) const {
903 return MI->getDesc().isPredicable();
906 /// Return true if it's safe to move a machine
907 /// instruction that defines the specified register class.
908 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
912 /// Test if the given instruction should be considered a scheduling boundary.
913 /// This primarily includes labels and terminators.
914 virtual bool isSchedulingBoundary(const MachineInstr *MI,
915 const MachineBasicBlock *MBB,
916 const MachineFunction &MF) const;
918 /// Measure the specified inline asm to determine an approximation of its
920 virtual unsigned getInlineAsmLength(const char *Str,
921 const MCAsmInfo &MAI) const;
923 /// Allocate and return a hazard recognizer to use for this target when
924 /// scheduling the machine instructions before register allocation.
925 virtual ScheduleHazardRecognizer*
926 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
927 const ScheduleDAG *DAG) const;
929 /// Allocate and return a hazard recognizer to use for this target when
930 /// scheduling the machine instructions before register allocation.
931 virtual ScheduleHazardRecognizer*
932 CreateTargetMIHazardRecognizer(const InstrItineraryData*,
933 const ScheduleDAG *DAG) const;
935 /// Allocate and return a hazard recognizer to use for this target when
936 /// scheduling the machine instructions after register allocation.
937 virtual ScheduleHazardRecognizer*
938 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
939 const ScheduleDAG *DAG) const;
941 /// Provide a global flag for disabling the PreRA hazard recognizer that
942 /// targets may choose to honor.
943 bool usePreRAHazardRecognizer() const;
945 /// For a comparison instruction, return the source registers
946 /// in SrcReg and SrcReg2 if having two register operands, and the value it
947 /// compares against in CmpValue. Return true if the comparison instruction
949 virtual bool analyzeCompare(const MachineInstr *MI,
950 unsigned &SrcReg, unsigned &SrcReg2,
951 int &Mask, int &Value) const {
955 /// See if the comparison instruction can be converted
956 /// into something more efficient. E.g., on ARM most instructions can set the
957 /// flags register, obviating the need for a separate CMP.
958 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr,
959 unsigned SrcReg, unsigned SrcReg2,
961 const MachineRegisterInfo *MRI) const {
964 virtual bool optimizeCondBranch(MachineInstr *MI) const { return false; }
966 /// Try to remove the load by folding it to a register operand at the use.
967 /// We fold the load instructions if and only if the
968 /// def and use are in the same BB. We only look at one load and see
969 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
970 /// defined by the load we are trying to fold. DefMI returns the machine
971 /// instruction that defines FoldAsLoadDefReg, and the function returns
972 /// the machine instruction generated due to folding.
973 virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,
974 const MachineRegisterInfo *MRI,
975 unsigned &FoldAsLoadDefReg,
976 MachineInstr *&DefMI) const {
980 /// 'Reg' is known to be defined by a move immediate instruction,
981 /// try to fold the immediate into the use instruction.
982 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
983 /// then the caller may assume that DefMI has been erased from its parent
984 /// block. The caller may assume that it will not be erased by this
985 /// function otherwise.
986 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
987 unsigned Reg, MachineRegisterInfo *MRI) const {
991 /// Return the number of u-operations the given machine
992 /// instruction will be decoded to on the target cpu. The itinerary's
993 /// IssueWidth is the number of microops that can be dispatched each
994 /// cycle. An instruction with zero microops takes no dispatch resources.
995 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
996 const MachineInstr *MI) const;
998 /// Return true for pseudo instructions that don't consume any
999 /// machine resources in their current form. These are common cases that the
1000 /// scheduler should consider free, rather than conservatively handling them
1001 /// as instructions with no itinerary.
1002 bool isZeroCost(unsigned Opcode) const {
1003 return Opcode <= TargetOpcode::COPY;
1006 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1007 SDNode *DefNode, unsigned DefIdx,
1008 SDNode *UseNode, unsigned UseIdx) const;
1010 /// Compute and return the use operand latency of a given pair of def and use.
1011 /// In most cases, the static scheduling itinerary was enough to determine the
1012 /// operand latency. But it may not be possible for instructions with variable
1013 /// number of defs / uses.
1015 /// This is a raw interface to the itinerary that may be directly overridden
1016 /// by a target. Use computeOperandLatency to get the best estimate of
1018 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1019 const MachineInstr *DefMI, unsigned DefIdx,
1020 const MachineInstr *UseMI,
1021 unsigned UseIdx) const;
1023 /// Compute and return the latency of the given data
1024 /// dependent def and use when the operand indices are already known.
1025 unsigned computeOperandLatency(const InstrItineraryData *ItinData,
1026 const MachineInstr *DefMI, unsigned DefIdx,
1027 const MachineInstr *UseMI, unsigned UseIdx)
1030 /// Compute the instruction latency of a given instruction.
1031 /// If the instruction has higher cost when predicated, it's returned via
1033 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1034 const MachineInstr *MI,
1035 unsigned *PredCost = nullptr) const;
1037 virtual unsigned getPredicationCost(const MachineInstr *MI) const;
1039 virtual int getInstrLatency(const InstrItineraryData *ItinData,
1040 SDNode *Node) const;
1042 /// Return the default expected latency for a def based on it's opcode.
1043 unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1044 const MachineInstr *DefMI) const;
1046 int computeDefOperandLatency(const InstrItineraryData *ItinData,
1047 const MachineInstr *DefMI) const;
1049 /// Return true if this opcode has high latency to its result.
1050 virtual bool isHighLatencyDef(int opc) const { return false; }
1052 /// Compute operand latency between a def of 'Reg'
1053 /// and a use in the current loop. Return true if the target considered
1054 /// it 'high'. This is used by optimization passes such as machine LICM to
1055 /// determine whether it makes sense to hoist an instruction out even in a
1056 /// high register pressure situation.
1058 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
1059 const MachineRegisterInfo *MRI,
1060 const MachineInstr *DefMI, unsigned DefIdx,
1061 const MachineInstr *UseMI, unsigned UseIdx) const {
1065 /// Compute operand latency of a def of 'Reg'. Return true
1066 /// if the target considered it 'low'.
1068 bool hasLowDefLatency(const InstrItineraryData *ItinData,
1069 const MachineInstr *DefMI, unsigned DefIdx) const;
1071 /// Perform target-specific instruction verification.
1073 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const {
1077 /// Return the current execution domain and bit mask of
1078 /// possible domains for instruction.
1080 /// Some micro-architectures have multiple execution domains, and multiple
1081 /// opcodes that perform the same operation in different domains. For
1082 /// example, the x86 architecture provides the por, orps, and orpd
1083 /// instructions that all do the same thing. There is a latency penalty if a
1084 /// register is written in one domain and read in another.
1086 /// This function returns a pair (domain, mask) containing the execution
1087 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1088 /// function can be used to change the opcode to one of the domains in the
1089 /// bit mask. Instructions whose execution domain can't be changed should
1090 /// return a 0 mask.
1092 /// The execution domain numbers don't have any special meaning except domain
1093 /// 0 is used for instructions that are not associated with any interesting
1094 /// execution domain.
1096 virtual std::pair<uint16_t, uint16_t>
1097 getExecutionDomain(const MachineInstr *MI) const {
1098 return std::make_pair(0, 0);
1101 /// Change the opcode of MI to execute in Domain.
1103 /// The bit (1 << Domain) must be set in the mask returned from
1104 /// getExecutionDomain(MI).
1105 virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {}
1108 /// Returns the preferred minimum clearance
1109 /// before an instruction with an unwanted partial register update.
1111 /// Some instructions only write part of a register, and implicitly need to
1112 /// read the other parts of the register. This may cause unwanted stalls
1113 /// preventing otherwise unrelated instructions from executing in parallel in
1114 /// an out-of-order CPU.
1116 /// For example, the x86 instruction cvtsi2ss writes its result to bits
1117 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1118 /// the instruction needs to wait for the old value of the register to become
1121 /// addps %xmm1, %xmm0
1122 /// movaps %xmm0, (%rax)
1123 /// cvtsi2ss %rbx, %xmm0
1125 /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1126 /// instruction before it can issue, even though the high bits of %xmm0
1127 /// probably aren't needed.
1129 /// This hook returns the preferred clearance before MI, measured in
1130 /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1131 /// instructions before MI. It should only return a positive value for
1132 /// unwanted dependencies. If the old bits of the defined register have
1133 /// useful values, or if MI is determined to otherwise read the dependency,
1134 /// the hook should return 0.
1136 /// The unwanted dependency may be handled by:
1138 /// 1. Allocating the same register for an MI def and use. That makes the
1139 /// unwanted dependency identical to a required dependency.
1141 /// 2. Allocating a register for the def that has no defs in the previous N
1144 /// 3. Calling breakPartialRegDependency() with the same arguments. This
1145 /// allows the target to insert a dependency breaking instruction.
1148 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
1149 const TargetRegisterInfo *TRI) const {
1150 // The default implementation returns 0 for no partial register dependency.
1154 /// \brief Return the minimum clearance before an instruction that reads an
1155 /// unused register.
1157 /// For example, AVX instructions may copy part of a register operand into
1158 /// the unused high bits of the destination register.
1160 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
1162 /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1163 /// false dependence on any previous write to %xmm0.
1165 /// This hook works similarly to getPartialRegUpdateClearance, except that it
1166 /// does not take an operand index. Instead sets \p OpNum to the index of the
1167 /// unused register.
1168 virtual unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
1169 const TargetRegisterInfo *TRI) const {
1170 // The default implementation returns 0 for no undef register dependency.
1174 /// Insert a dependency-breaking instruction
1175 /// before MI to eliminate an unwanted dependency on OpNum.
1177 /// If it wasn't possible to avoid a def in the last N instructions before MI
1178 /// (see getPartialRegUpdateClearance), this hook will be called to break the
1179 /// unwanted dependency.
1181 /// On x86, an xorps instruction can be used as a dependency breaker:
1183 /// addps %xmm1, %xmm0
1184 /// movaps %xmm0, (%rax)
1185 /// xorps %xmm0, %xmm0
1186 /// cvtsi2ss %rbx, %xmm0
1188 /// An <imp-kill> operand should be added to MI if an instruction was
1189 /// inserted. This ties the instructions together in the post-ra scheduler.
1192 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
1193 const TargetRegisterInfo *TRI) const {}
1195 /// Create machine specific model for scheduling.
1196 virtual DFAPacketizer *
1197 CreateTargetScheduleState(const TargetSubtargetInfo &) const {
1201 // Sometimes, it is possible for the target
1202 // to tell, even without aliasing information, that two MIs access different
1203 // memory addresses. This function returns true if two MIs access different
1204 // memory addresses and false otherwise.
1206 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
1207 AliasAnalysis *AA = nullptr) const {
1208 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
1209 "MIa must load from or modify a memory location");
1210 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
1211 "MIb must load from or modify a memory location");
1215 /// \brief Return the value to use for the MachineCSE's LookAheadLimit,
1216 /// which is a heuristic used for CSE'ing phys reg defs.
1217 virtual unsigned getMachineCSELookAheadLimit () const {
1218 // The default lookahead is small to prevent unprofitable quadratic
1224 unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
1227 } // End llvm namespace