1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instructions to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/Support/DataTypes.h"
31 class MachineCodeForInstruction;
32 class TargetRegisterClass;
34 //---------------------------------------------------------------------------
35 // Data types used to define information about a single machine instruction
36 //---------------------------------------------------------------------------
38 typedef short MachineOpCode;
39 typedef unsigned InstrSchedClass;
41 //---------------------------------------------------------------------------
42 // struct TargetInstrDescriptor:
43 // Predefined information about each machine instruction.
44 // Designed to initialized statically.
47 const unsigned M_NOP_FLAG = 1 << 0;
48 const unsigned M_BRANCH_FLAG = 1 << 1;
49 const unsigned M_CALL_FLAG = 1 << 2;
50 const unsigned M_RET_FLAG = 1 << 3;
51 const unsigned M_BARRIER_FLAG = 1 << 4;
52 const unsigned M_DELAY_SLOT_FLAG = 1 << 5;
53 const unsigned M_CC_FLAG = 1 << 6;
54 const unsigned M_LOAD_FLAG = 1 << 7;
55 const unsigned M_STORE_FLAG = 1 << 8;
57 // M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones.
58 const unsigned M_2_ADDR_FLAG = 1 << 9;
60 // M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be
61 // changed into a 3-address instruction if the first two operands cannot be
62 // assigned to the same register. The target must implement the
63 // TargetInstrInfo::convertToThreeAddress method for this instruction.
64 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 10;
66 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
67 // Z), which produces the same result if Y and Z are exchanged.
68 const unsigned M_COMMUTABLE = 1 << 11;
70 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
71 // block? Typically this is things like return and branch instructions.
72 // Various passes use this to insert code into the bottom of a basic block, but
73 // before control flow occurs.
74 const unsigned M_TERMINATOR_FLAG = 1 << 12;
76 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
77 // insertion support when the DAG scheduler is inserting it into a machine basic
79 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 13;
81 /// TargetOperandInfo - This holds information about one operand of a machine
82 /// instruction, indicating the register class for register operands, etc.
84 class TargetOperandInfo {
86 /// RegClass - This specifies the register class of the operand if the
87 /// operand is a register. If not, this contains null.
88 const TargetRegisterClass *RegClass;
90 /// Currently no other information.
94 class TargetInstrDescriptor {
96 const char * Name; // Assembly language mnemonic for the opcode.
97 int numOperands; // Number of args; -1 if variable #args
98 int resultPos; // Position of the result; -1 if no result
99 unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0.
100 bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
101 // smallest -ve value is -(maxImmedConst+1).
102 unsigned numDelaySlots; // Number of delay slots after instruction
103 unsigned latency; // Latency in machine cycles
104 InstrSchedClass schedClass; // enum identifying instr sched class
105 unsigned Flags; // flags identifying machine instr class
106 unsigned TSFlags; // Target Specific Flag values
107 const unsigned *ImplicitUses; // Registers implicitly read by this instr
108 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
109 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
113 //---------------------------------------------------------------------------
115 /// TargetInstrInfo - Interface to description of machine instructions
117 class TargetInstrInfo {
118 const TargetInstrDescriptor* desc; // raw array to allow static init'n
119 unsigned NumOpcodes; // number of entries in the desc array
120 unsigned numRealOpCodes; // number of non-dummy op codes
122 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
123 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
125 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
126 virtual ~TargetInstrInfo();
128 // Invariant opcodes: All instruction sets have these as their low opcodes.
134 unsigned getNumOpcodes() const { return NumOpcodes; }
136 /// get - Return the machine instruction descriptor that corresponds to the
137 /// specified instruction opcode.
139 const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
140 assert((unsigned)Opcode < NumOpcodes);
144 const char *getName(MachineOpCode Opcode) const {
145 return get(Opcode).Name;
148 int getNumOperands(MachineOpCode Opcode) const {
149 return get(Opcode).numOperands;
152 InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
153 return get(Opcode).schedClass;
156 const unsigned *getImplicitUses(MachineOpCode Opcode) const {
157 return get(Opcode).ImplicitUses;
160 const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
161 return get(Opcode).ImplicitDefs;
166 // Query instruction class flags according to the machine-independent
167 // flags listed above.
169 bool isReturn(MachineOpCode Opcode) const {
170 return get(Opcode).Flags & M_RET_FLAG;
173 bool isTwoAddrInstr(MachineOpCode Opcode) const {
174 return get(Opcode).Flags & M_2_ADDR_FLAG;
176 bool isTerminatorInstr(unsigned Opcode) const {
177 return get(Opcode).Flags & M_TERMINATOR_FLAG;
180 bool isBranch(MachineOpCode Opcode) const {
181 return get(Opcode).Flags & M_BRANCH_FLAG;
184 /// isBarrier - Returns true if the specified instruction stops control flow
185 /// from executing the instruction immediately following it. Examples include
186 /// unconditional branches and return instructions.
187 bool isBarrier(MachineOpCode Opcode) const {
188 return get(Opcode).Flags & M_BARRIER_FLAG;
191 bool isCall(MachineOpCode Opcode) const {
192 return get(Opcode).Flags & M_CALL_FLAG;
194 bool isLoad(MachineOpCode Opcode) const {
195 return get(Opcode).Flags & M_LOAD_FLAG;
197 bool isStore(MachineOpCode Opcode) const {
198 return get(Opcode).Flags & M_STORE_FLAG;
201 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
202 /// custom insertion support when the DAG scheduler is inserting it into a
203 /// machine basic block.
204 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
205 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
208 /// Return true if the instruction is a register to register move
209 /// and leave the source and dest operands in the passed parameters.
210 virtual bool isMoveInstr(const MachineInstr& MI,
212 unsigned& destReg) const {
216 /// isLoadFromStackSlot - If the specified machine instruction is a direct
217 /// load from a stack slot, return the virtual or physical register number of
218 /// the destination along with the FrameIndex of the loaded stack slot. If
219 /// not, return 0. This predicate must return 0 if the instruction has
220 /// any side effects other than loading from the stack slot.
221 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
225 /// isStoreToStackSlot - If the specified machine instruction is a direct
226 /// store to a stack slot, return the virtual or physical register number of
227 /// the source reg along with the FrameIndex of the loaded stack slot. If
228 /// not, return 0. This predicate must return 0 if the instruction has
229 /// any side effects other than storing to the stack slot.
230 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
234 /// convertToThreeAddress - This method must be implemented by targets that
235 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
236 /// may be able to convert a two-address instruction into a true
237 /// three-address instruction on demand. This allows the X86 target (for
238 /// example) to convert ADD and SHL instructions into LEA instructions if they
239 /// would require register copies due to two-addressness.
241 /// This method returns a null pointer if the transformation cannot be
242 /// performed, otherwise it returns the new instruction.
244 virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const {
248 /// commuteInstruction - If a target has any instructions that are commutable,
249 /// but require converting to a different instruction or making non-trivial
250 /// changes to commute them, this method can overloaded to do this. The
251 /// default implementation of this method simply swaps the first two operands
252 /// of MI and returns it.
254 /// If a target wants to make more aggressive changes, they can construct and
255 /// return a new machine instruction. If an instruction cannot commute, it
256 /// can also return null.
258 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
260 /// Insert a goto (unconditional branch) sequence to TMBB, at the
262 virtual void insertGoto(MachineBasicBlock& MBB,
263 MachineBasicBlock& TMBB) const {
264 assert(0 && "Target didn't implement insertGoto!");
267 /// Reverses the branch condition of the MachineInstr pointed by
268 /// MI. The instruction is replaced and the new MI is returned.
269 virtual MachineBasicBlock::iterator
270 reverseBranchCondition(MachineBasicBlock::iterator MI) const {
271 assert(0 && "Target didn't implement reverseBranchCondition!");
277 //-------------------------------------------------------------------------
278 // Code generation support for creating individual machine instructions
280 // WARNING: These methods are Sparc specific
282 // DO NOT USE ANY OF THESE METHODS THEY ARE DEPRECATED!
284 //-------------------------------------------------------------------------
286 unsigned getNumDelaySlots(MachineOpCode Opcode) const {
287 return get(Opcode).numDelaySlots;
289 bool isCCInstr(MachineOpCode Opcode) const {
290 return get(Opcode).Flags & M_CC_FLAG;
292 bool isNop(MachineOpCode Opcode) const {
293 return get(Opcode).Flags & M_NOP_FLAG;
296 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
297 /// which must be filled by the code generator.
298 bool hasDelaySlot(unsigned Opcode) const {
299 return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
302 virtual bool hasResultInterlock(MachineOpCode Opcode) const {
307 // Latencies for individual instructions and instruction pairs
309 virtual int minLatency(MachineOpCode Opcode) const {
310 return get(Opcode).latency;
313 virtual int maxLatency(MachineOpCode Opcode) const {
314 return get(Opcode).latency;
318 // Which operand holds an immediate constant? Returns -1 if none
320 virtual int getImmedConstantPos(MachineOpCode Opcode) const {
321 return -1; // immediate position is machine specific, so say -1 == "none"
324 // Check if the specified constant fits in the immediate field
325 // of this machine instruction
327 virtual bool constantFitsInImmedField(MachineOpCode Opcode,
328 int64_t intValue) const;
330 // Return the largest positive constant that can be held in the IMMED field
331 // of this machine instruction.
332 // isSignExtended is set to true if the value is sign-extended before use
333 // (this is true for all immediate fields in SPARC instructions).
334 // Return 0 if the instruction has no IMMED field.
336 virtual uint64_t maxImmedConstant(MachineOpCode Opcode,
337 bool &isSignExtended) const {
338 isSignExtended = get(Opcode).immedIsSignExtended;
339 return get(Opcode).maxImmedConst;
343 } // End llvm namespace