1 //===-- llvm/Target/TargetInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetOperandInfo and TargetInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_TARGETINSTRDESC_H
16 #define LLVM_TARGET_TARGETINSTRDESC_H
20 class TargetRegisterClass;
22 //===----------------------------------------------------------------------===//
23 // Machine Operand Flags and Description
24 //===----------------------------------------------------------------------===//
27 // Operand constraints: only "tied_to" for now.
28 enum OperandConstraint {
29 TIED_TO = 0 // Must be allocated the same register as.
32 /// OperandFlags - These are flags set on operands, but should be considered
33 /// private, all access should go through the TargetOperandInfo accessors.
34 /// See the accessors for a description of what these are.
36 LookupPtrRegClass = 0,
42 /// TargetOperandInfo - This holds information about one operand of a machine
43 /// instruction, indicating the register class for register operands, etc.
45 class TargetOperandInfo {
47 /// RegClass - This specifies the register class enumeration of the operand
48 /// if the operand is a register. If not, this contains 0.
49 unsigned short RegClass;
51 /// Lower 16 bits are used to specify which constraints are set. The higher 16
52 /// bits are used to specify the value of constraints (4 bits each).
53 unsigned int Constraints;
54 /// Currently no other information.
56 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
57 /// requires a callback to look up its register class.
58 bool isLookupPtrRegClass() const { return Flags&(1 <<TOI::LookupPtrRegClass);}
60 /// isPredicate - Set if this is one of the operands that made up of
61 /// the predicate operand that controls an isPredicable() instruction.
62 bool isPredicate() const { return Flags & (1 << TOI::Predicate); }
64 /// isOptionalDef - Set if this operand is a optional def.
66 bool isOptionalDef() const { return Flags & (1 << TOI::OptionalDef); }
70 //===----------------------------------------------------------------------===//
71 // Machine Instruction Flags and Description
72 //===----------------------------------------------------------------------===//
74 /// TargetInstrDesc flags - These should be considered private to the
75 /// implementation of the TargetInstrDesc class. Clients should use the
76 /// predicate methods on TargetInstrDesc, not use these directly. These
77 /// all correspond to bitfields in the TargetInstrDesc::Flags field.
97 UsesCustomDAGSchedInserter,
103 /// TargetInstrDesc - Describe properties that are true of each
104 /// instruction in the target description file. This captures information about
105 /// side effects, register use and many other things. There is one instance of
106 /// this struct for each target instruction class, and the MachineInstr class
107 /// points to this struct directly to describe itself.
108 class TargetInstrDesc {
110 unsigned short Opcode; // The opcode number
111 unsigned short NumOperands; // Num of args (may be more if variable_ops)
112 unsigned short NumDefs; // Num of args that are definitions
113 unsigned short SchedClass; // enum identifying instr sched class
114 const char * Name; // Name of the instruction record in td file
115 unsigned Flags; // Flags identifying machine instr class
116 unsigned TSFlags; // Target Specific Flag values
117 const unsigned *ImplicitUses; // Registers implicitly read by this instr
118 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
119 const TargetRegisterClass **RCBarriers; // Reg classes completely "clobbered"
120 const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands
122 /// getOperandConstraint - Returns the value of the specific constraint if
123 /// it is set. Returns -1 if it is not set.
124 int getOperandConstraint(unsigned OpNum,
125 TOI::OperandConstraint Constraint) const {
126 if (OpNum < NumOperands &&
127 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
128 unsigned Pos = 16 + Constraint * 4;
129 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
134 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
135 /// dest operand. Returns -1 if there isn't one.
136 int findTiedToSrcOperand(unsigned OpNum) const;
138 /// getOpcode - Return the opcode number for this descriptor.
139 unsigned getOpcode() const {
143 /// getName - Return the name of the record in the .td file for this
144 /// instruction, for example "ADD8ri".
145 const char *getName() const {
149 /// getNumOperands - Return the number of declared MachineOperands for this
150 /// MachineInstruction. Note that variadic (isVariadic() returns true)
151 /// instructions may have additional operands at the end of the list, and note
152 /// that the machine instruction may include implicit register def/uses as
154 unsigned getNumOperands() const {
158 /// getNumDefs - Return the number of MachineOperands that are register
159 /// definitions. Register definitions always occur at the start of the
160 /// machine operand list. This is the number of "outs" in the .td file,
161 /// and does not include implicit defs.
162 unsigned getNumDefs() const {
166 /// isVariadic - Return true if this instruction can have a variable number of
167 /// operands. In this case, the variable operands will be after the normal
168 /// operands but before the implicit definitions and uses (if any are
170 bool isVariadic() const {
171 return Flags & (1 << TID::Variadic);
174 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
175 /// ARM instructions which can set condition code if 's' bit is set.
176 bool hasOptionalDef() const {
177 return Flags & (1 << TID::HasOptionalDef);
180 /// getImplicitUses - Return a list of registers that are potentially
181 /// read by any instance of this machine instruction. For example, on X86,
182 /// the "adc" instruction adds two register operands and adds the carry bit in
183 /// from the flags register. In this case, the instruction is marked as
184 /// implicitly reading the flags. Likewise, the variable shift instruction on
185 /// X86 is marked as implicitly reading the 'CL' register, which it always
188 /// This method returns null if the instruction has no implicit uses.
189 const unsigned *getImplicitUses() const {
193 /// getImplicitDefs - Return a list of registers that are potentially
194 /// written by any instance of this machine instruction. For example, on X86,
195 /// many instructions implicitly set the flags register. In this case, they
196 /// are marked as setting the FLAGS. Likewise, many instructions always
197 /// deposit their result in a physical register. For example, the X86 divide
198 /// instruction always deposits the quotient and remainder in the EAX/EDX
199 /// registers. For that instruction, this will return a list containing the
200 /// EAX/EDX/EFLAGS registers.
202 /// This method returns null if the instruction has no implicit defs.
203 const unsigned *getImplicitDefs() const {
207 /// getRegClassBarriers - Return a list of register classes that are
208 /// completely clobbered by this machine instruction. For example, on X86
209 /// the call instructions will completely clobber all the registers in the
210 /// fp stack and XMM classes.
212 /// This method returns null if the instruction doesn't completely clobber
213 /// any register class.
214 const TargetRegisterClass **getRegClassBarriers() const {
218 /// getSchedClass - Return the scheduling class for this instruction. The
219 /// scheduling class is an index into the InstrItineraryData table. This
220 /// returns zero if there is no known scheduling information for the
223 unsigned getSchedClass() const {
227 bool isReturn() const {
228 return Flags & (1 << TID::Return);
231 bool isCall() const {
232 return Flags & (1 << TID::Call);
235 /// isBarrier - Returns true if the specified instruction stops control flow
236 /// from executing the instruction immediately following it. Examples include
237 /// unconditional branches and return instructions.
238 bool isBarrier() const {
239 return Flags & (1 << TID::Barrier);
242 /// isTerminator - Returns true if this instruction part of the terminator for
243 /// a basic block. Typically this is things like return and branch
246 /// Various passes use this to insert code into the bottom of a basic block,
247 /// but before control flow occurs.
248 bool isTerminator() const {
249 return Flags & (1 << TID::Terminator);
252 /// isBranch - Returns true if this is a conditional, unconditional, or
253 /// indirect branch. Predicates below can be used to discriminate between
254 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
255 /// get more information.
256 bool isBranch() const {
257 return Flags & (1 << TID::Branch);
260 /// isIndirectBranch - Return true if this is an indirect branch, such as a
261 /// branch through a register.
262 bool isIndirectBranch() const {
263 return Flags & (1 << TID::IndirectBranch);
266 /// isConditionalBranch - Return true if this is a branch which may fall
267 /// through to the next instruction or may transfer control flow to some other
268 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
269 /// information about this branch.
270 bool isConditionalBranch() const {
271 return isBranch() & !isBarrier() & !isIndirectBranch();
274 /// isUnconditionalBranch - Return true if this is a branch which always
275 /// transfers control flow to some other block. The
276 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
277 /// about this branch.
278 bool isUnconditionalBranch() const {
279 return isBranch() & isBarrier() & !isIndirectBranch();
282 // isPredicable - Return true if this instruction has a predicate operand that
283 // controls execution. It may be set to 'always', or may be set to other
284 /// values. There are various methods in TargetInstrInfo that can be used to
285 /// control and modify the predicate in this instruction.
286 bool isPredicable() const {
287 return Flags & (1 << TID::Predicable);
290 /// isNotDuplicable - Return true if this instruction cannot be safely
291 /// duplicated. For example, if the instruction has a unique labels attached
292 /// to it, duplicating it would cause multiple definition errors.
293 bool isNotDuplicable() const {
294 return Flags & (1 << TID::NotDuplicable);
297 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
298 /// which must be filled by the code generator.
299 bool hasDelaySlot() const {
300 return Flags & (1 << TID::DelaySlot);
303 /// canFoldAsLoad - Return true for instructions that can be folded as
304 /// memory operands in other instructions. The most common use for this
305 /// is instructions that are simple loads from memory that don't modify
306 /// the loaded value in any way, but it can also be used for instructions
307 /// that can be expressed as constant-pool loads, such as V_SETALLONES
308 /// on x86, to allow them to be folded when it is beneficial.
309 /// This should only be set on instructions that return a value in their
310 /// only virtual register definition.
311 bool canFoldAsLoad() const {
312 return Flags & (1 << TID::FoldableAsLoad);
315 //===--------------------------------------------------------------------===//
316 // Side Effect Analysis
317 //===--------------------------------------------------------------------===//
319 /// mayLoad - Return true if this instruction could possibly read memory.
320 /// Instructions with this flag set are not necessarily simple load
321 /// instructions, they may load a value and modify it, for example.
322 bool mayLoad() const {
323 return Flags & (1 << TID::MayLoad);
327 /// mayStore - Return true if this instruction could possibly modify memory.
328 /// Instructions with this flag set are not necessarily simple store
329 /// instructions, they may store a modified value based on their operands, or
330 /// may not actually modify anything, for example.
331 bool mayStore() const {
332 return Flags & (1 << TID::MayStore);
335 /// hasUnmodeledSideEffects - Return true if this instruction has side
336 /// effects that are not modeled by other flags. This does not return true
337 /// for instructions whose effects are captured by:
339 /// 1. Their operand list and implicit definition/use list. Register use/def
340 /// info is explicit for instructions.
341 /// 2. Memory accesses. Use mayLoad/mayStore.
342 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
344 /// Examples of side effects would be modifying 'invisible' machine state like
345 /// a control register, flushing a cache, modifying a register invisible to
348 bool hasUnmodeledSideEffects() const {
349 return Flags & (1 << TID::UnmodeledSideEffects);
352 //===--------------------------------------------------------------------===//
353 // Flags that indicate whether an instruction can be modified by a method.
354 //===--------------------------------------------------------------------===//
356 /// isCommutable - Return true if this may be a 2- or 3-address
357 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
358 /// result if Y and Z are exchanged. If this flag is set, then the
359 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
362 /// Note that this flag may be set on instructions that are only commutable
363 /// sometimes. In these cases, the call to commuteInstruction will fail.
364 /// Also note that some instructions require non-trivial modification to
366 bool isCommutable() const {
367 return Flags & (1 << TID::Commutable);
370 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
371 /// which can be changed into a 3-address instruction if needed. Doing this
372 /// transformation can be profitable in the register allocator, because it
373 /// means that the instruction can use a 2-address form if possible, but
374 /// degrade into a less efficient form if the source and dest register cannot
375 /// be assigned to the same register. For example, this allows the x86
376 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
377 /// is the same speed as the shift but has bigger code size.
379 /// If this returns true, then the target must implement the
380 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
381 /// is allowed to fail if the transformation isn't valid for this specific
382 /// instruction (e.g. shl reg, 4 on x86).
384 bool isConvertibleTo3Addr() const {
385 return Flags & (1 << TID::ConvertibleTo3Addr);
388 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
389 /// custom insertion support when the DAG scheduler is inserting it into a
390 /// machine basic block. If this is true for the instruction, it basically
391 /// means that it is a pseudo instruction used at SelectionDAG time that is
392 /// expanded out into magic code by the target when MachineInstrs are formed.
394 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
395 /// is used to insert this into the MachineBasicBlock.
396 bool usesCustomDAGSchedInsertionHook() const {
397 return Flags & (1 << TID::UsesCustomDAGSchedInserter);
400 /// isRematerializable - Returns true if this instruction is a candidate for
401 /// remat. This flag is deprecated, please don't use it anymore. If this
402 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
403 /// verify the instruction is really rematable.
404 bool isRematerializable() const {
405 return Flags & (1 << TID::Rematerializable);
408 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
409 /// less) than a move instruction. This is useful during certain types of
410 /// rematerializations (e.g., during two-address conversion) where we would
411 /// like to remat the instruction, but not if it costs more than moving the
412 /// instruction into the appropriate register.
413 bool isAsCheapAsAMove() const {
414 return Flags & (1 << TID::CheapAsAMove);
418 } // end namespace llvm