1 //===-- llvm/Target/TargetInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetOperandInfo and TargetInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_TARGETINSTRDESC_H
16 #define LLVM_TARGET_TARGETINSTRDESC_H
20 class TargetRegisterClass;
21 class TargetRegisterInfo;
23 //===----------------------------------------------------------------------===//
24 // Machine Operand Flags and Description
25 //===----------------------------------------------------------------------===//
28 // Operand constraints: only "tied_to" for now.
29 enum OperandConstraint {
30 TIED_TO = 0 // Must be allocated the same register as.
33 /// OperandFlags - These are flags set on operands, but should be considered
34 /// private, all access should go through the TargetOperandInfo accessors.
35 /// See the accessors for a description of what these are.
37 LookupPtrRegClass = 0,
43 /// TargetOperandInfo - This holds information about one operand of a machine
44 /// instruction, indicating the register class for register operands, etc.
46 class TargetOperandInfo {
48 /// RegClass - This specifies the register class enumeration of the operand
49 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
50 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
51 /// get a dynamic register class.
53 /// NOTE: This member should be considered to be private, all access should go
54 /// through "getRegClass(TRI)" below.
55 unsigned short RegClass;
57 /// Flags - These are flags from the TOI::OperandFlags enum.
60 /// Lower 16 bits are used to specify which constraints are set. The higher 16
61 /// bits are used to specify the value of constraints (4 bits each).
63 /// Currently no other information.
65 /// getRegClass - Get the register class for the operand, handling resolution
66 /// of "symbolic" pointer register classes etc. If this is not a register
67 /// operand, this returns null.
68 const TargetRegisterClass *getRegClass(const TargetRegisterInfo *TRI) const;
71 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
72 /// requires a callback to look up its register class.
73 bool isLookupPtrRegClass() const { return Flags&(1 <<TOI::LookupPtrRegClass);}
75 /// isPredicate - Set if this is one of the operands that made up of
76 /// the predicate operand that controls an isPredicable() instruction.
77 bool isPredicate() const { return Flags & (1 << TOI::Predicate); }
79 /// isOptionalDef - Set if this operand is a optional def.
81 bool isOptionalDef() const { return Flags & (1 << TOI::OptionalDef); }
85 //===----------------------------------------------------------------------===//
86 // Machine Instruction Flags and Description
87 //===----------------------------------------------------------------------===//
89 /// TargetInstrDesc flags - These should be considered private to the
90 /// implementation of the TargetInstrDesc class. Clients should use the
91 /// predicate methods on TargetInstrDesc, not use these directly. These
92 /// all correspond to bitfields in the TargetInstrDesc::Flags field.
109 UnmodeledSideEffects,
112 UsesCustomDAGSchedInserter,
118 /// TargetInstrDesc - Describe properties that are true of each
119 /// instruction in the target description file. This captures information about
120 /// side effects, register use and many other things. There is one instance of
121 /// this struct for each target instruction class, and the MachineInstr class
122 /// points to this struct directly to describe itself.
123 class TargetInstrDesc {
125 unsigned short Opcode; // The opcode number
126 unsigned short NumOperands; // Num of args (may be more if variable_ops)
127 unsigned short NumDefs; // Num of args that are definitions
128 unsigned short SchedClass; // enum identifying instr sched class
129 const char * Name; // Name of the instruction record in td file
130 unsigned Flags; // Flags identifying machine instr class
131 unsigned TSFlags; // Target Specific Flag values
132 const unsigned *ImplicitUses; // Registers implicitly read by this instr
133 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
134 const TargetRegisterClass **RCBarriers; // Reg classes completely "clobbered"
135 const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands
137 /// getOperandConstraint - Returns the value of the specific constraint if
138 /// it is set. Returns -1 if it is not set.
139 int getOperandConstraint(unsigned OpNum,
140 TOI::OperandConstraint Constraint) const {
141 if (OpNum < NumOperands &&
142 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
143 unsigned Pos = 16 + Constraint * 4;
144 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
149 /// getOpcode - Return the opcode number for this descriptor.
150 unsigned getOpcode() const {
154 /// getName - Return the name of the record in the .td file for this
155 /// instruction, for example "ADD8ri".
156 const char *getName() const {
160 /// getNumOperands - Return the number of declared MachineOperands for this
161 /// MachineInstruction. Note that variadic (isVariadic() returns true)
162 /// instructions may have additional operands at the end of the list, and note
163 /// that the machine instruction may include implicit register def/uses as
165 unsigned getNumOperands() const {
169 /// getNumDefs - Return the number of MachineOperands that are register
170 /// definitions. Register definitions always occur at the start of the
171 /// machine operand list. This is the number of "outs" in the .td file,
172 /// and does not include implicit defs.
173 unsigned getNumDefs() const {
177 /// isVariadic - Return true if this instruction can have a variable number of
178 /// operands. In this case, the variable operands will be after the normal
179 /// operands but before the implicit definitions and uses (if any are
181 bool isVariadic() const {
182 return Flags & (1 << TID::Variadic);
185 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
186 /// ARM instructions which can set condition code if 's' bit is set.
187 bool hasOptionalDef() const {
188 return Flags & (1 << TID::HasOptionalDef);
191 /// getImplicitUses - Return a list of registers that are potentially
192 /// read by any instance of this machine instruction. For example, on X86,
193 /// the "adc" instruction adds two register operands and adds the carry bit in
194 /// from the flags register. In this case, the instruction is marked as
195 /// implicitly reading the flags. Likewise, the variable shift instruction on
196 /// X86 is marked as implicitly reading the 'CL' register, which it always
199 /// This method returns null if the instruction has no implicit uses.
200 const unsigned *getImplicitUses() const {
204 /// getImplicitDefs - Return a list of registers that are potentially
205 /// written by any instance of this machine instruction. For example, on X86,
206 /// many instructions implicitly set the flags register. In this case, they
207 /// are marked as setting the FLAGS. Likewise, many instructions always
208 /// deposit their result in a physical register. For example, the X86 divide
209 /// instruction always deposits the quotient and remainder in the EAX/EDX
210 /// registers. For that instruction, this will return a list containing the
211 /// EAX/EDX/EFLAGS registers.
213 /// This method returns null if the instruction has no implicit defs.
214 const unsigned *getImplicitDefs() const {
218 /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
219 /// uses the specified physical register.
220 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
221 if (const unsigned *ImpUses = ImplicitUses)
222 for (; *ImpUses; ++ImpUses)
223 if (*ImpUses == Reg) return true;
227 /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
228 /// defines the specified physical register.
229 bool hasImplicitDefOfPhysReg(unsigned Reg) const {
230 if (const unsigned *ImpDefs = ImplicitDefs)
231 for (; *ImpDefs; ++ImpDefs)
232 if (*ImpDefs == Reg) return true;
236 /// getRegClassBarriers - Return a list of register classes that are
237 /// completely clobbered by this machine instruction. For example, on X86
238 /// the call instructions will completely clobber all the registers in the
239 /// fp stack and XMM classes.
241 /// This method returns null if the instruction doesn't completely clobber
242 /// any register class.
243 const TargetRegisterClass **getRegClassBarriers() const {
247 /// getSchedClass - Return the scheduling class for this instruction. The
248 /// scheduling class is an index into the InstrItineraryData table. This
249 /// returns zero if there is no known scheduling information for the
252 unsigned getSchedClass() const {
256 bool isReturn() const {
257 return Flags & (1 << TID::Return);
260 bool isCall() const {
261 return Flags & (1 << TID::Call);
264 /// isBarrier - Returns true if the specified instruction stops control flow
265 /// from executing the instruction immediately following it. Examples include
266 /// unconditional branches and return instructions.
267 bool isBarrier() const {
268 return Flags & (1 << TID::Barrier);
271 /// isTerminator - Returns true if this instruction part of the terminator for
272 /// a basic block. Typically this is things like return and branch
275 /// Various passes use this to insert code into the bottom of a basic block,
276 /// but before control flow occurs.
277 bool isTerminator() const {
278 return Flags & (1 << TID::Terminator);
281 /// isBranch - Returns true if this is a conditional, unconditional, or
282 /// indirect branch. Predicates below can be used to discriminate between
283 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
284 /// get more information.
285 bool isBranch() const {
286 return Flags & (1 << TID::Branch);
289 /// isIndirectBranch - Return true if this is an indirect branch, such as a
290 /// branch through a register.
291 bool isIndirectBranch() const {
292 return Flags & (1 << TID::IndirectBranch);
295 /// isConditionalBranch - Return true if this is a branch which may fall
296 /// through to the next instruction or may transfer control flow to some other
297 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
298 /// information about this branch.
299 bool isConditionalBranch() const {
300 return isBranch() & !isBarrier() & !isIndirectBranch();
303 /// isUnconditionalBranch - Return true if this is a branch which always
304 /// transfers control flow to some other block. The
305 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
306 /// about this branch.
307 bool isUnconditionalBranch() const {
308 return isBranch() & isBarrier() & !isIndirectBranch();
311 // isPredicable - Return true if this instruction has a predicate operand that
312 // controls execution. It may be set to 'always', or may be set to other
313 /// values. There are various methods in TargetInstrInfo that can be used to
314 /// control and modify the predicate in this instruction.
315 bool isPredicable() const {
316 return Flags & (1 << TID::Predicable);
319 /// isNotDuplicable - Return true if this instruction cannot be safely
320 /// duplicated. For example, if the instruction has a unique labels attached
321 /// to it, duplicating it would cause multiple definition errors.
322 bool isNotDuplicable() const {
323 return Flags & (1 << TID::NotDuplicable);
326 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
327 /// which must be filled by the code generator.
328 bool hasDelaySlot() const {
329 return Flags & (1 << TID::DelaySlot);
332 /// canFoldAsLoad - Return true for instructions that can be folded as
333 /// memory operands in other instructions. The most common use for this
334 /// is instructions that are simple loads from memory that don't modify
335 /// the loaded value in any way, but it can also be used for instructions
336 /// that can be expressed as constant-pool loads, such as V_SETALLONES
337 /// on x86, to allow them to be folded when it is beneficial.
338 /// This should only be set on instructions that return a value in their
339 /// only virtual register definition.
340 bool canFoldAsLoad() const {
341 return Flags & (1 << TID::FoldableAsLoad);
344 //===--------------------------------------------------------------------===//
345 // Side Effect Analysis
346 //===--------------------------------------------------------------------===//
348 /// mayLoad - Return true if this instruction could possibly read memory.
349 /// Instructions with this flag set are not necessarily simple load
350 /// instructions, they may load a value and modify it, for example.
351 bool mayLoad() const {
352 return Flags & (1 << TID::MayLoad);
356 /// mayStore - Return true if this instruction could possibly modify memory.
357 /// Instructions with this flag set are not necessarily simple store
358 /// instructions, they may store a modified value based on their operands, or
359 /// may not actually modify anything, for example.
360 bool mayStore() const {
361 return Flags & (1 << TID::MayStore);
364 /// hasUnmodeledSideEffects - Return true if this instruction has side
365 /// effects that are not modeled by other flags. This does not return true
366 /// for instructions whose effects are captured by:
368 /// 1. Their operand list and implicit definition/use list. Register use/def
369 /// info is explicit for instructions.
370 /// 2. Memory accesses. Use mayLoad/mayStore.
371 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
373 /// Examples of side effects would be modifying 'invisible' machine state like
374 /// a control register, flushing a cache, modifying a register invisible to
377 bool hasUnmodeledSideEffects() const {
378 return Flags & (1 << TID::UnmodeledSideEffects);
381 //===--------------------------------------------------------------------===//
382 // Flags that indicate whether an instruction can be modified by a method.
383 //===--------------------------------------------------------------------===//
385 /// isCommutable - Return true if this may be a 2- or 3-address
386 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
387 /// result if Y and Z are exchanged. If this flag is set, then the
388 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
391 /// Note that this flag may be set on instructions that are only commutable
392 /// sometimes. In these cases, the call to commuteInstruction will fail.
393 /// Also note that some instructions require non-trivial modification to
395 bool isCommutable() const {
396 return Flags & (1 << TID::Commutable);
399 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
400 /// which can be changed into a 3-address instruction if needed. Doing this
401 /// transformation can be profitable in the register allocator, because it
402 /// means that the instruction can use a 2-address form if possible, but
403 /// degrade into a less efficient form if the source and dest register cannot
404 /// be assigned to the same register. For example, this allows the x86
405 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
406 /// is the same speed as the shift but has bigger code size.
408 /// If this returns true, then the target must implement the
409 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
410 /// is allowed to fail if the transformation isn't valid for this specific
411 /// instruction (e.g. shl reg, 4 on x86).
413 bool isConvertibleTo3Addr() const {
414 return Flags & (1 << TID::ConvertibleTo3Addr);
417 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
418 /// custom insertion support when the DAG scheduler is inserting it into a
419 /// machine basic block. If this is true for the instruction, it basically
420 /// means that it is a pseudo instruction used at SelectionDAG time that is
421 /// expanded out into magic code by the target when MachineInstrs are formed.
423 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
424 /// is used to insert this into the MachineBasicBlock.
425 bool usesCustomDAGSchedInsertionHook() const {
426 return Flags & (1 << TID::UsesCustomDAGSchedInserter);
429 /// isRematerializable - Returns true if this instruction is a candidate for
430 /// remat. This flag is deprecated, please don't use it anymore. If this
431 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
432 /// verify the instruction is really rematable.
433 bool isRematerializable() const {
434 return Flags & (1 << TID::Rematerializable);
437 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
438 /// less) than a move instruction. This is useful during certain types of
439 /// optimizations (e.g., remat during two-address conversion or machine licm)
440 /// where we would like to remat or hoist the instruction, but not if it costs
441 /// more than moving the instruction into the appropriate register. Note, we
442 /// are not marking copies from and to the same register class with this flag.
443 bool isAsCheapAsAMove() const {
444 return Flags & (1 << TID::CheapAsAMove);
448 } // end namespace llvm