1 //===-- llvm/Target/TargetCacheInfo.h ---------------------------*- C++ -*-===//
3 // Describes properties of the target cache architecture.
5 //===----------------------------------------------------------------------===//
7 #ifndef LLVM_TARGET_TARGETCACHEINFO_H
8 #define LLVM_TARGET_TARGETCACHEINFO_H
10 #include "Support/DataTypes.h"
15 struct TargetCacheInfo {
16 const TargetMachine ⌖
17 TargetCacheInfo(const TargetCacheInfo&); // DO NOT IMPLEMENT
18 void operator=(const TargetCacheInfo&); // DO NOT IMPLEMENT
20 unsigned int numLevels;
21 std::vector<unsigned short> cacheLineSizes;
22 std::vector<unsigned int> cacheSizes;
23 std::vector<unsigned short> cacheAssoc;
26 TargetCacheInfo(const TargetMachine& tgt) : target(tgt) {
29 virtual ~TargetCacheInfo() {}
31 // Default parameters are:
33 // L1: LineSize 16, Cache Size 32KB, Direct-mapped (assoc = 1)
34 // L2: LineSize 32, Cache Size 1 MB, 4-way associative
35 // NOTE: Cache levels are numbered from 1 as above, not from 0.
37 virtual void Initialize (); // subclass to override defaults
39 unsigned int getNumCacheLevels () const {
42 unsigned short getCacheLineSize (unsigned level) const {
43 assert(level <= cacheLineSizes.size() && "Invalid cache level");
44 return cacheLineSizes[level-1];
46 unsigned int getCacheSize (unsigned level) const {
47 assert(level <= cacheSizes.size() && "Invalid cache level");
48 return cacheSizes[level-1];
50 unsigned short getCacheAssoc (unsigned level) const {
51 assert(level <= cacheAssoc.size() && "Invalid cache level");
52 return cacheAssoc[level];