1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
26 string Namespace = "";
29 // RegAltNameIndex - The alternate name set to use for register operands of
30 // this register class when printing.
31 class RegAltNameIndex {
32 string Namespace = "";
34 def NoRegAltName : RegAltNameIndex;
36 // Register - You should define one instance of this class for each register
37 // in the target machine. String n will become the "name" of the register.
38 class Register<string n, list<string> altNames = []> {
39 string Namespace = "";
41 list<string> AltNames = altNames;
43 // Aliases - A list of registers that this register overlaps with. A read or
44 // modification of this register can potentially read or modify the aliased
46 list<Register> Aliases = [];
48 // SubRegs - A list of registers that are parts of this register. Note these
49 // are "immediate" sub-registers and the registers within the list do not
50 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
52 list<Register> SubRegs = [];
54 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
55 // to address it. Sub-sub-register indices are automatically inherited from
57 list<SubRegIndex> SubRegIndices = [];
59 // RegAltNameIndices - The alternate name indices which are valid for this
61 list<RegAltNameIndex> RegAltNameIndices = [];
63 // CompositeIndices - Specify subreg indices that don't correspond directly to
64 // a register in SubRegs and are not inherited. The following formats are
67 // (a) Identity - Reg:a == Reg
68 // (a b) Alias - Reg:a == Reg:b
69 // (a b,c) Composite - Reg:a == (Reg:b):c
71 // This can be used to disambiguate a sub-sub-register that exists in more
72 // than one subregister and other weird stuff.
73 list<dag> CompositeIndices = [];
75 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
76 // These values can be determined by locating the <target>.h file in the
77 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
78 // order of these names correspond to the enumeration used by gcc. A value of
79 // -1 indicates that the gcc number is undefined and -2 that register number
80 // is invalid for this mode/flavour.
81 list<int> DwarfNumbers = [];
83 // CostPerUse - Additional cost of instructions using this register compared
84 // to other registers in its class. The register allocator will try to
85 // minimize the number of instructions using a register with a CostPerUse.
86 // This is used by the x86-64 and ARM Thumb targets where some registers
87 // require larger instruction encodings.
91 // RegisterWithSubRegs - This can be used to define instances of Register which
92 // need to specify sub-registers.
93 // List "subregs" specifies which registers are sub-registers to this one. This
94 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
95 // This allows the code generator to be careful not to put two values with
96 // overlapping live ranges into registers which alias.
97 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
98 let SubRegs = subregs;
101 // RegisterClass - Now that all of the registers are defined, and aliases
102 // between registers are defined, specify which registers belong to which
103 // register classes. This also defines the default allocation order of
104 // registers by register allocators.
106 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
107 dag regList, RegAltNameIndex idx = NoRegAltName> {
108 string Namespace = namespace;
110 // RegType - Specify the list ValueType of the registers in this register
111 // class. Note that all registers in a register class must have the same
112 // ValueTypes. This is a list because some targets permit storing different
113 // types in same register, for example vector values with 128-bit total size,
114 // but different count/size of items, like SSE on x86.
116 list<ValueType> RegTypes = regTypes;
118 // Size - Specify the spill size in bits of the registers. A default value of
119 // zero lets tablgen pick an appropriate size.
122 // Alignment - Specify the alignment required of the registers when they are
123 // stored or loaded to memory.
125 int Alignment = alignment;
127 // CopyCost - This value is used to specify the cost of copying a value
128 // between two registers in this register class. The default value is one
129 // meaning it takes a single instruction to perform the copying. A negative
130 // value means copying is extremely expensive or impossible.
133 // MemberList - Specify which registers are in this class. If the
134 // allocation_order_* method are not specified, this also defines the order of
135 // allocation used by the register allocator.
137 dag MemberList = regList;
139 // AltNameIndex - The alternate register name to use when printing operands
140 // of this register class. Every register in the register class must have
141 // a valid alternate name for the given index.
142 RegAltNameIndex altNameIndex = idx;
144 // SubRegClasses - Specify the register class of subregisters as a list of
145 // dags: (RegClass SubRegIndex, SubRegindex, ...)
146 list<dag> SubRegClasses = [];
148 // isAllocatable - Specify that the register class can be used for virtual
149 // registers and register allocation. Some register classes are only used to
150 // model instruction operand constraints, and should have isAllocatable = 0.
151 bit isAllocatable = 1;
153 // AltOrders - List of alternative allocation orders. The default order is
154 // MemberList itself, and that is good enough for most targets since the
155 // register allocators automatically remove reserved registers and move
156 // callee-saved registers to the end.
157 list<dag> AltOrders = [];
159 // AltOrderSelect - The body of a function that selects the allocation order
160 // to use in a given machine function. The code will be inserted in a
161 // function like this:
163 // static inline unsigned f(const MachineFunction &MF) { ... }
165 // The function should return 0 to select the default order defined by
166 // MemberList, 1 to select the first AltOrders entry and so on.
167 code AltOrderSelect = [{}];
170 // The memberList in a RegisterClass is a dag of set operations. TableGen
171 // evaluates these set operations and expand them into register lists. These
172 // are the most common operation, see test/TableGen/SetTheory.td for more
173 // examples of what is possible:
175 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
176 // register class, or a sub-expression. This is also the way to simply list
179 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
181 // (and GPR, CSR) - Set intersection. All registers from the first set that are
182 // also in the second set.
184 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
185 // numbered registers.
187 // (shl GPR, 4) - Remove the first N elements.
189 // (trunc GPR, 4) - Truncate after the first N elements.
191 // (rotl GPR, 1) - Rotate N places to the left.
193 // (rotr GPR, 1) - Rotate N places to the right.
195 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
197 // All of these operators work on ordered sets, not lists. That means
198 // duplicates are removed from sub-expressions.
200 // Set operators. The rest is defined in TargetSelectionDAG.td.
204 // RegisterTuples - Automatically generate super-registers by forming tuples of
205 // sub-registers. This is useful for modeling register sequence constraints
206 // with pseudo-registers that are larger than the architectural registers.
208 // The sub-register lists are zipped together:
210 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
212 // Generates the same registers as:
214 // let SubRegIndices = [sube, subo] in {
215 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
216 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
219 // The generated pseudo-registers inherit super-classes and fields from their
220 // first sub-register. Most fields from the Register class are inferred, and
221 // the AsmName and Dwarf numbers are cleared.
223 // RegisterTuples instances can be used in other set operations to form
224 // register classes and so on. This is the only way of using the generated
226 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
227 // SubRegs - N lists of registers to be zipped up. Super-registers are
228 // synthesized from the first element of each SubRegs list, the second
229 // element and so on.
230 list<dag> SubRegs = Regs;
232 // SubRegIndices - N SubRegIndex instances. This provides the names of the
233 // sub-registers in the synthesized super-registers.
234 list<SubRegIndex> SubRegIndices = Indices;
236 // Compose sub-register indices like in a normal Register.
237 list<dag> CompositeIndices = [];
241 //===----------------------------------------------------------------------===//
242 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
243 // to the register numbering used by gcc and gdb. These values are used by a
244 // debug information writer to describe where values may be located during
246 class DwarfRegNum<list<int> Numbers> {
247 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
248 // These values can be determined by locating the <target>.h file in the
249 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
250 // order of these names correspond to the enumeration used by gcc. A value of
251 // -1 indicates that the gcc number is undefined and -2 that register number
252 // is invalid for this mode/flavour.
253 list<int> DwarfNumbers = Numbers;
256 // DwarfRegAlias - This class declares that a given register uses the same dwarf
257 // numbers as another one. This is useful for making it clear that the two
258 // registers do have the same number. It also lets us build a mapping
259 // from dwarf register number to llvm register.
260 class DwarfRegAlias<Register reg> {
261 Register DwarfAlias = reg;
264 //===----------------------------------------------------------------------===//
265 // Pull in the common support for scheduling
267 include "llvm/Target/TargetSchedule.td"
269 class Predicate; // Forward def
271 //===----------------------------------------------------------------------===//
272 // Instruction set description - These classes correspond to the C++ classes in
273 // the Target/TargetInstrInfo.h file.
276 string Namespace = "";
278 dag OutOperandList; // An dag containing the MI def operand list.
279 dag InOperandList; // An dag containing the MI use operand list.
280 string AsmString = ""; // The .s format to print the instruction with.
282 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
283 // otherwise, uninitialized.
286 // The follow state will eventually be inferred automatically from the
287 // instruction pattern.
289 list<Register> Uses = []; // Default to using no non-operand registers
290 list<Register> Defs = []; // Default to modifying no non-operand registers
292 // Predicates - List of predicates which will be turned into isel matching
294 list<Predicate> Predicates = [];
296 // Size - Size of encoded instruction, or zero if the size cannot be determined
300 // DecoderNamespace - The "namespace" in which this instruction exists, on
301 // targets like ARM which multiple ISA namespaces exist.
302 string DecoderNamespace = "";
304 // Code size, for instruction selection.
305 // FIXME: What does this actually mean?
308 // Added complexity passed onto matching pattern.
309 int AddedComplexity = 0;
311 // These bits capture information about the high-level semantics of the
313 bit isReturn = 0; // Is this instruction a return instruction?
314 bit isBranch = 0; // Is this instruction a branch instruction?
315 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
316 bit isCompare = 0; // Is this instruction a comparison instruction?
317 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
318 bit isBitcast = 0; // Is this instruction a bitcast instruction?
319 bit isBarrier = 0; // Can control flow fall through this instruction?
320 bit isCall = 0; // Is this instruction a call instruction?
321 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
322 bit mayLoad = 0; // Is it possible for this inst to read memory?
323 bit mayStore = 0; // Is it possible for this inst to write memory?
324 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
325 bit isCommutable = 0; // Is this 3 operand instruction commutable?
326 bit isTerminator = 0; // Is this part of the terminator for a basic block?
327 bit isReMaterializable = 0; // Is this instruction re-materializable?
328 bit isPredicable = 0; // Is this instruction predicable?
329 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
330 bit usesCustomInserter = 0; // Pseudo instr needing special help.
331 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
332 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
333 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
334 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
335 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
336 bit isPseudo = 0; // Is this instruction a pseudo-instruction?
337 // If so, won't have encoding information for
338 // the [MC]CodeEmitter stuff.
340 // Side effect flags - When set, the flags have these meanings:
342 // hasSideEffects - The instruction has side effects that are not
343 // captured by any operands of the instruction or other flags.
345 // neverHasSideEffects - Set on an instruction with no pattern if it has no
347 bit hasSideEffects = 0;
348 bit neverHasSideEffects = 0;
350 // Is this instruction a "real" instruction (with a distinct machine
351 // encoding), or is it a pseudo instruction used for codegen modeling
353 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
354 // instructions can (and often do) still have encoding information
355 // associated with them. Once we've migrated all of them over to true
356 // pseudo-instructions that are lowered to real instructions prior to
357 // the printer/emitter, we can remove this attribute and just use isPseudo.
358 bit isCodeGenOnly = 0;
360 // Is this instruction a pseudo instruction for use by the assembler parser.
361 bit isAsmParserOnly = 0;
363 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
365 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
367 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
368 /// be encoded into the output machineinstr.
369 string DisableEncoding = "";
371 string PostEncoderMethod = "";
372 string DecoderMethod = "";
374 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
375 bits<64> TSFlags = 0;
377 ///@name Assembler Parser Support
380 string AsmMatchConverter = "";
385 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
386 /// Which instruction it expands to and how the operands map from the
388 class PseudoInstExpansion<dag Result> {
389 dag ResultInst = Result; // The instruction to generate.
393 /// Predicates - These are extra conditionals which are turned into instruction
394 /// selector matching code. Currently each predicate is just a string.
395 class Predicate<string cond> {
396 string CondString = cond;
398 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
399 /// matcher, this is true. Targets should set this by inheriting their
400 /// feature from the AssemblerPredicate class in addition to Predicate.
401 bit AssemblerMatcherPredicate = 0;
403 /// AssemblerCondString - Name of the subtarget feature being tested used
404 /// as alternative condition string used for assembler matcher.
405 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
406 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
407 /// It can also list multiple features separated by ",".
408 /// e.g. "ModeThumb,FeatureThumb2" is translated to
409 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
410 string AssemblerCondString = "";
413 /// NoHonorSignDependentRounding - This predicate is true if support for
414 /// sign-dependent-rounding is not enabled.
415 def NoHonorSignDependentRounding
416 : Predicate<"!HonorSignDependentRoundingFPMath()">;
418 class Requires<list<Predicate> preds> {
419 list<Predicate> Predicates = preds;
422 /// ops definition - This is just a simple marker used to identify the operand
423 /// list for an instruction. outs and ins are identical both syntactically and
424 /// semanticallyr; they are used to define def operands and use operands to
425 /// improve readibility. This should be used like this:
426 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
431 /// variable_ops definition - Mark this instruction as taking a variable number
436 /// PointerLikeRegClass - Values that are designed to have pointer width are
437 /// derived from this. TableGen treats the register class as having a symbolic
438 /// type that it doesn't know, and resolves the actual regclass to use by using
439 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
440 class PointerLikeRegClass<int Kind> {
441 int RegClassKind = Kind;
445 /// ptr_rc definition - Mark this operand as being a pointer value whose
446 /// register class is resolved dynamically via a callback to TargetInstrInfo.
447 /// FIXME: We should probably change this to a class which contain a list of
448 /// flags. But currently we have but one flag.
449 def ptr_rc : PointerLikeRegClass<0>;
451 /// unknown definition - Mark this operand as being of unknown type, causing
452 /// it to be resolved by inference in the context it is used.
455 /// AsmOperandClass - Representation for the kinds of operands which the target
456 /// specific parser can create and the assembly matcher may need to distinguish.
458 /// Operand classes are used to define the order in which instructions are
459 /// matched, to ensure that the instruction which gets matched for any
460 /// particular list of operands is deterministic.
462 /// The target specific parser must be able to classify a parsed operand into a
463 /// unique class which does not partially overlap with any other classes. It can
464 /// match a subset of some other class, in which case the super class field
465 /// should be defined.
466 class AsmOperandClass {
467 /// The name to use for this class, which should be usable as an enum value.
470 /// The super classes of this operand.
471 list<AsmOperandClass> SuperClasses = [];
473 /// The name of the method on the target specific operand to call to test
474 /// whether the operand is an instance of this class. If not set, this will
475 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
476 /// signature should be:
477 /// bool isFoo() const;
478 string PredicateMethod = ?;
480 /// The name of the method on the target specific operand to call to add the
481 /// target specific operand to an MCInst. If not set, this will default to
482 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
483 /// signature should be:
484 /// void addFooOperands(MCInst &Inst, unsigned N) const;
485 string RenderMethod = ?;
487 /// The name of the method on the target specific operand to call to custom
488 /// handle the operand parsing. This is useful when the operands do not relate
489 /// to immediates or registers and are very instruction specific (as flags to
490 /// set in a processor register, coprocessor number, ...).
491 string ParserMethod = ?;
494 def ImmAsmOperand : AsmOperandClass {
498 /// Operand Types - These provide the built-in operand types that may be used
499 /// by a target. Targets can optionally provide their own operand types as
500 /// needed, though this should not be needed for RISC targets.
501 class Operand<ValueType ty> {
503 string PrintMethod = "printOperand";
504 string EncoderMethod = "";
505 string DecoderMethod = "";
506 string AsmOperandLowerMethod = ?;
507 string OperandType = "OPERAND_UNKNOWN";
508 dag MIOperandInfo = (ops);
510 // ParserMatchClass - The "match class" that operands of this type fit
511 // in. Match classes are used to define the order in which instructions are
512 // match, to ensure that which instructions gets matched is deterministic.
514 // The target specific parser must be able to classify an parsed operand into
515 // a unique class, which does not partially overlap with any other classes. It
516 // can match a subset of some other class, in which case the AsmOperandClass
517 // should declare the other operand as one of its super classes.
518 AsmOperandClass ParserMatchClass = ImmAsmOperand;
521 class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> {
522 // RegClass - The register class of the operand.
523 RegisterClass RegClass = regclass;
524 // PrintMethod - The target method to call to print register operands of
525 // this type. The method normally will just use an alt-name index to look
526 // up the name to print. Default to the generic printOperand().
527 string PrintMethod = pm;
528 // ParserMatchClass - The "match class" that operands of this type fit
529 // in. Match classes are used to define the order in which instructions are
530 // match, to ensure that which instructions gets matched is deterministic.
532 // The target specific parser must be able to classify an parsed operand into
533 // a unique class, which does not partially overlap with any other classes. It
534 // can match a subset of some other class, in which case the AsmOperandClass
535 // should declare the other operand as one of its super classes.
536 AsmOperandClass ParserMatchClass;
539 let OperandType = "OPERAND_IMMEDIATE" in {
540 def i1imm : Operand<i1>;
541 def i8imm : Operand<i8>;
542 def i16imm : Operand<i16>;
543 def i32imm : Operand<i32>;
544 def i64imm : Operand<i64>;
546 def f32imm : Operand<f32>;
547 def f64imm : Operand<f64>;
550 /// zero_reg definition - Special node to stand for the zero register.
554 /// PredicateOperand - This can be used to define a predicate operand for an
555 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
556 /// AlwaysVal specifies the value of this predicate when set to "always
558 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
560 let MIOperandInfo = OpTypes;
561 dag DefaultOps = AlwaysVal;
564 /// OptionalDefOperand - This is used to define a optional definition operand
565 /// for an instruction. DefaultOps is the register the operand represents if
566 /// none is supplied, e.g. zero_reg.
567 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
569 let MIOperandInfo = OpTypes;
570 dag DefaultOps = defaultops;
574 // InstrInfo - This class should only be instantiated once to provide parameters
575 // which are global to the target machine.
578 // Target can specify its instructions in either big or little-endian formats.
579 // For instance, while both Sparc and PowerPC are big-endian platforms, the
580 // Sparc manual specifies its instructions in the format [31..0] (big), while
581 // PowerPC specifies them using the format [0..31] (little).
582 bit isLittleEndianEncoding = 0;
585 // Standard Pseudo Instructions.
586 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
587 // Only these instructions are allowed in the TargetOpcode namespace.
588 let isCodeGenOnly = 1, Namespace = "TargetOpcode" in {
589 def PHI : Instruction {
590 let OutOperandList = (outs);
591 let InOperandList = (ins variable_ops);
592 let AsmString = "PHINODE";
594 def INLINEASM : Instruction {
595 let OutOperandList = (outs);
596 let InOperandList = (ins variable_ops);
598 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
600 def PROLOG_LABEL : Instruction {
601 let OutOperandList = (outs);
602 let InOperandList = (ins i32imm:$id);
605 let isNotDuplicable = 1;
607 def EH_LABEL : Instruction {
608 let OutOperandList = (outs);
609 let InOperandList = (ins i32imm:$id);
612 let isNotDuplicable = 1;
614 def GC_LABEL : Instruction {
615 let OutOperandList = (outs);
616 let InOperandList = (ins i32imm:$id);
619 let isNotDuplicable = 1;
621 def KILL : Instruction {
622 let OutOperandList = (outs);
623 let InOperandList = (ins variable_ops);
625 let neverHasSideEffects = 1;
627 def EXTRACT_SUBREG : Instruction {
628 let OutOperandList = (outs unknown:$dst);
629 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
631 let neverHasSideEffects = 1;
633 def INSERT_SUBREG : Instruction {
634 let OutOperandList = (outs unknown:$dst);
635 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
637 let neverHasSideEffects = 1;
638 let Constraints = "$supersrc = $dst";
640 def IMPLICIT_DEF : Instruction {
641 let OutOperandList = (outs unknown:$dst);
642 let InOperandList = (ins);
644 let neverHasSideEffects = 1;
645 let isReMaterializable = 1;
646 let isAsCheapAsAMove = 1;
648 def SUBREG_TO_REG : Instruction {
649 let OutOperandList = (outs unknown:$dst);
650 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
652 let neverHasSideEffects = 1;
654 def COPY_TO_REGCLASS : Instruction {
655 let OutOperandList = (outs unknown:$dst);
656 let InOperandList = (ins unknown:$src, i32imm:$regclass);
658 let neverHasSideEffects = 1;
659 let isAsCheapAsAMove = 1;
661 def DBG_VALUE : Instruction {
662 let OutOperandList = (outs);
663 let InOperandList = (ins variable_ops);
664 let AsmString = "DBG_VALUE";
665 let neverHasSideEffects = 1;
667 def REG_SEQUENCE : Instruction {
668 let OutOperandList = (outs unknown:$dst);
669 let InOperandList = (ins variable_ops);
671 let neverHasSideEffects = 1;
672 let isAsCheapAsAMove = 1;
674 def COPY : Instruction {
675 let OutOperandList = (outs unknown:$dst);
676 let InOperandList = (ins unknown:$src);
678 let neverHasSideEffects = 1;
679 let isAsCheapAsAMove = 1;
683 //===----------------------------------------------------------------------===//
684 // AsmParser - This class can be implemented by targets that wish to implement
687 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
688 // syntax on X86 for example).
691 // AsmParserClassName - This specifies the suffix to use for the asmparser
692 // class. Generated AsmParser classes are always prefixed with the target
694 string AsmParserClassName = "AsmParser";
696 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
697 // function of the AsmParser class to call on every matched instruction.
698 // This can be used to perform target specific instruction post-processing.
699 string AsmParserInstCleanup = "";
701 // Variant - AsmParsers can be of multiple different variants. Variants are
702 // used to support targets that need to parser multiple formats for the
703 // assembly language.
706 // CommentDelimiter - If given, the delimiter string used to recognize
707 // comments which are hard coded in the .td assembler strings for individual
709 string CommentDelimiter = "";
711 // RegisterPrefix - If given, the token prefix which indicates a register
712 // token. This is used by the matcher to automatically recognize hard coded
713 // register tokens as constrained registers, instead of tokens, for the
714 // purposes of matching.
715 string RegisterPrefix = "";
717 def DefaultAsmParser : AsmParser;
719 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
720 /// matches instructions and aliases.
721 class AssemblerPredicate<string cond> {
722 bit AssemblerMatcherPredicate = 1;
723 string AssemblerCondString = cond;
728 /// MnemonicAlias - This class allows targets to define assembler mnemonic
729 /// aliases. This should be used when all forms of one mnemonic are accepted
730 /// with a different mnemonic. For example, X86 allows:
731 /// sal %al, 1 -> shl %al, 1
732 /// sal %ax, %cl -> shl %ax, %cl
733 /// sal %eax, %cl -> shl %eax, %cl
734 /// etc. Though "sal" is accepted with many forms, all of them are directly
735 /// translated to a shl, so it can be handled with (in the case of X86, it
736 /// actually has one for each suffix as well):
737 /// def : MnemonicAlias<"sal", "shl">;
739 /// Mnemonic aliases are mapped before any other translation in the match phase,
740 /// and do allow Requires predicates, e.g.:
742 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
743 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
745 class MnemonicAlias<string From, string To> {
746 string FromMnemonic = From;
747 string ToMnemonic = To;
749 // Predicates - Predicates that must be true for this remapping to happen.
750 list<Predicate> Predicates = [];
753 /// InstAlias - This defines an alternate assembly syntax that is allowed to
754 /// match an instruction that has a different (more canonical) assembly
756 class InstAlias<string Asm, dag Result, bit Emit = 0b1> {
757 string AsmString = Asm; // The .s format to match the instruction with.
758 dag ResultInst = Result; // The MCInst to generate.
759 bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
761 // Predicates - Predicates that must be true for this to match.
762 list<Predicate> Predicates = [];
765 //===----------------------------------------------------------------------===//
766 // AsmWriter - This class can be implemented by targets that need to customize
767 // the format of the .s file writer.
769 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
770 // on X86 for example).
773 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
774 // class. Generated AsmWriter classes are always prefixed with the target
776 string AsmWriterClassName = "AsmPrinter";
778 // Variant - AsmWriters can be of multiple different variants. Variants are
779 // used to support targets that need to emit assembly code in ways that are
780 // mostly the same for different targets, but have minor differences in
781 // syntax. If the asmstring contains {|} characters in them, this integer
782 // will specify which alternative to use. For example "{x|y|z}" with Variant
783 // == 1, will expand to "y".
787 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
788 // layout, the asmwriter can actually generate output in this columns (in
789 // verbose-asm mode). These two values indicate the width of the first column
790 // (the "opcode" area) and the width to reserve for subsequent operands. When
791 // verbose asm mode is enabled, operands will be indented to respect this.
792 int FirstOperandColumn = -1;
794 // OperandSpacing - Space between operand columns.
795 int OperandSpacing = -1;
797 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
798 // generation of the printInstruction() method. For MC printers, it takes
799 // an MCInstr* operand, otherwise it takes a MachineInstr*.
800 bit isMCAsmWriter = 0;
802 def DefaultAsmWriter : AsmWriter;
805 //===----------------------------------------------------------------------===//
806 // Target - This class contains the "global" target information
809 // InstructionSet - Instruction set description for this target.
810 InstrInfo InstructionSet;
812 // AssemblyParsers - The AsmParser instances available for this target.
813 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
815 // AssemblyWriters - The AsmWriter instances available for this target.
816 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
819 //===----------------------------------------------------------------------===//
820 // SubtargetFeature - A characteristic of the chip set.
822 class SubtargetFeature<string n, string a, string v, string d,
823 list<SubtargetFeature> i = []> {
824 // Name - Feature name. Used by command line (-mattr=) to determine the
825 // appropriate target chip.
829 // Attribute - Attribute to be set by feature.
831 string Attribute = a;
833 // Value - Value the attribute to be set to by feature.
837 // Desc - Feature description. Used by command line (-mattr=) to display help
842 // Implies - Features that this feature implies are present. If one of those
843 // features isn't set, then this one shouldn't be set either.
845 list<SubtargetFeature> Implies = i;
848 //===----------------------------------------------------------------------===//
849 // Processor chip sets - These values represent each of the chip sets supported
850 // by the scheduler. Each Processor definition requires corresponding
851 // instruction itineraries.
853 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
854 // Name - Chip set name. Used by command line (-mcpu=) to determine the
855 // appropriate target chip.
859 // ProcItin - The scheduling information for the target processor.
861 ProcessorItineraries ProcItin = pi;
863 // Features - list of
864 list<SubtargetFeature> Features = f;
867 //===----------------------------------------------------------------------===//
868 // Pull in the common support for calling conventions.
870 include "llvm/Target/TargetCallingConv.td"
872 //===----------------------------------------------------------------------===//
873 // Pull in the common support for DAG isel generation.
875 include "llvm/Target/TargetSelectionDAG.td"