1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
25 string Namespace = "";
27 // This explicit numbering is going away after RegisterClass::SubRegClassList
32 // Register - You should define one instance of this class for each register
33 // in the target machine. String n will become the "name" of the register.
34 class Register<string n> {
35 string Namespace = "";
38 // SpillSize - If this value is set to a non-zero value, it is the size in
39 // bits of the spill slot required to hold this register. If this value is
40 // set to zero, the information is inferred from any register classes the
41 // register belongs to.
44 // SpillAlignment - This value is used to specify the alignment required for
45 // spilling the register. Like SpillSize, this should only be explicitly
46 // specified if the register is not in a register class.
47 int SpillAlignment = 0;
49 // Aliases - A list of registers that this register overlaps with. A read or
50 // modification of this register can potentially read or modify the aliased
52 list<Register> Aliases = [];
54 // SubRegs - A list of registers that are parts of this register. Note these
55 // are "immediate" sub-registers and the registers within the list do not
56 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
58 list<Register> SubRegs = [];
60 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
61 // These values can be determined by locating the <target>.h file in the
62 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
63 // order of these names correspond to the enumeration used by gcc. A value of
64 // -1 indicates that the gcc number is undefined and -2 that register number
65 // is invalid for this mode/flavour.
66 list<int> DwarfNumbers = [];
69 // RegisterWithSubRegs - This can be used to define instances of Register which
70 // need to specify sub-registers.
71 // List "subregs" specifies which registers are sub-registers to this one. This
72 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
73 // This allows the code generator to be careful not to put two values with
74 // overlapping live ranges into registers which alias.
75 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
76 let SubRegs = subregs;
79 // SubRegSet - This can be used to define a specific mapping of registers to
80 // indices, for use as named subregs of a particular physical register. Each
81 // register in 'subregs' becomes an addressable subregister at index 'n' of the
82 // corresponding register in 'regs'.
83 class SubRegSet<int n, list<Register> regs, list<Register> subregs> {
86 list<Register> From = regs;
87 list<Register> To = subregs;
90 // RegisterClass - Now that all of the registers are defined, and aliases
91 // between registers are defined, specify which registers belong to which
92 // register classes. This also defines the default allocation order of
93 // registers by register allocators.
95 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
96 list<Register> regList> {
97 string Namespace = namespace;
99 // RegType - Specify the list ValueType of the registers in this register
100 // class. Note that all registers in a register class must have the same
101 // ValueTypes. This is a list because some targets permit storing different
102 // types in same register, for example vector values with 128-bit total size,
103 // but different count/size of items, like SSE on x86.
105 list<ValueType> RegTypes = regTypes;
107 // Size - Specify the spill size in bits of the registers. A default value of
108 // zero lets tablgen pick an appropriate size.
111 // Alignment - Specify the alignment required of the registers when they are
112 // stored or loaded to memory.
114 int Alignment = alignment;
116 // CopyCost - This value is used to specify the cost of copying a value
117 // between two registers in this register class. The default value is one
118 // meaning it takes a single instruction to perform the copying. A negative
119 // value means copying is extremely expensive or impossible.
122 // MemberList - Specify which registers are in this class. If the
123 // allocation_order_* method are not specified, this also defines the order of
124 // allocation used by the register allocator.
126 list<Register> MemberList = regList;
128 // SubClassList - Specify which register classes correspond to subregisters
129 // of this class. The order should be by subregister set index.
130 list<RegisterClass> SubRegClassList = [];
132 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
133 // code into a generated register class. The normal usage of this is to
134 // overload virtual methods.
135 code MethodProtos = [{}];
136 code MethodBodies = [{}];
140 //===----------------------------------------------------------------------===//
141 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
142 // to the register numbering used by gcc and gdb. These values are used by a
143 // debug information writer to describe where values may be located during
145 class DwarfRegNum<list<int> Numbers> {
146 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
147 // These values can be determined by locating the <target>.h file in the
148 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
149 // order of these names correspond to the enumeration used by gcc. A value of
150 // -1 indicates that the gcc number is undefined and -2 that register number is
151 // invalid for this mode/flavour.
152 list<int> DwarfNumbers = Numbers;
155 //===----------------------------------------------------------------------===//
156 // Pull in the common support for scheduling
158 include "llvm/Target/TargetSchedule.td"
160 class Predicate; // Forward def
162 //===----------------------------------------------------------------------===//
163 // Instruction set description - These classes correspond to the C++ classes in
164 // the Target/TargetInstrInfo.h file.
167 string Namespace = "";
169 dag OutOperandList; // An dag containing the MI def operand list.
170 dag InOperandList; // An dag containing the MI use operand list.
171 string AsmString = ""; // The .s format to print the instruction with.
173 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
174 // otherwise, uninitialized.
177 // The follow state will eventually be inferred automatically from the
178 // instruction pattern.
180 list<Register> Uses = []; // Default to using no non-operand registers
181 list<Register> Defs = []; // Default to modifying no non-operand registers
183 // Predicates - List of predicates which will be turned into isel matching
185 list<Predicate> Predicates = [];
190 // Added complexity passed onto matching pattern.
191 int AddedComplexity = 0;
193 // These bits capture information about the high-level semantics of the
195 bit isReturn = 0; // Is this instruction a return instruction?
196 bit isBranch = 0; // Is this instruction a branch instruction?
197 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
198 bit isBarrier = 0; // Can control flow fall through this instruction?
199 bit isCall = 0; // Is this instruction a call instruction?
200 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
201 bit mayLoad = 0; // Is it possible for this inst to read memory?
202 bit mayStore = 0; // Is it possible for this inst to write memory?
203 bit isTwoAddress = 0; // Is this a two address instruction?
204 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
205 bit isCommutable = 0; // Is this 3 operand instruction commutable?
206 bit isTerminator = 0; // Is this part of the terminator for a basic block?
207 bit isReMaterializable = 0; // Is this instruction re-materializable?
208 bit isPredicable = 0; // Is this instruction predicable?
209 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
210 bit usesCustomInserter = 0; // Pseudo instr needing special help.
211 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
212 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
213 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
214 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
215 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
217 // Side effect flags - When set, the flags have these meanings:
219 // hasSideEffects - The instruction has side effects that are not
220 // captured by any operands of the instruction or other flags.
222 // neverHasSideEffects - Set on an instruction with no pattern if it has no
224 bit hasSideEffects = 0;
225 bit neverHasSideEffects = 0;
227 // Is this instruction a "real" instruction (with a distinct machine
228 // encoding), or is it a pseudo instruction used for codegen modeling
230 bit isCodeGenOnly = 0;
232 // Is this instruction a pseudo instruction for use by the assembler parser.
233 bit isAsmParserOnly = 0;
235 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
237 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
239 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
240 /// be encoded into the output machineinstr.
241 string DisableEncoding = "";
243 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
244 bits<32> TSFlags = 0;
247 /// Predicates - These are extra conditionals which are turned into instruction
248 /// selector matching code. Currently each predicate is just a string.
249 class Predicate<string cond> {
250 string CondString = cond;
253 /// NoHonorSignDependentRounding - This predicate is true if support for
254 /// sign-dependent-rounding is not enabled.
255 def NoHonorSignDependentRounding
256 : Predicate<"!HonorSignDependentRoundingFPMath()">;
258 class Requires<list<Predicate> preds> {
259 list<Predicate> Predicates = preds;
262 /// ops definition - This is just a simple marker used to identify the operands
263 /// list for an instruction. outs and ins are identical both syntatically and
264 /// semantically, they are used to define def operands and use operands to
265 /// improve readibility. This should be used like this:
266 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
271 /// variable_ops definition - Mark this instruction as taking a variable number
276 /// PointerLikeRegClass - Values that are designed to have pointer width are
277 /// derived from this. TableGen treats the register class as having a symbolic
278 /// type that it doesn't know, and resolves the actual regclass to use by using
279 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
280 class PointerLikeRegClass<int Kind> {
281 int RegClassKind = Kind;
285 /// ptr_rc definition - Mark this operand as being a pointer value whose
286 /// register class is resolved dynamically via a callback to TargetInstrInfo.
287 /// FIXME: We should probably change this to a class which contain a list of
288 /// flags. But currently we have but one flag.
289 def ptr_rc : PointerLikeRegClass<0>;
291 /// unknown definition - Mark this operand as being of unknown type, causing
292 /// it to be resolved by inference in the context it is used.
295 /// AsmOperandClass - Representation for the kinds of operands which the target
296 /// specific parser can create and the assembly matcher may need to distinguish.
298 /// Operand classes are used to define the order in which instructions are
299 /// matched, to ensure that the instruction which gets matched for any
300 /// particular list of operands is deterministic.
302 /// The target specific parser must be able to classify a parsed operand into a
303 /// unique class which does not partially overlap with any other classes. It can
304 /// match a subset of some other class, in which case the super class field
305 /// should be defined.
306 class AsmOperandClass {
307 /// The name to use for this class, which should be usable as an enum value.
310 /// The super classes of this operand.
311 list<AsmOperandClass> SuperClasses = [];
313 /// The name of the method on the target specific operand to call to test
314 /// whether the operand is an instance of this class. If not set, this will
315 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
316 /// signature should be:
317 /// bool isFoo() const;
318 string PredicateMethod = ?;
320 /// The name of the method on the target specific operand to call to add the
321 /// target specific operand to an MCInst. If not set, this will default to
322 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
323 /// signature should be:
324 /// void addFooOperands(MCInst &Inst, unsigned N) const;
325 string RenderMethod = ?;
328 def ImmAsmOperand : AsmOperandClass {
332 /// Operand Types - These provide the built-in operand types that may be used
333 /// by a target. Targets can optionally provide their own operand types as
334 /// needed, though this should not be needed for RISC targets.
335 class Operand<ValueType ty> {
337 string PrintMethod = "printOperand";
338 string AsmOperandLowerMethod = ?;
339 dag MIOperandInfo = (ops);
341 // ParserMatchClass - The "match class" that operands of this type fit
342 // in. Match classes are used to define the order in which instructions are
343 // match, to ensure that which instructions gets matched is deterministic.
345 // The target specific parser must be able to classify an parsed operand into
346 // a unique class, which does not partially overlap with any other classes. It
347 // can match a subset of some other class, in which case the AsmOperandClass
348 // should declare the other operand as one of its super classes.
349 AsmOperandClass ParserMatchClass = ImmAsmOperand;
352 def i1imm : Operand<i1>;
353 def i8imm : Operand<i8>;
354 def i16imm : Operand<i16>;
355 def i32imm : Operand<i32>;
356 def i64imm : Operand<i64>;
358 def f32imm : Operand<f32>;
359 def f64imm : Operand<f64>;
361 /// zero_reg definition - Special node to stand for the zero register.
365 /// PredicateOperand - This can be used to define a predicate operand for an
366 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
367 /// AlwaysVal specifies the value of this predicate when set to "always
369 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
371 let MIOperandInfo = OpTypes;
372 dag DefaultOps = AlwaysVal;
375 /// OptionalDefOperand - This is used to define a optional definition operand
376 /// for an instruction. DefaultOps is the register the operand represents if
377 /// none is supplied, e.g. zero_reg.
378 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
380 let MIOperandInfo = OpTypes;
381 dag DefaultOps = defaultops;
385 // InstrInfo - This class should only be instantiated once to provide parameters
386 // which are global to the target machine.
389 // Target can specify its instructions in either big or little-endian formats.
390 // For instance, while both Sparc and PowerPC are big-endian platforms, the
391 // Sparc manual specifies its instructions in the format [31..0] (big), while
392 // PowerPC specifies them using the format [0..31] (little).
393 bit isLittleEndianEncoding = 0;
396 // Standard Pseudo Instructions.
397 let isCodeGenOnly = 1 in {
398 def PHI : Instruction {
399 let OutOperandList = (outs);
400 let InOperandList = (ins variable_ops);
401 let AsmString = "PHINODE";
402 let Namespace = "TargetOpcode";
404 def INLINEASM : Instruction {
405 let OutOperandList = (outs);
406 let InOperandList = (ins variable_ops);
408 let Namespace = "TargetOpcode";
410 def DBG_LABEL : Instruction {
411 let OutOperandList = (outs);
412 let InOperandList = (ins i32imm:$id);
414 let Namespace = "TargetOpcode";
416 let isNotDuplicable = 1;
418 def EH_LABEL : Instruction {
419 let OutOperandList = (outs);
420 let InOperandList = (ins i32imm:$id);
422 let Namespace = "TargetOpcode";
424 let isNotDuplicable = 1;
426 def GC_LABEL : Instruction {
427 let OutOperandList = (outs);
428 let InOperandList = (ins i32imm:$id);
430 let Namespace = "TargetOpcode";
432 let isNotDuplicable = 1;
434 def KILL : Instruction {
435 let OutOperandList = (outs);
436 let InOperandList = (ins variable_ops);
438 let Namespace = "TargetOpcode";
439 let neverHasSideEffects = 1;
441 def EXTRACT_SUBREG : Instruction {
442 let OutOperandList = (outs unknown:$dst);
443 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
445 let Namespace = "TargetOpcode";
446 let neverHasSideEffects = 1;
448 def INSERT_SUBREG : Instruction {
449 let OutOperandList = (outs unknown:$dst);
450 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
452 let Namespace = "TargetOpcode";
453 let neverHasSideEffects = 1;
454 let Constraints = "$supersrc = $dst";
456 def IMPLICIT_DEF : Instruction {
457 let OutOperandList = (outs unknown:$dst);
458 let InOperandList = (ins);
460 let Namespace = "TargetOpcode";
461 let neverHasSideEffects = 1;
462 let isReMaterializable = 1;
463 let isAsCheapAsAMove = 1;
465 def SUBREG_TO_REG : Instruction {
466 let OutOperandList = (outs unknown:$dst);
467 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
469 let Namespace = "TargetOpcode";
470 let neverHasSideEffects = 1;
472 def COPY_TO_REGCLASS : Instruction {
473 let OutOperandList = (outs unknown:$dst);
474 let InOperandList = (ins unknown:$src, i32imm:$regclass);
476 let Namespace = "TargetOpcode";
477 let neverHasSideEffects = 1;
478 let isAsCheapAsAMove = 1;
480 def DBG_VALUE : Instruction {
481 let OutOperandList = (outs);
482 let InOperandList = (ins variable_ops);
483 let AsmString = "DBG_VALUE";
484 let Namespace = "TargetOpcode";
485 let isAsCheapAsAMove = 1;
488 def REG_SEQUENCE : Instruction {
489 let OutOperandList = (outs unknown:$dst);
490 let InOperandList = (ins variable_ops);
492 let Namespace = "TargetOpcode";
493 let neverHasSideEffects = 1;
494 let isAsCheapAsAMove = 1;
498 //===----------------------------------------------------------------------===//
499 // AsmParser - This class can be implemented by targets that wish to implement
502 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
503 // syntax on X86 for example).
506 // AsmParserClassName - This specifies the suffix to use for the asmparser
507 // class. Generated AsmParser classes are always prefixed with the target
509 string AsmParserClassName = "AsmParser";
511 // AsmParserInstCleanup - If non-empty, this is the name of a custom function on the
512 // AsmParser class to call on every matched instruction. This can be used to
513 // perform target specific instruction post-processing.
514 string AsmParserInstCleanup = "";
516 // MatchInstructionName - The name of the instruction matching function to
518 string MatchInstructionName = "MatchInstruction";
520 // Variant - AsmParsers can be of multiple different variants. Variants are
521 // used to support targets that need to parser multiple formats for the
522 // assembly language.
525 // CommentDelimiter - If given, the delimiter string used to recognize
526 // comments which are hard coded in the .td assembler strings for individual
528 string CommentDelimiter = "";
530 // RegisterPrefix - If given, the token prefix which indicates a register
531 // token. This is used by the matcher to automatically recognize hard coded
532 // register tokens as constrained registers, instead of tokens, for the
533 // purposes of matching.
534 string RegisterPrefix = "";
536 def DefaultAsmParser : AsmParser;
539 //===----------------------------------------------------------------------===//
540 // AsmWriter - This class can be implemented by targets that need to customize
541 // the format of the .s file writer.
543 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
544 // on X86 for example).
547 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
548 // class. Generated AsmWriter classes are always prefixed with the target
550 string AsmWriterClassName = "AsmPrinter";
552 // InstFormatName - AsmWriters can specify the name of the format string to
553 // print instructions with.
554 string InstFormatName = "AsmString";
556 // Variant - AsmWriters can be of multiple different variants. Variants are
557 // used to support targets that need to emit assembly code in ways that are
558 // mostly the same for different targets, but have minor differences in
559 // syntax. If the asmstring contains {|} characters in them, this integer
560 // will specify which alternative to use. For example "{x|y|z}" with Variant
561 // == 1, will expand to "y".
565 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
566 // layout, the asmwriter can actually generate output in this columns (in
567 // verbose-asm mode). These two values indicate the width of the first column
568 // (the "opcode" area) and the width to reserve for subsequent operands. When
569 // verbose asm mode is enabled, operands will be indented to respect this.
570 int FirstOperandColumn = -1;
572 // OperandSpacing - Space between operand columns.
573 int OperandSpacing = -1;
575 def DefaultAsmWriter : AsmWriter;
578 //===----------------------------------------------------------------------===//
579 // Target - This class contains the "global" target information
582 // InstructionSet - Instruction set description for this target.
583 InstrInfo InstructionSet;
585 // AssemblyParsers - The AsmParser instances available for this target.
586 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
588 // AssemblyWriters - The AsmWriter instances available for this target.
589 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
592 //===----------------------------------------------------------------------===//
593 // SubtargetFeature - A characteristic of the chip set.
595 class SubtargetFeature<string n, string a, string v, string d,
596 list<SubtargetFeature> i = []> {
597 // Name - Feature name. Used by command line (-mattr=) to determine the
598 // appropriate target chip.
602 // Attribute - Attribute to be set by feature.
604 string Attribute = a;
606 // Value - Value the attribute to be set to by feature.
610 // Desc - Feature description. Used by command line (-mattr=) to display help
615 // Implies - Features that this feature implies are present. If one of those
616 // features isn't set, then this one shouldn't be set either.
618 list<SubtargetFeature> Implies = i;
621 //===----------------------------------------------------------------------===//
622 // Processor chip sets - These values represent each of the chip sets supported
623 // by the scheduler. Each Processor definition requires corresponding
624 // instruction itineraries.
626 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
627 // Name - Chip set name. Used by command line (-mcpu=) to determine the
628 // appropriate target chip.
632 // ProcItin - The scheduling information for the target processor.
634 ProcessorItineraries ProcItin = pi;
636 // Features - list of
637 list<SubtargetFeature> Features = f;
640 //===----------------------------------------------------------------------===//
641 // Pull in the common support for calling conventions.
643 include "llvm/Target/TargetCallingConv.td"
645 //===----------------------------------------------------------------------===//
646 // Pull in the common support for DAG isel generation.
648 include "llvm/Target/TargetSelectionDAG.td"