1 //===- Target/MRegisterInfo.h - Target Register Information -------*-C++-*-===//
3 // This file describes an abstract interface used to get information about a
4 // target machines register file. This information is used for a variety of
5 // purposed, especially register allocation.
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_TARGET_MREGISTERINFO_H
10 #define LLVM_TARGET_MREGISTERINFO_H
12 #include "llvm/CodeGen/MachineBasicBlock.h"
16 class MachineFunction;
18 /// MRegisterDesc - This record contains all of the information known about a
19 /// particular register. The AliasSet field (if not null) contains a pointer to
20 /// a Zero terminated array of registers that this register aliases. This is
21 /// needed for architectures like X86 which have AL alias AX alias EAX.
22 /// Registers that this does not apply to simply should set this to null.
24 struct MRegisterDesc {
25 const char *Name; // Assembly language name for the register
26 const unsigned *AliasSet; // Register Alias Set, described above
27 unsigned Flags; // Flags identifying register properties (below)
28 unsigned TSFlags; // Target Specific Flags
31 /// MRF namespace - This namespace contains flags that pertain to machine
34 namespace MRF { // MRF = Machine Register Flags
36 INT8 = 1 << 0, // This is an 8 bit integer register
37 INT16 = 1 << 1, // This is a 16 bit integer register
38 INT32 = 1 << 2, // This is a 32 bit integer register
39 INT64 = 1 << 3, // This is a 64 bit integer register
40 INT128 = 1 << 4, // This is a 128 bit integer register
42 FP32 = 1 << 5, // This is a 32 bit floating point register
43 FP64 = 1 << 6, // This is a 64 bit floating point register
44 FP80 = 1 << 7, // This is a 80 bit floating point register
45 FP128 = 1 << 8, // This is a 128 bit floating point register
49 class TargetRegisterClass {
51 typedef const unsigned* iterator;
52 typedef const unsigned* const_iterator;
55 const unsigned RegSize; // Size of register in bytes
56 const iterator RegsBegin, RegsEnd;
58 TargetRegisterClass(unsigned RS, iterator RB, iterator RE)
59 : RegSize(RS), RegsBegin(RB), RegsEnd(RE) {}
60 virtual ~TargetRegisterClass() {} // Allow subclasses
62 iterator begin() const { return RegsBegin; }
63 iterator end() const { return RegsEnd; }
65 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
66 unsigned getRegister(unsigned i) const {
67 assert(i < getNumRegs() && "Register number out of range!");
71 unsigned getDataSize() const { return RegSize; }
75 /// MRegisterInfo base class - We assume that the target defines a static array
76 /// of MRegisterDesc objects that represent all of the machine registers that
77 /// the target has. As such, we simply have to track a pointer to this array so
78 /// that we can turn register number into a register descriptor.
82 typedef const TargetRegisterClass * const * regclass_iterator;
84 const MRegisterDesc *Desc; // Pointer to the descriptor array
85 unsigned NumRegs; // Number of entries in the array
87 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
89 const TargetRegisterClass **PhysRegClasses; // Reg class for each register
91 MRegisterInfo(const MRegisterDesc *D, unsigned NR,
92 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd);
93 virtual ~MRegisterInfo();
96 enum { // Define some target independant constants
97 /// NoRegister - This 'hard' register is a 'noop' register for all backends.
98 /// This is used as the destination register for instructions that do not
99 /// produce a value. Some frontends may use this as an operand register to
100 /// mean special things, for example, the Sparc backend uses R0 to mean %g0
101 /// which always PRODUCES the value 0. The X86 backend does not use this
102 /// value as an operand register, except for memory references.
106 /// FirstVirtualRegister - This is the first register number that is
107 /// considered to be a 'virtual' register, which is part of the SSA
108 /// namespace. This must be the same for all targets, which means that each
109 /// target is limited to 1024 registers.
111 FirstVirtualRegister = 1024,
114 const MRegisterDesc &operator[](unsigned RegNo) const {
115 assert(RegNo < NumRegs &&
116 "Attempting to access record for invalid register number!");
120 /// Provide a get method, equivalent to [], but more useful if we have a
121 /// pointer to this object.
123 const MRegisterDesc &get(unsigned RegNo) const { return operator[](RegNo); }
125 /// getRegClass - Return the register class for the specified physical
128 const TargetRegisterClass *getRegClass(unsigned RegNo) const {
129 assert(RegNo < NumRegs && "Register number out of range!");
130 assert(PhysRegClasses[RegNo] && "Register is not in a class!");
131 return PhysRegClasses[RegNo];
134 /// getAliasSet - Return the set of registers aliased by the specified
135 /// register, or a null list of there are none. The list returned is zero
138 const unsigned *getAliasSet(unsigned RegNo) const {
139 return get(RegNo).AliasSet;
142 virtual unsigned getFramePointer() const = 0;
143 virtual unsigned getStackPointer() const = 0;
145 virtual const unsigned* getCalleeSaveRegs() const = 0;
146 virtual const unsigned* getCallerSaveRegs() const = 0;
149 //===--------------------------------------------------------------------===//
150 // Register Class Information
153 /// Register class iterators
154 regclass_iterator regclass_begin() const { return RegClassBegin; }
155 regclass_iterator regclass_end() const { return RegClassEnd; }
157 unsigned getNumRegClasses() const {
158 return regclass_end()-regclass_begin();
160 virtual const TargetRegisterClass* getRegClassForType(const Type* Ty) const=0;
163 //===--------------------------------------------------------------------===//
164 // Interfaces used primarily by the register allocator to move data around
165 // between registers, immediates and memory.
168 virtual void emitPrologue(MachineFunction &MF, unsigned Bytes) const = 0;
169 virtual void emitEpilogue(MachineBasicBlock &MBB, unsigned Bytes) const = 0;
171 virtual MachineBasicBlock::iterator
172 storeReg2RegOffset(MachineBasicBlock &MBB,
173 MachineBasicBlock::iterator MBBI,
174 unsigned SrcReg, unsigned DestReg,
175 unsigned ImmOffset, unsigned dataSize) const = 0;
177 virtual MachineBasicBlock::iterator
178 loadRegOffset2Reg(MachineBasicBlock &MBB,
179 MachineBasicBlock::iterator MBBI,
180 unsigned DestReg, unsigned SrcReg,
181 unsigned ImmOffset, unsigned dataSize) const = 0;
183 virtual MachineBasicBlock::iterator
184 moveReg2Reg(MachineBasicBlock &MBB,
185 MachineBasicBlock::iterator MBBI,
186 unsigned DestReg, unsigned SrcReg, unsigned dataSize) const = 0;
188 virtual MachineBasicBlock::iterator
189 moveImm2Reg(MachineBasicBlock &MBB,
190 MachineBasicBlock::iterator MBBI,
191 unsigned DestReg, unsigned Imm, unsigned dataSize) const = 0;