1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // This file describes an abstract interface used to get information about a
4 // target machines register file. This information is used for a variety of
5 // purposed, especially register allocation.
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_TARGET_MREGISTERINFO_H
10 #define LLVM_TARGET_MREGISTERINFO_H
12 #include "llvm/CodeGen/MachineBasicBlock.h"
16 class MachineFunction;
18 /// MRegisterDesc - This record contains all of the information known about a
19 /// particular register. The AliasSet field (if not null) contains a pointer to
20 /// a Zero terminated array of registers that this register aliases. This is
21 /// needed for architectures like X86 which have AL alias AX alias EAX.
22 /// Registers that this does not apply to simply should set this to null.
24 struct MRegisterDesc {
25 const char *Name; // Assembly language name for the register
26 const unsigned *AliasSet; // Register Alias Set, described above
27 unsigned Flags; // Flags identifying register properties (below)
28 unsigned TSFlags; // Target Specific Flags
31 class TargetRegisterClass {
33 typedef const unsigned* iterator;
34 typedef const unsigned* const_iterator;
37 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
38 const iterator RegsBegin, RegsEnd;
40 TargetRegisterClass(unsigned RS, unsigned Al, iterator RB, iterator RE)
41 : RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
42 virtual ~TargetRegisterClass() {} // Allow subclasses
44 // begin/end - Return all of the registers in this class.
45 iterator begin() const { return RegsBegin; }
46 iterator end() const { return RegsEnd; }
48 // getNumRegs - Return the number of registers in this class
49 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
51 // getRegister - Return the specified register in the class
52 unsigned getRegister(unsigned i) const {
53 assert(i < getNumRegs() && "Register number out of range!");
57 /// allocation_order_begin/end - These methods define a range of registers
58 /// which specify the registers in this class that are valid to register
59 /// allocate, and the preferred order to allocate them in. For example,
60 /// callee saved registers should be at the end of the list, because it is
61 /// cheaper to allocate caller saved registers.
63 /// These methods take a MachineFunction argument, which can be used to tune
64 /// the allocatable registers based on the characteristics of the function.
65 /// One simple example is that the frame pointer register can be used if
66 /// frame-pointer-elimination is performed.
68 /// By default, these methods return all registers in the class.
70 virtual iterator allocation_order_begin(MachineFunction &MF) const {
73 virtual iterator allocation_order_end(MachineFunction &MF) const {
79 /// getSize - Return the size of the register in bytes, which is also the size
80 /// of a stack slot allocated to hold a spilled copy of this register.
81 unsigned getSize() const { return RegSize; }
83 /// getAlignment - Return the minimum required alignment for a register of
85 unsigned getAlignment() const { return Alignment; }
89 /// MRegisterInfo base class - We assume that the target defines a static array
90 /// of MRegisterDesc objects that represent all of the machine registers that
91 /// the target has. As such, we simply have to track a pointer to this array so
92 /// that we can turn register number into a register descriptor.
96 typedef const TargetRegisterClass * const * regclass_iterator;
98 const MRegisterDesc *Desc; // Pointer to the descriptor array
99 unsigned NumRegs; // Number of entries in the array
101 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
103 const TargetRegisterClass **PhysRegClasses; // Reg class for each register
104 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
106 MRegisterInfo(const MRegisterDesc *D, unsigned NR,
107 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
108 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
109 virtual ~MRegisterInfo();
112 enum { // Define some target independant constants
113 /// NoRegister - This 'hard' register is a 'noop' register for all backends.
114 /// This is used as the destination register for instructions that do not
115 /// produce a value. Some frontends may use this as an operand register to
116 /// mean special things, for example, the Sparc backend uses R0 to mean %g0
117 /// which always PRODUCES the value 0. The X86 backend does not use this
118 /// value as an operand register, except for memory references.
122 /// FirstVirtualRegister - This is the first register number that is
123 /// considered to be a 'virtual' register, which is part of the SSA
124 /// namespace. This must be the same for all targets, which means that each
125 /// target is limited to 1024 registers.
127 FirstVirtualRegister = 1024,
130 const MRegisterDesc &operator[](unsigned RegNo) const {
131 assert(RegNo < NumRegs &&
132 "Attempting to access record for invalid register number!");
136 /// Provide a get method, equivalent to [], but more useful if we have a
137 /// pointer to this object.
139 const MRegisterDesc &get(unsigned RegNo) const { return operator[](RegNo); }
141 /// getRegClass - Return the register class for the specified physical
144 const TargetRegisterClass *getRegClass(unsigned RegNo) const {
145 assert(RegNo < NumRegs && "Register number out of range!");
146 assert(PhysRegClasses[RegNo] && "Register is not in a class!");
147 return PhysRegClasses[RegNo];
150 /// getAliasSet - Return the set of registers aliased by the specified
151 /// register, or a null list of there are none. The list returned is zero
154 const unsigned *getAliasSet(unsigned RegNo) const {
155 return get(RegNo).AliasSet;
158 /// getName - Return the symbolic target specific name for the specified
159 /// physical register.
160 const char *getName(unsigned RegNo) const {
161 return get(RegNo).Name;
164 virtual const unsigned* getCalleeSaveRegs() const = 0;
167 //===--------------------------------------------------------------------===//
168 // Register Class Information
171 /// Register class iterators
172 regclass_iterator regclass_begin() const { return RegClassBegin; }
173 regclass_iterator regclass_end() const { return RegClassEnd; }
175 unsigned getNumRegClasses() const {
176 return regclass_end()-regclass_begin();
178 virtual const TargetRegisterClass* getRegClassForType(const Type* Ty) const=0;
181 //===--------------------------------------------------------------------===//
182 // Interfaces used by the register allocator and stack frame manipulation
183 // passes to move data around between registers, immediates and memory.
186 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
187 MachineBasicBlock::iterator &MBBI,
188 unsigned SrcReg, int FrameIndex,
189 const TargetRegisterClass *RC) const = 0;
191 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
192 MachineBasicBlock::iterator &MBBI,
193 unsigned DestReg, int FrameIndex,
194 const TargetRegisterClass *RC) const = 0;
196 virtual void copyRegToReg(MachineBasicBlock &MBB,
197 MachineBasicBlock::iterator &MBBI,
198 unsigned DestReg, unsigned SrcReg,
199 const TargetRegisterClass *RC) const = 0;
202 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
203 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
204 /// targets use pseudo instructions in order to abstract away the difference
205 /// between operating with a frame pointer and operating without, through the
206 /// use of these two instructions.
208 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
209 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
212 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
213 /// code insertion to eliminate call frame setup and destroy pseudo
214 /// instructions (but only if the Target is using them). It is responsible
215 /// for eliminating these instructions, replacing them with concrete
216 /// instructions. This method need only be implemented if using call frame
217 /// setup/destroy pseudo instructions.
219 virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
220 MachineBasicBlock &MBB,
221 MachineBasicBlock::iterator &I) const {
222 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
223 "eliminateCallFramePseudoInstr must be implemented if using"
224 " call frame setup/destroy pseudo instructions!");
225 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
228 /// processFunctionBeforeFrameFinalized - This method is called immediately
229 /// before the specified functions frame layout (MF.getFrameInfo()) is
230 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
231 /// replaced with direct constants. This method is optional.
233 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
235 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
236 /// frame indices from instructions which may use them. The instruction
237 /// referenced by the iterator contains an MO_FrameIndex operand which must be
238 /// eliminated by this method. This method may modify or replace the
239 /// specified instruction, as long as it keeps the iterator pointing the the
240 /// finished product.
242 virtual void eliminateFrameIndex(MachineFunction &MF,
243 MachineBasicBlock::iterator &II) const = 0;
245 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
247 virtual void emitPrologue(MachineFunction &MF) const = 0;
248 virtual void emitEpilogue(MachineFunction &MF,
249 MachineBasicBlock &MBB) const = 0;