1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class MachineFunction;
29 class MachineLocation;
31 class TargetRegisterClass;
33 /// TargetRegisterDesc - This record contains all of the information known about
34 /// a particular register. The AliasSet field (if not null) contains a pointer
35 /// to a Zero terminated array of registers that this register aliases. This is
36 /// needed for architectures like X86 which have AL alias AX alias EAX.
37 /// Registers that this does not apply to simply should set this to null.
39 struct TargetRegisterDesc {
40 const char *Name; // Assembly language name for the register
41 const unsigned *AliasSet; // Register Alias Set, described above
44 class TargetRegisterClass {
46 typedef const unsigned* iterator;
47 typedef const unsigned* const_iterator;
49 typedef const MVT::ValueType* vt_iterator;
51 const vt_iterator VTs;
52 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
53 const iterator RegsBegin, RegsEnd;
55 TargetRegisterClass(const MVT::ValueType *vts, unsigned RS, unsigned Al,
56 iterator RB, iterator RE)
57 : VTs(vts), RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
58 virtual ~TargetRegisterClass() {} // Allow subclasses
60 // begin/end - Return all of the registers in this class.
61 iterator begin() const { return RegsBegin; }
62 iterator end() const { return RegsEnd; }
64 // getNumRegs - Return the number of registers in this class
65 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
67 // getRegister - Return the specified register in the class
68 unsigned getRegister(unsigned i) const {
69 assert(i < getNumRegs() && "Register number out of range!");
73 /// contains - Return true if the specified register is included in this
75 bool contains(unsigned Reg) const {
76 for (iterator I = begin(), E = end(); I != E; ++I)
77 if (*I == Reg) return true;
81 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
83 bool hasType(MVT::ValueType vt) const {
84 for(int i = 0; VTs[i] != MVT::Other; ++i)
90 /// vt_begin - Loop over all of the value types that can be represented by
91 /// values in this register class.
92 vt_iterator vt_begin() const {
96 /// vt_begin - Loop over all of the value types that can be represented by
97 /// values in this register class.
98 vt_iterator vt_end() const {
100 while (*I != MVT::Other) ++I;
105 /// allocation_order_begin/end - These methods define a range of registers
106 /// which specify the registers in this class that are valid to register
107 /// allocate, and the preferred order to allocate them in. For example,
108 /// callee saved registers should be at the end of the list, because it is
109 /// cheaper to allocate caller saved registers.
111 /// These methods take a MachineFunction argument, which can be used to tune
112 /// the allocatable registers based on the characteristics of the function.
113 /// One simple example is that the frame pointer register can be used if
114 /// frame-pointer-elimination is performed.
116 /// By default, these methods return all registers in the class.
118 virtual iterator allocation_order_begin(MachineFunction &MF) const {
121 virtual iterator allocation_order_end(MachineFunction &MF) const {
127 /// getSize - Return the size of the register in bytes, which is also the size
128 /// of a stack slot allocated to hold a spilled copy of this register.
129 unsigned getSize() const { return RegSize; }
131 /// getAlignment - Return the minimum required alignment for a register of
133 unsigned getAlignment() const { return Alignment; }
137 /// MRegisterInfo base class - We assume that the target defines a static array
138 /// of TargetRegisterDesc objects that represent all of the machine registers
139 /// that the target has. As such, we simply have to track a pointer to this
140 /// array so that we can turn register number into a register descriptor.
142 class MRegisterInfo {
144 typedef const TargetRegisterClass * const * regclass_iterator;
146 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
147 unsigned NumRegs; // Number of entries in the array
149 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
151 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
153 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
154 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
155 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
156 virtual ~MRegisterInfo();
159 enum { // Define some target independent constants
160 /// NoRegister - This 'hard' register is a 'noop' register for all backends.
161 /// This is used as the destination register for instructions that do not
162 /// produce a value. Some frontends may use this as an operand register to
163 /// mean special things, for example, the Sparc backend uses R0 to mean %g0
164 /// which always PRODUCES the value 0. The X86 backend does not use this
165 /// value as an operand register, except for memory references.
169 /// FirstVirtualRegister - This is the first register number that is
170 /// considered to be a 'virtual' register, which is part of the SSA
171 /// namespace. This must be the same for all targets, which means that each
172 /// target is limited to 1024 registers.
174 FirstVirtualRegister = 1024
177 /// isPhysicalRegister - Return true if the specified register number is in
178 /// the physical register namespace.
179 static bool isPhysicalRegister(unsigned Reg) {
180 assert(Reg && "this is not a register!");
181 return Reg < FirstVirtualRegister;
184 /// isVirtualRegister - Return true if the specified register number is in
185 /// the virtual register namespace.
186 static bool isVirtualRegister(unsigned Reg) {
187 assert(Reg && "this is not a register!");
188 return Reg >= FirstVirtualRegister;
191 /// getAllocatableSet - Returns a bitset indexed by register number
192 /// indicating if a register is allocatable or not.
193 std::vector<bool> getAllocatableSet(MachineFunction &MF) const;
195 const TargetRegisterDesc &operator[](unsigned RegNo) const {
196 assert(RegNo < NumRegs &&
197 "Attempting to access record for invalid register number!");
201 /// Provide a get method, equivalent to [], but more useful if we have a
202 /// pointer to this object.
204 const TargetRegisterDesc &get(unsigned RegNo) const {
205 return operator[](RegNo);
208 /// getAliasSet - Return the set of registers aliased by the specified
209 /// register, or a null list of there are none. The list returned is zero
212 const unsigned *getAliasSet(unsigned RegNo) const {
213 return get(RegNo).AliasSet;
216 /// getName - Return the symbolic target specific name for the specified
217 /// physical register.
218 const char *getName(unsigned RegNo) const {
219 return get(RegNo).Name;
222 /// getNumRegs - Return the number of registers this target has
223 /// (useful for sizing arrays holding per register information)
224 unsigned getNumRegs() const {
228 /// areAliases - Returns true if the two registers alias each other,
230 bool areAliases(unsigned regA, unsigned regB) const {
231 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
232 if (*Alias == regB) return true;
236 /// getCalleeSaveRegs - Return a null-terminated list of all of the
237 /// callee-save registers on this target.
238 virtual const unsigned* getCalleeSaveRegs() const = 0;
240 /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
241 /// register classes to spill each callee-saved register with. The order and
242 /// length of this list match the getCalleeSaveRegs() list.
243 virtual const TargetRegisterClass* const *getCalleeSaveRegClasses() const = 0;
245 //===--------------------------------------------------------------------===//
246 // Register Class Information
249 /// Register class iterators
251 regclass_iterator regclass_begin() const { return RegClassBegin; }
252 regclass_iterator regclass_end() const { return RegClassEnd; }
254 unsigned getNumRegClasses() const {
255 return regclass_end()-regclass_begin();
258 //===--------------------------------------------------------------------===//
259 // Interfaces used by the register allocator and stack frame
260 // manipulation passes to move data around between registers,
261 // immediates and memory. The return value is the number of
262 // instructions added to (negative if removed from) the basic block.
265 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
266 MachineBasicBlock::iterator MI,
267 unsigned SrcReg, int FrameIndex,
268 const TargetRegisterClass *RC) const = 0;
270 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
271 MachineBasicBlock::iterator MI,
272 unsigned DestReg, int FrameIndex,
273 const TargetRegisterClass *RC) const = 0;
275 virtual void copyRegToReg(MachineBasicBlock &MBB,
276 MachineBasicBlock::iterator MI,
277 unsigned DestReg, unsigned SrcReg,
278 const TargetRegisterClass *RC) const = 0;
280 /// foldMemoryOperand - Attempt to fold a load or store of the
281 /// specified stack slot into the specified machine instruction for
282 /// the specified operand. If this is possible, a new instruction
283 /// is returned with the specified operand folded, otherwise NULL is
284 /// returned. The client is responsible for removing the old
285 /// instruction and adding the new one in the instruction stream
286 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
288 int FrameIndex) const {
292 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
293 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
294 /// targets use pseudo instructions in order to abstract away the difference
295 /// between operating with a frame pointer and operating without, through the
296 /// use of these two instructions.
298 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
299 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
302 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
303 /// code insertion to eliminate call frame setup and destroy pseudo
304 /// instructions (but only if the Target is using them). It is responsible
305 /// for eliminating these instructions, replacing them with concrete
306 /// instructions. This method need only be implemented if using call frame
307 /// setup/destroy pseudo instructions.
310 eliminateCallFramePseudoInstr(MachineFunction &MF,
311 MachineBasicBlock &MBB,
312 MachineBasicBlock::iterator MI) const {
313 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
314 "eliminateCallFramePseudoInstr must be implemented if using"
315 " call frame setup/destroy pseudo instructions!");
316 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
319 /// processFunctionBeforeFrameFinalized - This method is called immediately
320 /// before the specified functions frame layout (MF.getFrameInfo()) is
321 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
322 /// replaced with direct constants. This method is optional. The return value
323 /// is the number of instructions added to (negative if removed from) the
326 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
329 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
330 /// frame indices from instructions which may use them. The instruction
331 /// referenced by the iterator contains an MO_FrameIndex operand which must be
332 /// eliminated by this method. This method may modify or replace the
333 /// specified instruction, as long as it keeps the iterator pointing the the
334 /// finished product. The return value is the number of instructions
335 /// added to (negative if removed from) the basic block.
337 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0;
339 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
340 /// the function. The return value is the number of instructions
341 /// added to (negative if removed from) the basic block (entry for prologue).
343 virtual void emitPrologue(MachineFunction &MF) const = 0;
344 virtual void emitEpilogue(MachineFunction &MF,
345 MachineBasicBlock &MBB) const = 0;
347 //===--------------------------------------------------------------------===//
348 /// Debug information queries.
350 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
351 /// number. Returns -1 if there is no equivalent value.
352 virtual int getDwarfRegNum(unsigned RegNum) const = 0;
354 /// getFrameRegister - This method should return the register used as a base
355 /// for values allocated in the current stack frame.
356 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
358 /// getRARegister - This method should return the register where the return
359 /// address can be found.
360 virtual unsigned getRARegister() const = 0;
362 /// getStackDirection - This method should return the factor by which stacks
363 /// grow. The tyical value is -4 which is the grows negatively in 4 byte
365 virtual int getStackDirection() const;
367 /// getLocation - This method should return the actual location of a frame
368 /// variable given the frame index. The location is returned in ML.
369 /// Subclasses should override this method for special handling of frame
370 /// variables and call MRegisterInfo::getLocation for the default action.
371 virtual void getLocation(MachineFunction &MF, unsigned Index,
372 MachineLocation &ML) const;
374 /// getInitialFrameState - Returns a list of machine moves that are assumed
375 /// on entry to all functions. Note that LabelID is ignored (assumed to be
376 /// the beginning of the function.)
377 virtual void getInitialFrameState(std::vector<MachineMove *> &Moves) const;
380 // This is useful when building DenseMaps keyed on virtual registers
381 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
382 unsigned operator()(unsigned Reg) const {
383 return Reg - MRegisterInfo::FirstVirtualRegister;
387 } // End llvm namespace