1 //===- Target/MRegisterInfo.h - Target Register Information -------*-C++-*-===//
3 // This file describes an abstract interface used to get information about a
4 // target machines register file. This information is used for a variety of
5 // purposed, especially register allocation.
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_TARGET_MREGISTERINFO_H
10 #define LLVM_TARGET_MREGISTERINFO_H
12 #include "llvm/CodeGen/MachineBasicBlock.h"
16 class MachineFunction;
18 /// MRegisterDesc - This record contains all of the information known about a
19 /// particular register.
21 struct MRegisterDesc {
22 const char *Name; // Assembly language name for the register
23 unsigned Flags; // Flags identifying register properties (defined below)
24 unsigned TSFlags; // Target Specific Flags
27 /// MRF namespace - This namespace contains flags that pertain to machine
30 namespace MRF { // MRF = Machine Register Flags
32 INT8 = 1 << 0, // This is an 8 bit integer register
33 INT16 = 1 << 1, // This is a 16 bit integer register
34 INT32 = 1 << 2, // This is a 32 bit integer register
35 INT64 = 1 << 3, // This is a 64 bit integer register
36 INT128 = 1 << 4, // This is a 128 bit integer register
38 FP32 = 1 << 5, // This is a 32 bit floating point register
39 FP64 = 1 << 6, // This is a 64 bit floating point register
40 FP80 = 1 << 7, // This is a 80 bit floating point register
41 FP128 = 1 << 8, // This is a 128 bit floating point register
45 class TargetRegisterClass {
47 typedef const unsigned* iterator;
48 typedef const unsigned* const_iterator;
51 const unsigned RegSize; // Size of register in bytes
52 const iterator RegsBegin, RegsEnd;
54 TargetRegisterClass(unsigned RS, iterator RB, iterator RE)
55 : RegSize(RS), RegsBegin(RB), RegsEnd(RE) {}
56 virtual ~TargetRegisterClass() {} // Allow subclasses
58 iterator begin() const { return RegsBegin; }
59 iterator end() const { return RegsEnd; }
61 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
62 unsigned getRegister(unsigned i) const {
63 assert(i < getNumRegs() && "Register number out of range!");
67 unsigned getDataSize() const { return RegSize; }
69 //void getAliases(void);
73 /// MRegisterInfo base class - We assume that the target defines a static array
74 /// of MRegisterDesc objects that represent all of the machine registers that
75 /// the target has. As such, we simply have to track a pointer to this array so
76 /// that we can turn register number into a register descriptor.
79 const MRegisterDesc *Desc; // Pointer to the descriptor array
80 unsigned NumRegs; // Number of entries in the array
82 MRegisterInfo(const MRegisterDesc *D, unsigned NR) : Desc(D), NumRegs(NR) {}
85 enum { // Define some target independant constants
86 /// NoRegister - This 'hard' register is a 'noop' register for all backends.
87 /// This is used as the destination register for instructions that do not
88 /// produce a value. Some frontends may use this as an operand register to
89 /// mean special things, for example, the Sparc backend uses R0 to mean %g0
90 /// which always PRODUCES the value 0. The X86 backend does not use this
91 /// value as an operand register.
95 /// FirstVirtualRegister - This is the first register number that is
96 /// considered to be a 'virtual' register, which is part of the SSA
97 /// namespace. This must be the same for all targets, which means that each
98 /// target is limited to 1024 registers.
100 FirstVirtualRegister = 1024,
103 const MRegisterDesc &operator[](unsigned RegNo) const {
104 assert(RegNo < NumRegs &&
105 "Attempting to access record for invalid register number!");
109 /// Provide a get method, equivalent to [], but more useful if we have a
110 /// pointer to this object.
112 const MRegisterDesc &get(unsigned RegNo) const { return operator[](RegNo); }
115 virtual MachineBasicBlock::iterator
116 storeReg2RegOffset(MachineBasicBlock &MBB,
117 MachineBasicBlock::iterator MBBI,
118 unsigned SrcReg, unsigned DestReg,
119 unsigned ImmOffset, unsigned dataSize) const = 0;
121 virtual MachineBasicBlock::iterator
122 loadRegOffset2Reg(MachineBasicBlock &MBB,
123 MachineBasicBlock::iterator MBBI,
124 unsigned DestReg, unsigned SrcReg,
125 unsigned ImmOffset, unsigned dataSize) const = 0;
127 virtual MachineBasicBlock::iterator
128 moveReg2Reg(MachineBasicBlock &MBB,
129 MachineBasicBlock::iterator MBBI,
130 unsigned DestReg, unsigned SrcReg, unsigned dataSize) const = 0;
132 virtual MachineBasicBlock::iterator
133 moveImm2Reg(MachineBasicBlock &MBB,
134 MachineBasicBlock::iterator MBBI,
135 unsigned DestReg, unsigned Imm, unsigned dataSize) const = 0;
138 emitPrologue(MachineFunction &MF, unsigned numBytes) const = 0;
141 emitEpilogue(MachineBasicBlock &MBB, unsigned numBytes) const = 0;
143 virtual const unsigned* getCalleeSaveRegs() const = 0;
144 virtual const unsigned* getCallerSaveRegs() const = 0;
146 virtual unsigned getFramePointer() const = 0;
147 virtual unsigned getStackPointer() const = 0;
149 /// Register class iterators
150 typedef const TargetRegisterClass * const * const_iterator;
152 virtual const_iterator regclass_begin() const = 0;
153 virtual const_iterator regclass_end() const = 0;
155 virtual unsigned getNumRegClasses() const = 0;
156 virtual const TargetRegisterClass* getRegClassForType(const Type* Ty) const=0;