1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class CalleeSavedInfo;
28 class MachineFunction;
30 class MachineLocation;
33 class TargetRegisterClass;
36 /// TargetRegisterDesc - This record contains all of the information known about
37 /// a particular register. The AliasSet field (if not null) contains a pointer
38 /// to a Zero terminated array of registers that this register aliases. This is
39 /// needed for architectures like X86 which have AL alias AX alias EAX.
40 /// Registers that this does not apply to simply should set this to null.
41 /// The SubRegs field is a zero terminated array of registers that are
42 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
43 /// The ImmsubRegs field is a subset of SubRegs. It includes only the immediate
44 /// sub-registers. e.g. EAX has only one immediate sub-register of AX, not AH,
45 /// AL which are immediate sub-registers of AX. The SuperRegs field is a zero
46 /// terminated array of registers that are super-registers of the specific
47 /// register, e.g. RAX, EAX, are super-registers of AX.
49 struct TargetRegisterDesc {
50 const char *Name; // Assembly language name for the register
51 const unsigned *AliasSet; // Register Alias Set, described above
52 const unsigned *SubRegs; // Sub-register set, described above
53 const unsigned *ImmSubRegs; // Immediate sub-register set, described above
54 const unsigned *SuperRegs; // Super-register set, described above
57 class TargetRegisterClass {
59 typedef const unsigned* iterator;
60 typedef const unsigned* const_iterator;
62 typedef const MVT::ValueType* vt_iterator;
63 typedef const TargetRegisterClass* const * sc_iterator;
67 const vt_iterator VTs;
68 const sc_iterator SubClasses;
69 const sc_iterator SuperClasses;
70 const sc_iterator SubRegClasses;
71 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
72 const iterator RegsBegin, RegsEnd;
74 TargetRegisterClass(unsigned id,
75 const MVT::ValueType *vts,
76 const TargetRegisterClass * const *subcs,
77 const TargetRegisterClass * const *supcs,
78 const TargetRegisterClass * const *subregcs,
79 unsigned RS, unsigned Al, iterator RB, iterator RE)
80 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
81 SubRegClasses(subregcs),
82 RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
83 virtual ~TargetRegisterClass() {} // Allow subclasses
85 /// getID() - Return the register class ID number.
87 unsigned getID() const { return ID; }
89 /// begin/end - Return all of the registers in this class.
91 iterator begin() const { return RegsBegin; }
92 iterator end() const { return RegsEnd; }
94 /// getNumRegs - Return the number of registers in this class.
96 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
98 /// getRegister - Return the specified register in the class.
100 unsigned getRegister(unsigned i) const {
101 assert(i < getNumRegs() && "Register number out of range!");
105 /// contains - Return true if the specified register is included in this
107 bool contains(unsigned Reg) const {
108 for (iterator I = begin(), E = end(); I != E; ++I)
109 if (*I == Reg) return true;
113 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
115 bool hasType(MVT::ValueType vt) const {
116 for(int i = 0; VTs[i] != MVT::Other; ++i)
122 /// vt_begin / vt_end - Loop over all of the value types that can be
123 /// represented by values in this register class.
124 vt_iterator vt_begin() const {
128 vt_iterator vt_end() const {
130 while (*I != MVT::Other) ++I;
134 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
135 /// sub-register class of this TargetRegisterClass.
136 bool hasSubRegClass(const TargetRegisterClass *cs) const {
137 for (int i = 0; SubClasses[i] != NULL; ++i)
138 if (SubClasses[i] == cs)
143 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
144 /// this register class.
145 sc_iterator subclasses_begin() const {
149 sc_iterator subclasses_end() const {
150 sc_iterator I = SubClasses;
151 while (*I != NULL) ++I;
155 /// hasSuperRegClass - return true if the specified TargetRegisterClass is a
156 /// super-register class of this TargetRegisterClass.
157 bool hasSuperRegClass(const TargetRegisterClass *cs) const {
158 for (int i = 0; SuperClasses[i] != NULL; ++i)
159 if (SuperClasses[i] == cs)
164 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
165 /// of this register class.
166 sc_iterator superclasses_begin() const {
170 sc_iterator superclasses_end() const {
171 sc_iterator I = SuperClasses;
172 while (*I != NULL) ++I;
176 /// hasSubRegForClass - return true if the specified TargetRegisterClass is a
177 /// class of a sub-register class for this TargetRegisterClass.
178 bool hasSubRegForClass(const TargetRegisterClass *cs) const {
179 for (int i = 0; SubRegClasses[i] != NULL; ++i)
180 if (SubRegClasses[i] == cs)
185 /// hasClassForSubReg - return true if the specified TargetRegisterClass is a
186 /// class of a sub-register class for this TargetRegisterClass.
187 bool hasClassForSubReg(unsigned SubReg) const {
189 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
195 /// getClassForSubReg - return theTargetRegisterClass for the sub-register
196 /// at idx for this TargetRegisterClass.
197 sc_iterator getClassForSubReg(unsigned SubReg) const {
199 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
201 return &SubRegClasses[i];
205 /// subregclasses_begin / subregclasses_end - Loop over all of
206 /// the subregister classes of this register class.
207 sc_iterator subregclasses_begin() const {
208 return SubRegClasses;
211 sc_iterator subregclasses_end() const {
212 sc_iterator I = SubRegClasses;
213 while (*I != NULL) ++I;
217 /// allocation_order_begin/end - These methods define a range of registers
218 /// which specify the registers in this class that are valid to register
219 /// allocate, and the preferred order to allocate them in. For example,
220 /// callee saved registers should be at the end of the list, because it is
221 /// cheaper to allocate caller saved registers.
223 /// These methods take a MachineFunction argument, which can be used to tune
224 /// the allocatable registers based on the characteristics of the function.
225 /// One simple example is that the frame pointer register can be used if
226 /// frame-pointer-elimination is performed.
228 /// By default, these methods return all registers in the class.
230 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
233 virtual iterator allocation_order_end(const MachineFunction &MF) const {
239 /// getSize - Return the size of the register in bytes, which is also the size
240 /// of a stack slot allocated to hold a spilled copy of this register.
241 unsigned getSize() const { return RegSize; }
243 /// getAlignment - Return the minimum required alignment for a register of
245 unsigned getAlignment() const { return Alignment; }
249 /// MRegisterInfo base class - We assume that the target defines a static array
250 /// of TargetRegisterDesc objects that represent all of the machine registers
251 /// that the target has. As such, we simply have to track a pointer to this
252 /// array so that we can turn register number into a register descriptor.
254 class MRegisterInfo {
256 typedef const TargetRegisterClass * const * regclass_iterator;
258 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
259 unsigned NumRegs; // Number of entries in the array
261 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
263 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
265 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
266 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
267 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
268 virtual ~MRegisterInfo();
271 enum { // Define some target independent constants
272 /// NoRegister - This physical register is not a real target register. It
273 /// is useful as a sentinal.
276 /// FirstVirtualRegister - This is the first register number that is
277 /// considered to be a 'virtual' register, which is part of the SSA
278 /// namespace. This must be the same for all targets, which means that each
279 /// target is limited to 1024 registers.
280 FirstVirtualRegister = 1024
283 /// isPhysicalRegister - Return true if the specified register number is in
284 /// the physical register namespace.
285 static bool isPhysicalRegister(unsigned Reg) {
286 assert(Reg && "this is not a register!");
287 return Reg < FirstVirtualRegister;
290 /// isVirtualRegister - Return true if the specified register number is in
291 /// the virtual register namespace.
292 static bool isVirtualRegister(unsigned Reg) {
293 assert(Reg && "this is not a register!");
294 return Reg >= FirstVirtualRegister;
297 /// getAllocatableSet - Returns a bitset indexed by register number
298 /// indicating if a register is allocatable or not. If a register class is
299 /// specified, returns the subset for the class.
300 BitVector getAllocatableSet(MachineFunction &MF,
301 const TargetRegisterClass *RC = NULL) const;
303 const TargetRegisterDesc &operator[](unsigned RegNo) const {
304 assert(RegNo < NumRegs &&
305 "Attempting to access record for invalid register number!");
309 /// Provide a get method, equivalent to [], but more useful if we have a
310 /// pointer to this object.
312 const TargetRegisterDesc &get(unsigned RegNo) const {
313 return operator[](RegNo);
316 /// getAliasSet - Return the set of registers aliased by the specified
317 /// register, or a null list of there are none. The list returned is zero
320 const unsigned *getAliasSet(unsigned RegNo) const {
321 return get(RegNo).AliasSet;
324 /// getSubRegisters - Return the set of registers that are sub-registers of
325 /// the specified register, or a null list of there are none. The list
326 /// returned is zero terminated.
328 const unsigned *getSubRegisters(unsigned RegNo) const {
329 return get(RegNo).SubRegs;
332 /// getImmediateSubRegisters - Return the set of registers that are immediate
333 /// sub-registers of the specified register, or a null list of there are none.
334 /// The list returned is zero terminated.
336 const unsigned *getImmediateSubRegisters(unsigned RegNo) const {
337 return get(RegNo).ImmSubRegs;
340 /// getSuperRegisters - Return the set of registers that are super-registers
341 /// of the specified register, or a null list of there are none. The list
342 /// returned is zero terminated.
344 const unsigned *getSuperRegisters(unsigned RegNo) const {
345 return get(RegNo).SuperRegs;
348 /// getName - Return the symbolic target specific name for the specified
349 /// physical register.
350 const char *getName(unsigned RegNo) const {
351 return get(RegNo).Name;
354 /// getNumRegs - Return the number of registers this target has
355 /// (useful for sizing arrays holding per register information)
356 unsigned getNumRegs() const {
360 /// areAliases - Returns true if the two registers alias each other,
362 bool areAliases(unsigned regA, unsigned regB) const {
363 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
364 if (*Alias == regB) return true;
368 /// regsOverlap - Returns true if the two registers are equal or alias
369 /// each other. The registers may be virtual register.
370 bool regsOverlap(unsigned regA, unsigned regB) const {
374 if (isVirtualRegister(regA) || isVirtualRegister(regB))
376 return areAliases(regA, regB);
379 /// isSubRegister - Returns true if regB is a sub-register of regA.
381 bool isSubRegister(unsigned regA, unsigned regB) const {
382 for (const unsigned *SR = getSubRegisters(regA); *SR; ++SR)
383 if (*SR == regB) return true;
387 /// isSuperRegister - Returns true if regB is a super-register of regA.
389 bool isSuperRegister(unsigned regA, unsigned regB) const {
390 for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR)
391 if (*SR == regB) return true;
395 /// getCalleeSavedRegs - Return a null-terminated list of all of the
396 /// callee saved registers on this target. The register should be in the
397 /// order of desired callee-save stack frame offset. The first register is
398 /// closed to the incoming stack pointer if stack grows down, and vice versa.
399 virtual const unsigned* getCalleeSavedRegs() const = 0;
401 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
402 /// register classes to spill each callee saved register with. The order and
403 /// length of this list match the getCalleeSaveRegs() list.
404 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const =0;
406 /// getReservedRegs - Returns a bitset indexed by physical register number
407 /// indicating if a register is a special register that has particular uses and
408 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
409 /// register scavenger to determine what registers are free.
410 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
412 /// getSubReg - Returns the physical register number of sub-register "Index"
413 /// for physical register RegNo.
414 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
416 //===--------------------------------------------------------------------===//
417 // Register Class Information
420 /// Register class iterators
422 regclass_iterator regclass_begin() const { return RegClassBegin; }
423 regclass_iterator regclass_end() const { return RegClassEnd; }
425 unsigned getNumRegClasses() const {
426 return regclass_end()-regclass_begin();
429 /// getRegClass - Returns the register class associated with the enumeration
430 /// value. See class TargetOperandInfo.
431 const TargetRegisterClass *getRegClass(unsigned i) const {
432 assert(i <= getNumRegClasses() && "Register Class ID out of range");
433 return i ? RegClassBegin[i - 1] : NULL;
436 //===--------------------------------------------------------------------===//
437 // Interfaces used by the register allocator and stack frame
438 // manipulation passes to move data around between registers,
439 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
442 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved
443 /// registers and returns true if it isn't possible / profitable to do so by
444 /// issuing a series of store instructions via storeRegToStackSlot(). Returns
446 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
447 MachineBasicBlock::iterator MI,
448 const std::vector<CalleeSavedInfo> &CSI) const {
452 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
453 /// saved registers and returns true if it isn't possible / profitable to do
454 /// so by issuing a series of load instructions via loadRegToStackSlot().
455 /// Returns false otherwise.
456 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
457 MachineBasicBlock::iterator MI,
458 const std::vector<CalleeSavedInfo> &CSI) const {
462 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
463 MachineBasicBlock::iterator MI,
464 unsigned SrcReg, int FrameIndex,
465 const TargetRegisterClass *RC) const = 0;
467 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
468 MachineBasicBlock::iterator MI,
469 unsigned DestReg, int FrameIndex,
470 const TargetRegisterClass *RC) const = 0;
472 virtual void copyRegToReg(MachineBasicBlock &MBB,
473 MachineBasicBlock::iterator MI,
474 unsigned DestReg, unsigned SrcReg,
475 const TargetRegisterClass *RC) const = 0;
477 /// reMaterialize - Re-issue the specified 'original' instruction at the
478 /// specific location targeting a new destination register.
479 virtual void reMaterialize(MachineBasicBlock &MBB,
480 MachineBasicBlock::iterator MI,
482 const MachineInstr *Orig) const = 0;
484 /// foldMemoryOperand - Attempt to fold a load or store of the
485 /// specified stack slot into the specified machine instruction for
486 /// the specified operand. If this is possible, a new instruction
487 /// is returned with the specified operand folded, otherwise NULL is
488 /// returned. The client is responsible for removing the old
489 /// instruction and adding the new one in the instruction stream
490 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
492 int FrameIndex) const {
496 /// targetHandlesStackFrameRounding - Returns true if the target is responsible
497 /// for rounding up the stack frame (probably at emitPrologue time).
498 virtual bool targetHandlesStackFrameRounding() const {
502 /// requiresRegisterScavenging - returns true if the target requires (and
503 /// can make use of) the register scavenger.
504 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
508 /// hasFP - Return true if the specified function should have a dedicated frame
509 /// pointer register. For most targets this is true only if the function has
510 /// variable sized allocas or if frame pointer elimination is disabled.
511 virtual bool hasFP(const MachineFunction &MF) const = 0;
513 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
514 // not required, we reserve argument space for call sites in the function
515 // immediately on entry to the current function. This eliminates the need for
516 // add/sub sp brackets around call sites. Returns true if the call frame is
517 // included as part of the stack frame.
518 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
522 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
523 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
524 /// targets use pseudo instructions in order to abstract away the difference
525 /// between operating with a frame pointer and operating without, through the
526 /// use of these two instructions.
528 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
529 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
532 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
533 /// code insertion to eliminate call frame setup and destroy pseudo
534 /// instructions (but only if the Target is using them). It is responsible
535 /// for eliminating these instructions, replacing them with concrete
536 /// instructions. This method need only be implemented if using call frame
537 /// setup/destroy pseudo instructions.
540 eliminateCallFramePseudoInstr(MachineFunction &MF,
541 MachineBasicBlock &MBB,
542 MachineBasicBlock::iterator MI) const {
543 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
544 "eliminateCallFramePseudoInstr must be implemented if using"
545 " call frame setup/destroy pseudo instructions!");
546 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
549 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
550 /// before PrologEpilogInserter scans the physical registers used to determine
551 /// what callee saved registers should be spilled. This method is optional.
552 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
553 RegScavenger *RS = NULL) const {
557 /// processFunctionBeforeFrameFinalized - This method is called immediately
558 /// before the specified functions frame layout (MF.getFrameInfo()) is
559 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
560 /// replaced with direct constants. This method is optional.
562 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
565 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
566 /// frame indices from instructions which may use them. The instruction
567 /// referenced by the iterator contains an MO_FrameIndex operand which must be
568 /// eliminated by this method. This method may modify or replace the
569 /// specified instruction, as long as it keeps the iterator pointing the the
570 /// finished product. SPAdj is the SP adjustment due to call frame setup
571 /// instruction. The return value is the number of instructions added to
572 /// (negative if removed from) the basic block.
574 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
575 int SPAdj, RegScavenger *RS=NULL) const = 0;
577 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
578 /// the function. The return value is the number of instructions
579 /// added to (negative if removed from) the basic block (entry for prologue).
581 virtual void emitPrologue(MachineFunction &MF) const = 0;
582 virtual void emitEpilogue(MachineFunction &MF,
583 MachineBasicBlock &MBB) const = 0;
585 //===--------------------------------------------------------------------===//
586 /// Debug information queries.
588 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
589 /// number. Returns -1 if there is no equivalent value.
590 virtual int getDwarfRegNum(unsigned RegNum) const = 0;
592 /// getFrameRegister - This method should return the register used as a base
593 /// for values allocated in the current stack frame.
594 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
596 /// getRARegister - This method should return the register where the return
597 /// address can be found.
598 virtual unsigned getRARegister() const = 0;
600 /// getLocation - This method should return the actual location of a frame
601 /// variable given the frame index. The location is returned in ML.
602 /// Subclasses should override this method for special handling of frame
603 /// variables and call MRegisterInfo::getLocation for the default action.
604 virtual void getLocation(MachineFunction &MF, unsigned Index,
605 MachineLocation &ML) const;
607 /// getInitialFrameState - Returns a list of machine moves that are assumed
608 /// on entry to all functions. Note that LabelID is ignored (assumed to be
609 /// the beginning of the function.)
610 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
613 // This is useful when building IndexedMaps keyed on virtual registers
614 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
615 unsigned operator()(unsigned Reg) const {
616 return Reg - MRegisterInfo::FirstVirtualRegister;
620 } // End llvm namespace