1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class MachineFunction;
29 class TargetRegisterClass;
31 /// TargetRegisterDesc - This record contains all of the information known about
32 /// a particular register. The AliasSet field (if not null) contains a pointer
33 /// to a Zero terminated array of registers that this register aliases. This is
34 /// needed for architectures like X86 which have AL alias AX alias EAX.
35 /// Registers that this does not apply to simply should set this to null.
37 struct TargetRegisterDesc {
38 const char *Name; // Assembly language name for the register
39 const unsigned *AliasSet; // Register Alias Set, described above
42 class TargetRegisterClass {
44 typedef const unsigned* iterator;
45 typedef const unsigned* const_iterator;
47 typedef const MVT::ValueType* vt_iterator;
49 const vt_iterator VTs;
50 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
51 const iterator RegsBegin, RegsEnd;
53 TargetRegisterClass(const MVT::ValueType *vts, unsigned RS, unsigned Al,
54 iterator RB, iterator RE)
55 : VTs(vts), RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
56 virtual ~TargetRegisterClass() {} // Allow subclasses
58 // begin/end - Return all of the registers in this class.
59 iterator begin() const { return RegsBegin; }
60 iterator end() const { return RegsEnd; }
62 // getNumRegs - Return the number of registers in this class
63 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
65 // getRegister - Return the specified register in the class
66 unsigned getRegister(unsigned i) const {
67 assert(i < getNumRegs() && "Register number out of range!");
71 /// contains - Return true if the specified register is included in this
73 bool contains(unsigned Reg) const {
74 for (iterator I = begin(), E = end(); I != E; ++I)
75 if (*I == Reg) return true;
79 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
81 bool hasType(MVT::ValueType vt) const {
82 for(int i = 0; VTs[i] != MVT::Other; ++i)
88 /// vt_begin - Loop over all of the value types that can be represented by
89 /// values in this register class.
90 vt_iterator vt_begin() const {
94 /// vt_begin - Loop over all of the value types that can be represented by
95 /// values in this register class.
96 vt_iterator vt_end() const {
98 while (*I != MVT::Other) ++I;
103 /// allocation_order_begin/end - These methods define a range of registers
104 /// which specify the registers in this class that are valid to register
105 /// allocate, and the preferred order to allocate them in. For example,
106 /// callee saved registers should be at the end of the list, because it is
107 /// cheaper to allocate caller saved registers.
109 /// These methods take a MachineFunction argument, which can be used to tune
110 /// the allocatable registers based on the characteristics of the function.
111 /// One simple example is that the frame pointer register can be used if
112 /// frame-pointer-elimination is performed.
114 /// By default, these methods return all registers in the class.
116 virtual iterator allocation_order_begin(MachineFunction &MF) const {
119 virtual iterator allocation_order_end(MachineFunction &MF) const {
125 /// getSize - Return the size of the register in bytes, which is also the size
126 /// of a stack slot allocated to hold a spilled copy of this register.
127 unsigned getSize() const { return RegSize; }
129 /// getAlignment - Return the minimum required alignment for a register of
131 unsigned getAlignment() const { return Alignment; }
135 /// MRegisterInfo base class - We assume that the target defines a static array
136 /// of TargetRegisterDesc objects that represent all of the machine registers
137 /// that the target has. As such, we simply have to track a pointer to this
138 /// array so that we can turn register number into a register descriptor.
140 class MRegisterInfo {
142 typedef const TargetRegisterClass * const * regclass_iterator;
144 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
145 unsigned NumRegs; // Number of entries in the array
147 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
149 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
151 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
152 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
153 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
154 virtual ~MRegisterInfo();
157 enum { // Define some target independent constants
158 /// NoRegister - This 'hard' register is a 'noop' register for all backends.
159 /// This is used as the destination register for instructions that do not
160 /// produce a value. Some frontends may use this as an operand register to
161 /// mean special things, for example, the Sparc backend uses R0 to mean %g0
162 /// which always PRODUCES the value 0. The X86 backend does not use this
163 /// value as an operand register, except for memory references.
167 /// FirstVirtualRegister - This is the first register number that is
168 /// considered to be a 'virtual' register, which is part of the SSA
169 /// namespace. This must be the same for all targets, which means that each
170 /// target is limited to 1024 registers.
172 FirstVirtualRegister = 1024
175 /// isPhysicalRegister - Return true if the specified register number is in
176 /// the physical register namespace.
177 static bool isPhysicalRegister(unsigned Reg) {
178 assert(Reg && "this is not a register!");
179 return Reg < FirstVirtualRegister;
182 /// isVirtualRegister - Return true if the specified register number is in
183 /// the virtual register namespace.
184 static bool isVirtualRegister(unsigned Reg) {
185 assert(Reg && "this is not a register!");
186 return Reg >= FirstVirtualRegister;
189 /// getAllocatableSet - Returns a bitset indexed by register number
190 /// indicating if a register is allocatable or not.
191 std::vector<bool> getAllocatableSet(MachineFunction &MF) const;
193 const TargetRegisterDesc &operator[](unsigned RegNo) const {
194 assert(RegNo < NumRegs &&
195 "Attempting to access record for invalid register number!");
199 /// Provide a get method, equivalent to [], but more useful if we have a
200 /// pointer to this object.
202 const TargetRegisterDesc &get(unsigned RegNo) const {
203 return operator[](RegNo);
206 /// getAliasSet - Return the set of registers aliased by the specified
207 /// register, or a null list of there are none. The list returned is zero
210 const unsigned *getAliasSet(unsigned RegNo) const {
211 return get(RegNo).AliasSet;
214 /// getName - Return the symbolic target specific name for the specified
215 /// physical register.
216 const char *getName(unsigned RegNo) const {
217 return get(RegNo).Name;
220 /// getNumRegs - Return the number of registers this target has
221 /// (useful for sizing arrays holding per register information)
222 unsigned getNumRegs() const {
226 /// areAliases - Returns true if the two registers alias each other,
228 bool areAliases(unsigned regA, unsigned regB) const {
229 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
230 if (*Alias == regB) return true;
234 /// getCalleeSaveRegs - Return a null-terminated list of all of the
235 /// callee-save registers on this target.
236 virtual const unsigned* getCalleeSaveRegs() const = 0;
238 /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
239 /// register classes to spill each callee-saved register with. The order and
240 /// length of this list match the getCalleeSaveRegs() list.
241 virtual const TargetRegisterClass* const *getCalleeSaveRegClasses() const = 0;
243 //===--------------------------------------------------------------------===//
244 // Register Class Information
247 /// Register class iterators
249 regclass_iterator regclass_begin() const { return RegClassBegin; }
250 regclass_iterator regclass_end() const { return RegClassEnd; }
252 unsigned getNumRegClasses() const {
253 return regclass_end()-regclass_begin();
256 //===--------------------------------------------------------------------===//
257 // Interfaces used by the register allocator and stack frame
258 // manipulation passes to move data around between registers,
259 // immediates and memory. The return value is the number of
260 // instructions added to (negative if removed from) the basic block.
263 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
264 MachineBasicBlock::iterator MI,
265 unsigned SrcReg, int FrameIndex,
266 const TargetRegisterClass *RC) const = 0;
268 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
269 MachineBasicBlock::iterator MI,
270 unsigned DestReg, int FrameIndex,
271 const TargetRegisterClass *RC) const = 0;
273 virtual void copyRegToReg(MachineBasicBlock &MBB,
274 MachineBasicBlock::iterator MI,
275 unsigned DestReg, unsigned SrcReg,
276 const TargetRegisterClass *RC) const = 0;
278 /// foldMemoryOperand - Attempt to fold a load or store of the
279 /// specified stack slot into the specified machine instruction for
280 /// the specified operand. If this is possible, a new instruction
281 /// is returned with the specified operand folded, otherwise NULL is
282 /// returned. The client is responsible for removing the old
283 /// instruction and adding the new one in the instruction stream
284 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
286 int FrameIndex) const {
290 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
291 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
292 /// targets use pseudo instructions in order to abstract away the difference
293 /// between operating with a frame pointer and operating without, through the
294 /// use of these two instructions.
296 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
297 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
300 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
301 /// code insertion to eliminate call frame setup and destroy pseudo
302 /// instructions (but only if the Target is using them). It is responsible
303 /// for eliminating these instructions, replacing them with concrete
304 /// instructions. This method need only be implemented if using call frame
305 /// setup/destroy pseudo instructions.
308 eliminateCallFramePseudoInstr(MachineFunction &MF,
309 MachineBasicBlock &MBB,
310 MachineBasicBlock::iterator MI) const {
311 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
312 "eliminateCallFramePseudoInstr must be implemented if using"
313 " call frame setup/destroy pseudo instructions!");
314 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
317 /// processFunctionBeforeFrameFinalized - This method is called immediately
318 /// before the specified functions frame layout (MF.getFrameInfo()) is
319 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
320 /// replaced with direct constants. This method is optional. The return value
321 /// is the number of instructions added to (negative if removed from) the
324 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
327 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
328 /// frame indices from instructions which may use them. The instruction
329 /// referenced by the iterator contains an MO_FrameIndex operand which must be
330 /// eliminated by this method. This method may modify or replace the
331 /// specified instruction, as long as it keeps the iterator pointing the the
332 /// finished product. The return value is the number of instructions
333 /// added to (negative if removed from) the basic block.
335 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0;
337 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
338 /// the function. The return value is the number of instructions
339 /// added to (negative if removed from) the basic block (entry for prologue).
341 virtual void emitPrologue(MachineFunction &MF) const = 0;
342 virtual void emitEpilogue(MachineFunction &MF,
343 MachineBasicBlock &MBB) const = 0;
346 // This is useful when building DenseMaps keyed on virtual registers
347 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
348 unsigned operator()(unsigned Reg) const {
349 return Reg - MRegisterInfo::FirstVirtualRegister;
353 } // End llvm namespace