1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
25 class MachineFunction;
27 /// MRegisterDesc - This record contains all of the information known about a
28 /// particular register. The AliasSet field (if not null) contains a pointer to
29 /// a Zero terminated array of registers that this register aliases. This is
30 /// needed for architectures like X86 which have AL alias AX alias EAX.
31 /// Registers that this does not apply to simply should set this to null.
33 struct MRegisterDesc {
34 const char *Name; // Assembly language name for the register
35 const unsigned *AliasSet; // Register Alias Set, described above
36 unsigned Flags; // Flags identifying register properties (below)
37 unsigned TSFlags; // Target Specific Flags
40 class TargetRegisterClass {
42 typedef const unsigned* iterator;
43 typedef const unsigned* const_iterator;
46 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
47 const iterator RegsBegin, RegsEnd;
49 TargetRegisterClass(unsigned RS, unsigned Al, iterator RB, iterator RE)
50 : RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
51 virtual ~TargetRegisterClass() {} // Allow subclasses
53 // begin/end - Return all of the registers in this class.
54 iterator begin() const { return RegsBegin; }
55 iterator end() const { return RegsEnd; }
57 // getNumRegs - Return the number of registers in this class
58 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
60 // getRegister - Return the specified register in the class
61 unsigned getRegister(unsigned i) const {
62 assert(i < getNumRegs() && "Register number out of range!");
66 /// allocation_order_begin/end - These methods define a range of registers
67 /// which specify the registers in this class that are valid to register
68 /// allocate, and the preferred order to allocate them in. For example,
69 /// callee saved registers should be at the end of the list, because it is
70 /// cheaper to allocate caller saved registers.
72 /// These methods take a MachineFunction argument, which can be used to tune
73 /// the allocatable registers based on the characteristics of the function.
74 /// One simple example is that the frame pointer register can be used if
75 /// frame-pointer-elimination is performed.
77 /// By default, these methods return all registers in the class.
79 virtual iterator allocation_order_begin(MachineFunction &MF) const {
82 virtual iterator allocation_order_end(MachineFunction &MF) const {
88 /// getSize - Return the size of the register in bytes, which is also the size
89 /// of a stack slot allocated to hold a spilled copy of this register.
90 unsigned getSize() const { return RegSize; }
92 /// getAlignment - Return the minimum required alignment for a register of
94 unsigned getAlignment() const { return Alignment; }
98 /// MRegisterInfo base class - We assume that the target defines a static array
99 /// of MRegisterDesc objects that represent all of the machine registers that
100 /// the target has. As such, we simply have to track a pointer to this array so
101 /// that we can turn register number into a register descriptor.
103 class MRegisterInfo {
105 typedef const TargetRegisterClass * const * regclass_iterator;
107 const MRegisterDesc *Desc; // Pointer to the descriptor array
108 unsigned NumRegs; // Number of entries in the array
110 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
112 const TargetRegisterClass **PhysRegClasses; // Reg class for each register
113 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
115 MRegisterInfo(const MRegisterDesc *D, unsigned NR,
116 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
117 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
118 virtual ~MRegisterInfo();
121 enum { // Define some target independent constants
122 /// NoRegister - This 'hard' register is a 'noop' register for all backends.
123 /// This is used as the destination register for instructions that do not
124 /// produce a value. Some frontends may use this as an operand register to
125 /// mean special things, for example, the Sparc backend uses R0 to mean %g0
126 /// which always PRODUCES the value 0. The X86 backend does not use this
127 /// value as an operand register, except for memory references.
131 /// FirstVirtualRegister - This is the first register number that is
132 /// considered to be a 'virtual' register, which is part of the SSA
133 /// namespace. This must be the same for all targets, which means that each
134 /// target is limited to 1024 registers.
136 FirstVirtualRegister = 1024,
139 /// isPhysicalRegister - Return true if the specified register number is in
140 /// the physical register namespace.
141 static bool isPhysicalRegister(unsigned Reg) {
142 return Reg < FirstVirtualRegister;
145 /// isVirtualRegister - Return true if the specified register number is in
146 /// the virtual register namespace.
147 static bool isVirtualRegister(unsigned Reg) {
148 return Reg >= FirstVirtualRegister;
151 const MRegisterDesc &operator[](unsigned RegNo) const {
152 assert(RegNo < NumRegs &&
153 "Attempting to access record for invalid register number!");
157 /// Provide a get method, equivalent to [], but more useful if we have a
158 /// pointer to this object.
160 const MRegisterDesc &get(unsigned RegNo) const { return operator[](RegNo); }
162 /// getRegClass - Return the register class for the specified physical
165 const TargetRegisterClass *getRegClass(unsigned RegNo) const {
166 assert(RegNo < NumRegs && "Register number out of range!");
167 assert(PhysRegClasses[RegNo] && "Register is not in a class!");
168 return PhysRegClasses[RegNo];
171 /// getAliasSet - Return the set of registers aliased by the specified
172 /// register, or a null list of there are none. The list returned is zero
175 const unsigned *getAliasSet(unsigned RegNo) const {
176 return get(RegNo).AliasSet;
179 /// getName - Return the symbolic target specific name for the specified
180 /// physical register.
181 const char *getName(unsigned RegNo) const {
182 return get(RegNo).Name;
185 virtual const unsigned* getCalleeSaveRegs() const = 0;
188 //===--------------------------------------------------------------------===//
189 // Register Class Information
192 /// Register class iterators
194 regclass_iterator regclass_begin() const { return RegClassBegin; }
195 regclass_iterator regclass_end() const { return RegClassEnd; }
197 unsigned getNumRegClasses() const {
198 return regclass_end()-regclass_begin();
201 //===--------------------------------------------------------------------===//
202 // All basic block modifier functions below return the number of
203 // instructions added to (negative if removed from) the basic block
204 // passed as their first argument.
206 // FIXME: This is only needed because we use a std::vector instead
207 // of an ilist to keep MachineBasicBlock instructions. Inserting an
208 // instruction to a MachineBasicBlock invalidates all iterators to
209 // the basic block. The return value can be used to update an index
210 // to the machine basic block instruction vector and circumvent the
211 // iterator elimination problem but this is really not needed if we
212 // move to a better representation.
215 //===--------------------------------------------------------------------===//
216 // Interfaces used by the register allocator and stack frame
217 // manipulation passes to move data around between registers,
218 // immediates and memory. The return value is the number of
219 // instructions added to (negative if removed from) the basic block.
222 virtual int storeRegToStackSlot(MachineBasicBlock &MBB,
223 MachineBasicBlock::iterator &MBBI,
224 unsigned SrcReg, int FrameIndex,
225 const TargetRegisterClass *RC) const = 0;
227 virtual int loadRegFromStackSlot(MachineBasicBlock &MBB,
228 MachineBasicBlock::iterator &MBBI,
229 unsigned DestReg, int FrameIndex,
230 const TargetRegisterClass *RC) const = 0;
232 virtual int copyRegToReg(MachineBasicBlock &MBB,
233 MachineBasicBlock::iterator &MBBI,
234 unsigned DestReg, unsigned SrcReg,
235 const TargetRegisterClass *RC) const = 0;
238 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
239 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
240 /// targets use pseudo instructions in order to abstract away the difference
241 /// between operating with a frame pointer and operating without, through the
242 /// use of these two instructions.
244 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
245 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
248 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
249 /// code insertion to eliminate call frame setup and destroy pseudo
250 /// instructions (but only if the Target is using them). It is responsible
251 /// for eliminating these instructions, replacing them with concrete
252 /// instructions. This method need only be implemented if using call frame
253 /// setup/destroy pseudo instructions. The return value is the number of
254 /// instructions added to (negative if removed from) the basic block.
256 virtual int eliminateCallFramePseudoInstr(MachineFunction &MF,
257 MachineBasicBlock &MBB,
258 MachineBasicBlock::iterator &I) const {
259 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
260 "eliminateCallFramePseudoInstr must be implemented if using"
261 " call frame setup/destroy pseudo instructions!");
262 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
266 /// processFunctionBeforeFrameFinalized - This method is called immediately
267 /// before the specified functions frame layout (MF.getFrameInfo()) is
268 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
269 /// replaced with direct constants. This method is optional. The return value
270 /// is the number of instructions added to (negative if removed from) the
273 virtual int processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
277 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
278 /// frame indices from instructions which may use them. The instruction
279 /// referenced by the iterator contains an MO_FrameIndex operand which must be
280 /// eliminated by this method. This method may modify or replace the
281 /// specified instruction, as long as it keeps the iterator pointing the the
282 /// finished product. The return value is the number of instructions
283 /// added to (negative if removed from) the basic block.
285 virtual int eliminateFrameIndex(MachineFunction &MF,
286 MachineBasicBlock::iterator &II) const = 0;
288 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
289 /// the function. The return value is the number of instructions
290 /// added to (negative if removed from) the basic block (entry for prologue).
292 virtual int emitPrologue(MachineFunction &MF) const = 0;
293 virtual int emitEpilogue(MachineFunction &MF,
294 MachineBasicBlock &MBB) const = 0;
297 } // End llvm namespace