1 //==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subtarget options of a Target machine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_MC_MCSUBTARGETINFO_H
15 #define LLVM_MC_MCSUBTARGETINFO_H
17 #include "llvm/MC/MCInstrItineraries.h"
18 #include "llvm/MC/SubtargetFeature.h"
25 //===----------------------------------------------------------------------===//
27 /// MCSubtargetInfo - Generic base class for all target subtargets.
29 class MCSubtargetInfo {
30 Triple TargetTriple; // Target triple
31 std::string CPU; // CPU being targeted.
32 ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
33 ArrayRef<SubtargetFeatureKV> ProcDesc; // Processor descriptions
35 // Scheduler machine model
36 const SubtargetInfoKV *ProcSchedModels;
37 const MCWriteProcResEntry *WriteProcResTable;
38 const MCWriteLatencyEntry *WriteLatencyTable;
39 const MCReadAdvanceEntry *ReadAdvanceTable;
40 const MCSchedModel *CPUSchedModel;
42 const InstrStage *Stages; // Instruction itinerary stages
43 const unsigned *OperandCycles; // Itinerary operand cycles
44 const unsigned *ForwardingPaths; // Forwarding paths
45 FeatureBitset FeatureBits; // Feature bits for current CPU + FS
47 MCSubtargetInfo() = delete;
50 MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
51 ArrayRef<SubtargetFeatureKV> PF,
52 ArrayRef<SubtargetFeatureKV> PD,
53 const SubtargetInfoKV *ProcSched,
54 const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
55 const MCReadAdvanceEntry *RA, const InstrStage *IS,
56 const unsigned *OC, const unsigned *FP);
58 /// getTargetTriple - Return the target triple string.
59 const Triple &getTargetTriple() const { return TargetTriple; }
61 /// getCPU - Return the CPU string.
62 StringRef getCPU() const {
66 /// getFeatureBits - Return the feature bits.
68 const FeatureBitset& getFeatureBits() const {
72 /// setFeatureBits - Set the feature bits.
74 void setFeatureBits(const FeatureBitset &FeatureBits_) {
75 FeatureBits = FeatureBits_;
78 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
79 /// feature string). Recompute feature bits and scheduling model.
80 void InitMCProcessorInfo(StringRef CPU, StringRef FS);
82 /// ToggleFeature - Toggle a feature and returns the re-computed feature
83 /// bits. This version does not change the implied bits.
84 FeatureBitset ToggleFeature(uint64_t FB);
86 /// ToggleFeature - Toggle a feature and returns the re-computed feature
87 /// bits. This version does not change the implied bits.
88 FeatureBitset ToggleFeature(const FeatureBitset& FB);
90 /// ToggleFeature - Toggle a set of features and returns the re-computed
91 /// feature bits. This version will also change all implied bits.
92 FeatureBitset ToggleFeature(StringRef FS);
94 /// Apply a feature flag and return the re-computed feature bits, including
95 /// all feature bits implied by the flag.
96 FeatureBitset ApplyFeatureFlag(StringRef FS);
98 /// getSchedModelForCPU - Get the machine model of a CPU.
100 const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
102 /// Get the machine model for this subtarget's CPU.
103 const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }
105 /// Return an iterator at the first process resource consumed by the given
106 /// scheduling class.
107 const MCWriteProcResEntry *getWriteProcResBegin(
108 const MCSchedClassDesc *SC) const {
109 return &WriteProcResTable[SC->WriteProcResIdx];
111 const MCWriteProcResEntry *getWriteProcResEnd(
112 const MCSchedClassDesc *SC) const {
113 return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
116 const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
117 unsigned DefIdx) const {
118 assert(DefIdx < SC->NumWriteLatencyEntries &&
119 "MachineModel does not specify a WriteResource for DefIdx");
121 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
124 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
125 unsigned WriteResID) const {
126 // TODO: The number of read advance entries in a class can be significant
127 // (~50). Consider compressing the WriteID into a dense ID of those that are
128 // used by ReadAdvance and representing them as a bitset.
129 for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
130 *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
131 if (I->UseIdx < UseIdx)
133 if (I->UseIdx > UseIdx)
135 // Find the first WriteResIdx match, which has the highest cycle count.
136 if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
143 /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
145 InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
147 /// Initialize an InstrItineraryData instance.
148 void initInstrItins(InstrItineraryData &InstrItins) const;
150 /// Check whether the CPU string is valid.
151 bool isCPUStringValid(StringRef CPU) const {
152 auto Found = std::find_if(ProcDesc.begin(), ProcDesc.end(),
153 [=](const SubtargetFeatureKV &KV) {
154 return CPU == KV.Key;
156 return Found != ProcDesc.end();
160 } // End llvm namespace