1 //=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_MC_MCREGISTERINFO_H
17 #define LLVM_MC_MCREGISTERINFO_H
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/Support/ErrorHandling.h"
25 /// An unsigned integer type large enough to represent all physical registers,
26 /// but not necessarily virtual registers.
27 typedef uint16_t MCPhysReg;
29 /// MCRegisterClass - Base class of TargetRegisterClass.
30 class MCRegisterClass {
32 typedef const MCPhysReg* iterator;
33 typedef const MCPhysReg* const_iterator;
35 const iterator RegsBegin;
36 const uint8_t *const RegSet;
37 const uint32_t NameIdx;
38 const uint16_t RegsSize;
39 const uint16_t RegSetSize;
41 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
42 const int8_t CopyCost;
43 const bool Allocatable;
45 /// getID() - Return the register class ID number.
47 unsigned getID() const { return ID; }
49 /// begin/end - Return all of the registers in this class.
51 iterator begin() const { return RegsBegin; }
52 iterator end() const { return RegsBegin + RegsSize; }
54 /// getNumRegs - Return the number of registers in this class.
56 unsigned getNumRegs() const { return RegsSize; }
58 /// getRegister - Return the specified register in the class.
60 unsigned getRegister(unsigned i) const {
61 assert(i < getNumRegs() && "Register number out of range!");
65 /// contains - Return true if the specified register is included in this
66 /// register class. This does not include virtual registers.
67 bool contains(unsigned Reg) const {
68 unsigned InByte = Reg % 8;
69 unsigned Byte = Reg / 8;
70 if (Byte >= RegSetSize)
72 return (RegSet[Byte] & (1 << InByte)) != 0;
75 /// contains - Return true if both registers are in this class.
76 bool contains(unsigned Reg1, unsigned Reg2) const {
77 return contains(Reg1) && contains(Reg2);
80 /// getSize - Return the size of the register in bytes, which is also the size
81 /// of a stack slot allocated to hold a spilled copy of this register.
82 unsigned getSize() const { return RegSize; }
84 /// getAlignment - Return the minimum required alignment for a register of
86 unsigned getAlignment() const { return Alignment; }
88 /// getCopyCost - Return the cost of copying a value between two registers in
89 /// this class. A negative number means the register class is very expensive
90 /// to copy e.g. status flag register classes.
91 int getCopyCost() const { return CopyCost; }
93 /// isAllocatable - Return true if this register class may be used to create
94 /// virtual registers.
95 bool isAllocatable() const { return Allocatable; }
98 /// MCRegisterDesc - This record contains information about a particular
99 /// register. The SubRegs field is a zero terminated array of registers that
100 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers
101 /// of AX. The SuperRegs field is a zero terminated array of registers that are
102 /// super-registers of the specific register, e.g. RAX, EAX, are
103 /// super-registers of AX.
105 struct MCRegisterDesc {
106 uint32_t Name; // Printable name for the reg (for debugging)
107 uint32_t SubRegs; // Sub-register set, described above
108 uint32_t SuperRegs; // Super-register set, described above
110 // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
111 // sub-register in SubRegs.
112 uint32_t SubRegIndices;
114 // RegUnits - Points to the list of register units. The low 4 bits holds the
115 // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
119 /// MCRegisterInfo base class - We assume that the target defines a static
120 /// array of MCRegisterDesc objects that represent all of the machine
121 /// registers that the target has. As such, we simply have to track a pointer
122 /// to this array so that we can turn register number into a register
125 /// Note this class is designed to be a base class of TargetRegisterInfo, which
126 /// is the interface used by codegen. However, specific targets *should never*
127 /// specialize this class. MCRegisterInfo should only contain getters to access
128 /// TableGen generated physical register data. It must not be extended with
131 class MCRegisterInfo {
133 typedef const MCRegisterClass *regclass_iterator;
135 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
136 /// performed with a binary search.
137 struct DwarfLLVMRegPair {
141 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
144 /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
145 /// index, -1 in any being invalid.
146 struct SubRegCoveredBits {
151 const MCRegisterDesc *Desc; // Pointer to the descriptor array
152 unsigned NumRegs; // Number of entries in the array
153 unsigned RAReg; // Return address register
154 unsigned PCReg; // Program counter register
155 const MCRegisterClass *Classes; // Pointer to the regclass array
156 unsigned NumClasses; // Number of entries in the array
157 unsigned NumRegUnits; // Number of regunits.
158 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
159 const MCPhysReg *DiffLists; // Pointer to the difflists array
160 const char *RegStrings; // Pointer to the string table.
161 const char *RegClassStrings; // Pointer to the class strings.
162 const uint16_t *SubRegIndices; // Pointer to the subreg lookup
164 const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered
166 unsigned NumSubRegIndices; // Number of subreg indices.
167 const uint16_t *RegEncodingTable; // Pointer to array of register
170 unsigned L2DwarfRegsSize;
171 unsigned EHL2DwarfRegsSize;
172 unsigned Dwarf2LRegsSize;
173 unsigned EHDwarf2LRegsSize;
174 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
175 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
176 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping
177 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
178 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
181 /// DiffListIterator - Base iterator class that can traverse the
182 /// differentially encoded register and regunit lists in DiffLists.
183 /// Don't use this class directly, use one of the specialized sub-classes
185 class DiffListIterator {
187 const MCPhysReg *List;
190 /// Create an invalid iterator. Call init() to point to something useful.
191 DiffListIterator() : Val(0), List(nullptr) {}
193 /// init - Point the iterator to InitVal, decoding subsequent values from
194 /// DiffList. The iterator will initially point to InitVal, sub-classes are
195 /// responsible for skipping the seed value if it is not part of the list.
196 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
201 /// advance - Move to the next list position, return the applied
202 /// differential. This function does not detect the end of the list, that
203 /// is the caller's responsibility (by checking for a 0 return value).
205 assert(isValid() && "Cannot move off the end of the list.");
206 MCPhysReg D = *List++;
213 /// isValid - returns true if this iterator is not yet at the end.
214 bool isValid() const { return List; }
216 /// Dereference the iterator to get the value at the current position.
217 unsigned operator*() const { return Val; }
219 /// Pre-increment to move to the next position.
221 // The end of the list is encoded as a 0 differential.
227 // These iterators are allowed to sub-class DiffListIterator and access
228 // internal list pointers.
229 friend class MCSubRegIterator;
230 friend class MCSuperRegIterator;
231 friend class MCRegUnitIterator;
232 friend class MCRegUnitRootIterator;
234 /// \brief Initialize MCRegisterInfo, called by TableGen
235 /// auto-generated routines. *DO NOT USE*.
236 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
238 const MCRegisterClass *C, unsigned NC,
239 const MCPhysReg (*RURoots)[2],
243 const char *ClassStrings,
244 const uint16_t *SubIndices,
246 const SubRegCoveredBits *SubIdxRanges,
247 const uint16_t *RET) {
254 RegStrings = Strings;
255 RegClassStrings = ClassStrings;
257 RegUnitRoots = RURoots;
259 SubRegIndices = SubIndices;
260 NumSubRegIndices = NumIndices;
261 SubRegIdxRanges = SubIdxRanges;
262 RegEncodingTable = RET;
265 /// \brief Used to initialize LLVM register to Dwarf
266 /// register number mapping. Called by TableGen auto-generated routines.
268 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
272 EHL2DwarfRegsSize = Size;
275 L2DwarfRegsSize = Size;
279 /// \brief Used to initialize Dwarf register to LLVM
280 /// register number mapping. Called by TableGen auto-generated routines.
282 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
286 EHDwarf2LRegsSize = Size;
289 Dwarf2LRegsSize = Size;
293 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
294 /// number mapping. By default the SEH register number is just the same
295 /// as the LLVM register number.
296 /// FIXME: TableGen these numbers. Currently this requires target specific
297 /// initialization code.
298 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
299 L2SEHRegs[LLVMReg] = SEHReg;
302 /// \brief This method should return the register where the return
303 /// address can be found.
304 unsigned getRARegister() const {
308 /// Return the register which is the program counter.
309 unsigned getProgramCounter() const {
313 const MCRegisterDesc &operator[](unsigned RegNo) const {
314 assert(RegNo < NumRegs &&
315 "Attempting to access record for invalid register number!");
319 /// \brief Provide a get method, equivalent to [], but more useful with a
320 /// pointer to this object.
321 const MCRegisterDesc &get(unsigned RegNo) const {
322 return operator[](RegNo);
325 /// \brief Returns the physical register number of sub-register "Index"
326 /// for physical register RegNo. Return zero if the sub-register does not
328 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
330 /// \brief Return a super-register of the specified register
331 /// Reg so its sub-register of index SubIdx is Reg.
332 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
333 const MCRegisterClass *RC) const;
335 /// \brief For a given register pair, return the sub-register index
336 /// if the second register is a sub-register of the first. Return zero
338 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
340 /// \brief Get the size of the bit range covered by a sub-register index.
341 /// If the index isn't continuous, return the sum of the sizes of its parts.
342 /// If the index is used to access subregisters of different sizes, return -1.
343 unsigned getSubRegIdxSize(unsigned Idx) const;
345 /// \brief Get the offset of the bit range covered by a sub-register index.
346 /// If an Offset doesn't make sense (the index isn't continuous, or is used to
347 /// access sub-registers at different offsets), return -1.
348 unsigned getSubRegIdxOffset(unsigned Idx) const;
350 /// \brief Return the human-readable symbolic target-specific name for the
351 /// specified physical register.
352 const char *getName(unsigned RegNo) const {
353 return RegStrings + get(RegNo).Name;
356 /// \brief Return the number of registers this target has (useful for
357 /// sizing arrays holding per register information)
358 unsigned getNumRegs() const {
362 /// \brief Return the number of sub-register indices
363 /// understood by the target. Index 0 is reserved for the no-op sub-register,
364 /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
365 unsigned getNumSubRegIndices() const {
366 return NumSubRegIndices;
369 /// \brief Return the number of (native) register units in the
370 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
371 /// can be accessed through MCRegUnitIterator defined below.
372 unsigned getNumRegUnits() const {
376 /// \brief Map a target register to an equivalent dwarf register
377 /// number. Returns -1 if there is no equivalent value. The second
378 /// parameter allows targets to use different numberings for EH info and
380 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
382 /// \brief Map a dwarf register back to a target register.
383 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
385 /// \brief Map a target register to an equivalent SEH register
386 /// number. Returns LLVM register number if there is no equivalent value.
387 int getSEHRegNum(unsigned RegNum) const;
389 regclass_iterator regclass_begin() const { return Classes; }
390 regclass_iterator regclass_end() const { return Classes+NumClasses; }
392 unsigned getNumRegClasses() const {
393 return (unsigned)(regclass_end()-regclass_begin());
396 /// \brief Returns the register class associated with the enumeration
397 /// value. See class MCOperandInfo.
398 const MCRegisterClass& getRegClass(unsigned i) const {
399 assert(i < getNumRegClasses() && "Register Class ID out of range");
403 const char *getRegClassName(const MCRegisterClass *Class) const {
404 return RegClassStrings + Class->NameIdx;
407 /// \brief Returns the encoding for RegNo
408 uint16_t getEncodingValue(unsigned RegNo) const {
409 assert(RegNo < NumRegs &&
410 "Attempting to get encoding for invalid register number!");
411 return RegEncodingTable[RegNo];
414 /// \brief Returns true if RegB is a sub-register of RegA.
415 bool isSubRegister(unsigned RegA, unsigned RegB) const {
416 return isSuperRegister(RegB, RegA);
419 /// \brief Returns true if RegB is a super-register of RegA.
420 bool isSuperRegister(unsigned RegA, unsigned RegB) const;
422 /// \brief Returns true if RegB is a sub-register of RegA or if RegB == RegA.
423 bool isSubRegisterEq(unsigned RegA, unsigned RegB) const {
424 return isSuperRegisterEq(RegB, RegA);
427 /// \brief Returns true if RegB is a super-register of RegA or if
429 bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const {
430 return RegA == RegB || isSuperRegister(RegA, RegB);
435 //===----------------------------------------------------------------------===//
436 // Register List Iterators
437 //===----------------------------------------------------------------------===//
439 // MCRegisterInfo provides lists of super-registers, sub-registers, and
440 // aliasing registers. Use these iterator classes to traverse the lists.
442 /// MCSubRegIterator enumerates all sub-registers of Reg.
443 /// If IncludeSelf is set, Reg itself is included in the list.
444 class MCSubRegIterator : public MCRegisterInfo::DiffListIterator {
446 MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
447 bool IncludeSelf = false) {
448 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
449 // Initially, the iterator points to Reg itself.
455 /// MCSuperRegIterator enumerates all super-registers of Reg.
456 /// If IncludeSelf is set, Reg itself is included in the list.
457 class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator {
459 MCSuperRegIterator() {}
460 MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
461 bool IncludeSelf = false) {
462 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
463 // Initially, the iterator points to Reg itself.
469 // Definition for isSuperRegister. Put it down here since it needs the
470 // iterator defined above in addition to the MCRegisterInfo class itself.
471 inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{
472 for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)
478 //===----------------------------------------------------------------------===//
480 //===----------------------------------------------------------------------===//
482 // Register units are used to compute register aliasing. Every register has at
483 // least one register unit, but it can have more. Two registers overlap if and
484 // only if they have a common register unit.
486 // A target with a complicated sub-register structure will typically have many
487 // fewer register units than actual registers. MCRI::getNumRegUnits() returns
488 // the number of register units in the target.
490 // MCRegUnitIterator enumerates a list of register units for Reg. The list is
491 // in ascending numerical order.
492 class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
494 /// MCRegUnitIterator - Create an iterator that traverses the register units
496 MCRegUnitIterator() {}
497 MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
498 assert(Reg && "Null register has no regunits");
499 // Decode the RegUnits MCRegisterDesc field.
500 unsigned RU = MCRI->get(Reg).RegUnits;
501 unsigned Scale = RU & 15;
502 unsigned Offset = RU >> 4;
504 // Initialize the iterator to Reg * Scale, and the List pointer to
505 // DiffLists + Offset.
506 init(Reg * Scale, MCRI->DiffLists + Offset);
508 // That may not be a valid unit, we need to advance by one to get the real
509 // unit number. The first differential can be 0 which would normally
510 // terminate the list, but since we know every register has at least one
511 // unit, we can allow a 0 differential here.
516 // Each register unit has one or two root registers. The complete set of
517 // registers containing a register unit is the union of the roots and their
518 // super-registers. All registers aliasing Unit can be visited like this:
520 // for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
521 // for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
525 /// MCRegUnitRootIterator enumerates the root registers of a register unit.
526 class MCRegUnitRootIterator {
530 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {}
531 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
532 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
533 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
534 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
537 /// \brief Dereference to get the current root register.
538 unsigned operator*() const {
542 /// \brief Check if the iterator is at the end of the list.
543 bool isValid() const {
547 /// \brief Preincrement to move to the next root register.
549 assert(isValid() && "Cannot move off the end of the list.");
555 /// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is
556 /// set, Reg itself is included in the list. This iterator does not guarantee
557 /// any ordering or that entries are unique.
558 class MCRegAliasIterator {
561 const MCRegisterInfo *MCRI;
564 MCRegUnitIterator RI;
565 MCRegUnitRootIterator RRI;
566 MCSuperRegIterator SI;
568 MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI,
570 : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
572 // Initialize the iterators.
573 for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) {
574 for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
575 for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) {
576 if (!(!IncludeSelf && Reg == *SI))
583 bool isValid() const {
587 unsigned operator*() const {
588 assert (SI.isValid() && "Cannot dereference an invalid iterator.");
593 // Assuming SI is valid.
595 if (SI.isValid()) return;
599 SI = MCSuperRegIterator(*RRI, MCRI, true);
605 RRI = MCRegUnitRootIterator(*RI, MCRI);
606 SI = MCSuperRegIterator(*RRI, MCRI, true);
611 assert(isValid() && "Cannot move off the end of the list.");
613 while (!IncludeSelf && isValid() && *SI == Reg);
617 } // End llvm namespace