1 //=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_MC_MCREGISTERINFO_H
17 #define LLVM_MC_MCREGISTERINFO_H
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/Support/ErrorHandling.h"
25 /// MCRegisterClass - Base class of TargetRegisterClass.
26 class MCRegisterClass {
28 typedef const uint16_t* iterator;
29 typedef const uint16_t* const_iterator;
32 const iterator RegsBegin;
33 const uint8_t *const RegSet;
34 const uint16_t RegsSize;
35 const uint16_t RegSetSize;
37 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
38 const int8_t CopyCost;
39 const bool Allocatable;
41 /// getID() - Return the register class ID number.
43 unsigned getID() const { return ID; }
45 /// getName() - Return the register class name for debugging.
47 const char *getName() const { return Name; }
49 /// begin/end - Return all of the registers in this class.
51 iterator begin() const { return RegsBegin; }
52 iterator end() const { return RegsBegin + RegsSize; }
54 /// getNumRegs - Return the number of registers in this class.
56 unsigned getNumRegs() const { return RegsSize; }
58 /// getRegister - Return the specified register in the class.
60 unsigned getRegister(unsigned i) const {
61 assert(i < getNumRegs() && "Register number out of range!");
65 /// contains - Return true if the specified register is included in this
66 /// register class. This does not include virtual registers.
67 bool contains(unsigned Reg) const {
68 unsigned InByte = Reg % 8;
69 unsigned Byte = Reg / 8;
70 if (Byte >= RegSetSize)
72 return (RegSet[Byte] & (1 << InByte)) != 0;
75 /// contains - Return true if both registers are in this class.
76 bool contains(unsigned Reg1, unsigned Reg2) const {
77 return contains(Reg1) && contains(Reg2);
80 /// getSize - Return the size of the register in bytes, which is also the size
81 /// of a stack slot allocated to hold a spilled copy of this register.
82 unsigned getSize() const { return RegSize; }
84 /// getAlignment - Return the minimum required alignment for a register of
86 unsigned getAlignment() const { return Alignment; }
88 /// getCopyCost - Return the cost of copying a value between two registers in
89 /// this class. A negative number means the register class is very expensive
90 /// to copy e.g. status flag register classes.
91 int getCopyCost() const { return CopyCost; }
93 /// isAllocatable - Return true if this register class may be used to create
94 /// virtual registers.
95 bool isAllocatable() const { return Allocatable; }
98 /// MCRegisterDesc - This record contains all of the information known about
99 /// a particular register. The Overlaps field contains a pointer to a zero
100 /// terminated array of registers that this register aliases, starting with
101 /// itself. This is needed for architectures like X86 which have AL alias AX
102 /// alias EAX. The SubRegs field is a zero terminated array of registers that
103 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers of
104 /// AX. The SuperRegs field is a zero terminated array of registers that are
105 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
108 struct MCRegisterDesc {
109 const char *Name; // Printable name for the reg (for debugging)
110 uint32_t Overlaps; // Overlapping registers, described above
111 uint32_t SubRegs; // Sub-register set, described above
112 uint32_t SuperRegs; // Super-register set, described above
115 /// MCRegisterInfo base class - We assume that the target defines a static
116 /// array of MCRegisterDesc objects that represent all of the machine
117 /// registers that the target has. As such, we simply have to track a pointer
118 /// to this array so that we can turn register number into a register
121 /// Note this class is designed to be a base class of TargetRegisterInfo, which
122 /// is the interface used by codegen. However, specific targets *should never*
123 /// specialize this class. MCRegisterInfo should only contain getters to access
124 /// TableGen generated physical register data. It must not be extended with
127 class MCRegisterInfo {
129 typedef const MCRegisterClass *regclass_iterator;
131 const MCRegisterDesc *Desc; // Pointer to the descriptor array
132 unsigned NumRegs; // Number of entries in the array
133 unsigned RAReg; // Return address register
134 const MCRegisterClass *Classes; // Pointer to the regclass array
135 unsigned NumClasses; // Number of entries in the array
136 const uint16_t *RegLists; // Pointer to the reglists array
137 const uint16_t *SubRegIndices; // Pointer to the subreg lookup
139 unsigned NumSubRegIndices; // Number of subreg indices.
140 DenseMap<unsigned, int> L2DwarfRegs; // LLVM to Dwarf regs mapping
141 DenseMap<unsigned, int> EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
142 DenseMap<unsigned, unsigned> Dwarf2LRegs; // Dwarf to LLVM regs mapping
143 DenseMap<unsigned, unsigned> EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
144 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
147 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
148 /// auto-generated routines. *DO NOT USE*.
149 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
150 const MCRegisterClass *C, unsigned NC,
152 const uint16_t *SubIndices,
153 unsigned NumIndices) {
160 SubRegIndices = SubIndices;
161 NumSubRegIndices = NumIndices;
164 /// mapLLVMRegToDwarfReg - Used to initialize LLVM register to Dwarf
165 /// register number mapping. Called by TableGen auto-generated routines.
167 void mapLLVMRegToDwarfReg(unsigned LLVMReg, int DwarfReg, bool isEH) {
169 EHL2DwarfRegs[LLVMReg] = DwarfReg;
171 L2DwarfRegs[LLVMReg] = DwarfReg;
174 /// mapDwarfRegToLLVMReg - Used to initialize Dwarf register to LLVM
175 /// register number mapping. Called by TableGen auto-generated routines.
177 void mapDwarfRegToLLVMReg(unsigned DwarfReg, unsigned LLVMReg, bool isEH) {
179 EHDwarf2LRegs[DwarfReg] = LLVMReg;
181 Dwarf2LRegs[DwarfReg] = LLVMReg;
184 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
185 /// number mapping. By default the SEH register number is just the same
186 /// as the LLVM register number.
187 /// FIXME: TableGen these numbers. Currently this requires target specific
188 /// initialization code.
189 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
190 L2SEHRegs[LLVMReg] = SEHReg;
193 /// getRARegister - This method should return the register where the return
194 /// address can be found.
195 unsigned getRARegister() const {
199 const MCRegisterDesc &operator[](unsigned RegNo) const {
200 assert(RegNo < NumRegs &&
201 "Attempting to access record for invalid register number!");
205 /// Provide a get method, equivalent to [], but more useful if we have a
206 /// pointer to this object.
208 const MCRegisterDesc &get(unsigned RegNo) const {
209 return operator[](RegNo);
212 /// getAliasSet - Return the set of registers aliased by the specified
213 /// register, or a null list of there are none. The list returned is zero
216 const uint16_t *getAliasSet(unsigned RegNo) const {
217 // The Overlaps set always begins with Reg itself.
218 return RegLists + get(RegNo).Overlaps + 1;
221 /// getOverlaps - Return a list of registers that overlap Reg, including
222 /// itself. This is the same as the alias set except Reg is included in the
224 /// These are exactly the registers in { x | regsOverlap(x, Reg) }.
226 const uint16_t *getOverlaps(unsigned RegNo) const {
227 return RegLists + get(RegNo).Overlaps;
230 /// getSubRegisters - Return the list of registers that are sub-registers of
231 /// the specified register, or a null list of there are none. The list
232 /// returned is zero terminated and sorted according to super-sub register
233 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
235 const uint16_t *getSubRegisters(unsigned RegNo) const {
236 return RegLists + get(RegNo).SubRegs;
239 /// getSubReg - Returns the physical register number of sub-register "Index"
240 /// for physical register RegNo. Return zero if the sub-register does not
242 unsigned getSubReg(unsigned Reg, unsigned Idx) const {
243 return *(SubRegIndices + (Reg - 1) * NumSubRegIndices + Idx - 1);
246 /// getMatchingSuperReg - Return a super-register of the specified register
247 /// Reg so its sub-register of index SubIdx is Reg.
248 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
249 const MCRegisterClass *RC) const {
250 for (const uint16_t *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
251 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
256 /// getSubRegIndex - For a given register pair, return the sub-register index
257 /// if the second register is a sub-register of the first. Return zero
259 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {
260 for (unsigned I = 1; I <= NumSubRegIndices; ++I)
261 if (getSubReg(RegNo, I) == SubRegNo)
266 /// getSuperRegisters - Return the list of registers that are super-registers
267 /// of the specified register, or a null list of there are none. The list
268 /// returned is zero terminated and sorted according to super-sub register
269 /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX.
271 const uint16_t *getSuperRegisters(unsigned RegNo) const {
272 return RegLists + get(RegNo).SuperRegs;
275 /// getName - Return the human-readable symbolic target-specific name for the
276 /// specified physical register.
277 const char *getName(unsigned RegNo) const {
278 return get(RegNo).Name;
281 /// getNumRegs - Return the number of registers this target has (useful for
282 /// sizing arrays holding per register information)
283 unsigned getNumRegs() const {
287 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
288 /// number. Returns -1 if there is no equivalent value. The second
289 /// parameter allows targets to use different numberings for EH info and
291 int getDwarfRegNum(unsigned RegNum, bool isEH) const {
292 const DenseMap<unsigned, int> &M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
293 const DenseMap<unsigned, int>::const_iterator I = M.find(RegNum);
294 if (I == M.end()) return -1;
298 /// getLLVMRegNum - Map a dwarf register back to a target register.
300 int getLLVMRegNum(unsigned RegNum, bool isEH) const {
301 const DenseMap<unsigned, unsigned> &M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
302 const DenseMap<unsigned, unsigned>::const_iterator I = M.find(RegNum);
304 llvm_unreachable("Invalid RegNum");
309 /// getSEHRegNum - Map a target register to an equivalent SEH register
310 /// number. Returns LLVM register number if there is no equivalent value.
311 int getSEHRegNum(unsigned RegNum) const {
312 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum);
313 if (I == L2SEHRegs.end()) return (int)RegNum;
317 regclass_iterator regclass_begin() const { return Classes; }
318 regclass_iterator regclass_end() const { return Classes+NumClasses; }
320 unsigned getNumRegClasses() const {
321 return (unsigned)(regclass_end()-regclass_begin());
324 /// getRegClass - Returns the register class associated with the enumeration
325 /// value. See class MCOperandInfo.
326 const MCRegisterClass getRegClass(unsigned i) const {
327 assert(i < getNumRegClasses() && "Register Class ID out of range");
332 } // End llvm namespace