1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MCOperandInfo and MCInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_MC_MCINSTRDESC_H
16 #define LLVM_MC_MCINSTRDESC_H
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/DataTypes.h"
25 //===----------------------------------------------------------------------===//
26 // Machine Operand Flags and Description
27 //===----------------------------------------------------------------------===//
30 // Operand constraints
31 enum OperandConstraint {
32 TIED_TO = 0, // Must be allocated the same register as.
33 EARLY_CLOBBER // Operand is an early clobber register operand
36 /// \brief These are flags set on operands, but should be considered
37 /// private, all access should go through the MCOperandInfo accessors.
38 /// See the accessors for a description of what these are.
39 enum OperandFlags { LookupPtrRegClass = 0, Predicate, OptionalDef };
41 /// \brief Operands are tagged with one of the values of this enum.
44 OPERAND_IMMEDIATE = 1,
48 OPERAND_FIRST_TARGET = 5
52 /// \brief This holds information about one operand of a machine instruction,
53 /// indicating the register class for register operands, etc.
56 /// \brief This specifies the register class enumeration of the operand
57 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
58 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
59 /// get a dynamic register class.
62 /// \brief These are flags from the MCOI::OperandFlags enum.
65 /// \brief Information about the type of the operand.
67 /// \brief The lower 16 bits are used to specify which constraints are set.
68 /// The higher 16 bits are used to specify the value of constraints (4 bits
72 /// \brief Set if this operand is a pointer value and it requires a callback
73 /// to look up its register class.
74 bool isLookupPtrRegClass() const {
75 return Flags & (1 << MCOI::LookupPtrRegClass);
78 /// \brief Set if this is one of the operands that made up of the predicate
79 /// operand that controls an isPredicable() instruction.
80 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
82 /// \brief Set if this operand is a optional def.
83 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
86 //===----------------------------------------------------------------------===//
87 // Machine Instruction Flags and Description
88 //===----------------------------------------------------------------------===//
91 /// \brief These should be considered private to the implementation of the
92 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc,
93 /// not use these directly. These all correspond to bitfields in the
94 /// MCInstrDesc::Flags field.
115 UnmodeledSideEffects,
130 /// \brief Describe properties that are true of each instruction in the target
131 /// description file. This captures information about side effects, register
132 /// use and many other things. There is one instance of this struct for each
133 /// target instruction class, and the MachineInstr class points to this struct
134 /// directly to describe itself.
137 unsigned short Opcode; // The opcode number
138 unsigned short NumOperands; // Num of args (may be more if variable_ops)
139 unsigned short NumDefs; // Num of args that are definitions
140 unsigned short SchedClass; // enum identifying instr sched class
141 unsigned short Size; // Number of bytes in encoding.
142 unsigned Flags; // Flags identifying machine instr class
143 uint64_t TSFlags; // Target Specific Flag values
144 const uint16_t *ImplicitUses; // Registers implicitly read by this instr
145 const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
146 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
148 DeprecatedFeatureMask; // Feature bits that this is deprecated on, if any
149 // A complex method to determine is a certain is deprecated or not, and return
150 // the reason for deprecation.
151 bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);
153 /// \brief Returns the value of the specific constraint if
154 /// it is set. Returns -1 if it is not set.
155 int getOperandConstraint(unsigned OpNum,
156 MCOI::OperandConstraint Constraint) const {
157 if (OpNum < NumOperands &&
158 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
159 unsigned Pos = 16 + Constraint * 4;
160 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
165 /// \brief Returns true if a certain instruction is deprecated and if so
166 /// returns the reason in \p Info.
167 bool getDeprecatedInfo(MCInst &MI, MCSubtargetInfo &STI,
168 std::string &Info) const;
170 /// \brief Return the opcode number for this descriptor.
171 unsigned getOpcode() const { return Opcode; }
173 /// \brief Return the number of declared MachineOperands for this
174 /// MachineInstruction. Note that variadic (isVariadic() returns true)
175 /// instructions may have additional operands at the end of the list, and note
176 /// that the machine instruction may include implicit register def/uses as
178 unsigned getNumOperands() const { return NumOperands; }
180 /// \brief Return the number of MachineOperands that are register
181 /// definitions. Register definitions always occur at the start of the
182 /// machine operand list. This is the number of "outs" in the .td file,
183 /// and does not include implicit defs.
184 unsigned getNumDefs() const { return NumDefs; }
186 /// \brief Return flags of this instruction.
187 unsigned getFlags() const { return Flags; }
189 /// \brief Return true if this instruction can have a variable number of
190 /// operands. In this case, the variable operands will be after the normal
191 /// operands but before the implicit definitions and uses (if any are
193 bool isVariadic() const { return Flags & (1 << MCID::Variadic); }
195 /// \brief Set if this instruction has an optional definition, e.g.
196 /// ARM instructions which can set condition code if 's' bit is set.
197 bool hasOptionalDef() const { return Flags & (1 << MCID::HasOptionalDef); }
199 /// \brief Return true if this is a pseudo instruction that doesn't
200 /// correspond to a real machine instruction.
201 bool isPseudo() const { return Flags & (1 << MCID::Pseudo); }
203 /// \brief Return true if the instruction is a return.
204 bool isReturn() const { return Flags & (1 << MCID::Return); }
206 /// \brief Return true if the instruction is a call.
207 bool isCall() const { return Flags & (1 << MCID::Call); }
209 /// \brief Returns true if the specified instruction stops control flow
210 /// from executing the instruction immediately following it. Examples include
211 /// unconditional branches and return instructions.
212 bool isBarrier() const { return Flags & (1 << MCID::Barrier); }
214 /// \brief Returns true if this instruction part of the terminator for
215 /// a basic block. Typically this is things like return and branch
218 /// Various passes use this to insert code into the bottom of a basic block,
219 /// but before control flow occurs.
220 bool isTerminator() const { return Flags & (1 << MCID::Terminator); }
222 /// \brief Returns true if this is a conditional, unconditional, or
223 /// indirect branch. Predicates below can be used to discriminate between
224 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
225 /// get more information.
226 bool isBranch() const { return Flags & (1 << MCID::Branch); }
228 /// \brief Return true if this is an indirect branch, such as a
229 /// branch through a register.
230 bool isIndirectBranch() const { return Flags & (1 << MCID::IndirectBranch); }
232 /// \brief Return true if this is a branch which may fall
233 /// through to the next instruction or may transfer control flow to some other
234 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
235 /// information about this branch.
236 bool isConditionalBranch() const {
237 return isBranch() & !isBarrier() & !isIndirectBranch();
240 /// \brief Return true if this is a branch which always
241 /// transfers control flow to some other block. The
242 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
243 /// about this branch.
244 bool isUnconditionalBranch() const {
245 return isBranch() & isBarrier() & !isIndirectBranch();
248 /// \brief Return true if this is a branch or an instruction which directly
249 /// writes to the program counter. Considered 'may' affect rather than
250 /// 'does' affect as things like predication are not taken into account.
251 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
253 /// \brief Return true if this instruction has a predicate operand
254 /// that controls execution. It may be set to 'always', or may be set to other
255 /// values. There are various methods in TargetInstrInfo that can be used to
256 /// control and modify the predicate in this instruction.
257 bool isPredicable() const { return Flags & (1 << MCID::Predicable); }
259 /// \brief Return true if this instruction is a comparison.
260 bool isCompare() const { return Flags & (1 << MCID::Compare); }
262 /// \brief Return true if this instruction is a move immediate
263 /// (including conditional moves) instruction.
264 bool isMoveImmediate() const { return Flags & (1 << MCID::MoveImm); }
266 /// \brief Return true if this instruction is a bitcast instruction.
267 bool isBitcast() const { return Flags & (1 << MCID::Bitcast); }
269 /// \brief Return true if this is a select instruction.
270 bool isSelect() const { return Flags & (1 << MCID::Select); }
272 /// \brief Return true if this instruction cannot be safely
273 /// duplicated. For example, if the instruction has a unique labels attached
274 /// to it, duplicating it would cause multiple definition errors.
275 bool isNotDuplicable() const { return Flags & (1 << MCID::NotDuplicable); }
277 /// \brief Returns true if the specified instruction has a delay slot which
278 /// must be filled by the code generator.
279 bool hasDelaySlot() const { return Flags & (1 << MCID::DelaySlot); }
281 /// \brief Return true for instructions that can be folded as memory operands
282 /// in other instructions. The most common use for this is instructions that
283 /// are simple loads from memory that don't modify the loaded value in any
284 /// way, but it can also be used for instructions that can be expressed as
285 /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
286 /// folded when it is beneficial. This should only be set on instructions
287 /// that return a value in their only virtual register definition.
288 bool canFoldAsLoad() const { return Flags & (1 << MCID::FoldableAsLoad); }
290 /// \brief Return true if this instruction behaves
291 /// the same way as the generic REG_SEQUENCE instructions.
293 /// dX VMOVDRR rY, rZ
295 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
297 /// Note that for the optimizers to be able to take advantage of
298 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
299 /// override accordingly.
300 bool isRegSequenceLike() const { return Flags & (1 << MCID::RegSequence); }
302 /// \brief Return true if this instruction behaves
303 /// the same way as the generic EXTRACT_SUBREG instructions.
305 /// rX, rY VMOVRRD dZ
306 /// is equivalent to two EXTRACT_SUBREG:
307 /// rX = EXTRACT_SUBREG dZ, ssub_0
308 /// rY = EXTRACT_SUBREG dZ, ssub_1
310 /// Note that for the optimizers to be able to take advantage of
311 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
312 /// override accordingly.
313 bool isExtractSubregLike() const {
314 return Flags & (1 << MCID::ExtractSubreg);
317 /// \brief Return true if this instruction behaves
318 /// the same way as the generic INSERT_SUBREG instructions.
320 /// dX = VSETLNi32 dY, rZ, Imm
321 /// is equivalent to a INSERT_SUBREG:
322 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
324 /// Note that for the optimizers to be able to take advantage of
325 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
326 /// override accordingly.
327 bool isInsertSubregLike() const { return Flags & (1 << MCID::InsertSubreg); }
329 //===--------------------------------------------------------------------===//
330 // Side Effect Analysis
331 //===--------------------------------------------------------------------===//
333 /// \brief Return true if this instruction could possibly read memory.
334 /// Instructions with this flag set are not necessarily simple load
335 /// instructions, they may load a value and modify it, for example.
336 bool mayLoad() const { return Flags & (1 << MCID::MayLoad); }
338 /// \brief Return true if this instruction could possibly modify memory.
339 /// Instructions with this flag set are not necessarily simple store
340 /// instructions, they may store a modified value based on their operands, or
341 /// may not actually modify anything, for example.
342 bool mayStore() const { return Flags & (1 << MCID::MayStore); }
344 /// \brief Return true if this instruction has side
345 /// effects that are not modeled by other flags. This does not return true
346 /// for instructions whose effects are captured by:
348 /// 1. Their operand list and implicit definition/use list. Register use/def
349 /// info is explicit for instructions.
350 /// 2. Memory accesses. Use mayLoad/mayStore.
351 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
353 /// Examples of side effects would be modifying 'invisible' machine state like
354 /// a control register, flushing a cache, modifying a register invisible to
356 bool hasUnmodeledSideEffects() const {
357 return Flags & (1 << MCID::UnmodeledSideEffects);
360 //===--------------------------------------------------------------------===//
361 // Flags that indicate whether an instruction can be modified by a method.
362 //===--------------------------------------------------------------------===//
364 /// \brief Return true if this may be a 2- or 3-address instruction (of the
365 /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
366 /// exchanged. If this flag is set, then the
367 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
370 /// Note that this flag may be set on instructions that are only commutable
371 /// sometimes. In these cases, the call to commuteInstruction will fail.
372 /// Also note that some instructions require non-trivial modification to
374 bool isCommutable() const { return Flags & (1 << MCID::Commutable); }
376 /// \brief Return true if this is a 2-address instruction which can be changed
377 /// into a 3-address instruction if needed. Doing this transformation can be
378 /// profitable in the register allocator, because it means that the
379 /// instruction can use a 2-address form if possible, but degrade into a less
380 /// efficient form if the source and dest register cannot be assigned to the
381 /// same register. For example, this allows the x86 backend to turn a "shl
382 /// reg, 3" instruction into an LEA instruction, which is the same speed as
383 /// the shift but has bigger code size.
385 /// If this returns true, then the target must implement the
386 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
387 /// is allowed to fail if the transformation isn't valid for this specific
388 /// instruction (e.g. shl reg, 4 on x86).
390 bool isConvertibleTo3Addr() const {
391 return Flags & (1 << MCID::ConvertibleTo3Addr);
394 /// \brief Return true if this instruction requires custom insertion support
395 /// when the DAG scheduler is inserting it into a machine basic block. If
396 /// this is true for the instruction, it basically means that it is a pseudo
397 /// instruction used at SelectionDAG time that is expanded out into magic code
398 /// by the target when MachineInstrs are formed.
400 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
401 /// is used to insert this into the MachineBasicBlock.
402 bool usesCustomInsertionHook() const {
403 return Flags & (1 << MCID::UsesCustomInserter);
406 /// \brief Return true if this instruction requires *adjustment* after
407 /// instruction selection by calling a target hook. For example, this can be
408 /// used to fill in ARM 's' optional operand depending on whether the
409 /// conditional flag register is used.
410 bool hasPostISelHook() const { return Flags & (1 << MCID::HasPostISelHook); }
412 /// \brief Returns true if this instruction is a candidate for remat. This
413 /// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
415 /// If this flag is set, the isReallyTriviallyReMaterializable()
416 /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
417 /// the instruction is really rematable.
418 bool isRematerializable() const {
419 return Flags & (1 << MCID::Rematerializable);
422 /// \brief Returns true if this instruction has the same cost (or less) than a
423 /// move instruction. This is useful during certain types of optimizations
424 /// (e.g., remat during two-address conversion or machine licm) where we would
425 /// like to remat or hoist the instruction, but not if it costs more than
426 /// moving the instruction into the appropriate register. Note, we are not
427 /// marking copies from and to the same register class with this flag.
429 /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
430 /// for different subtargets.
431 bool isAsCheapAsAMove() const { return Flags & (1 << MCID::CheapAsAMove); }
433 /// \brief Returns true if this instruction source operands have special
434 /// register allocation requirements that are not captured by the operand
435 /// register classes. e.g. ARM::STRD's two source registers must be an even /
436 /// odd pair, ARM::STM registers have to be in ascending order. Post-register
437 /// allocation passes should not attempt to change allocations for sources of
438 /// instructions with this flag.
439 bool hasExtraSrcRegAllocReq() const {
440 return Flags & (1 << MCID::ExtraSrcRegAllocReq);
443 /// \brief Returns true if this instruction def operands have special register
444 /// allocation requirements that are not captured by the operand register
445 /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
446 /// ARM::LDM registers have to be in ascending order. Post-register
447 /// allocation passes should not attempt to change allocations for definitions
448 /// of instructions with this flag.
449 bool hasExtraDefRegAllocReq() const {
450 return Flags & (1 << MCID::ExtraDefRegAllocReq);
453 /// \brief Return a list of registers that are potentially read by any
454 /// instance of this machine instruction. For example, on X86, the "adc"
455 /// instruction adds two register operands and adds the carry bit in from the
456 /// flags register. In this case, the instruction is marked as implicitly
457 /// reading the flags. Likewise, the variable shift instruction on X86 is
458 /// marked as implicitly reading the 'CL' register, which it always does.
460 /// This method returns null if the instruction has no implicit uses.
461 const uint16_t *getImplicitUses() const { return ImplicitUses; }
463 /// \brief Return the number of implicit uses this instruction has.
464 unsigned getNumImplicitUses() const {
468 for (; ImplicitUses[i]; ++i) /*empty*/
473 /// \brief Return a list of registers that are potentially written by any
474 /// instance of this machine instruction. For example, on X86, many
475 /// instructions implicitly set the flags register. In this case, they are
476 /// marked as setting the FLAGS. Likewise, many instructions always deposit
477 /// their result in a physical register. For example, the X86 divide
478 /// instruction always deposits the quotient and remainder in the EAX/EDX
479 /// registers. For that instruction, this will return a list containing the
480 /// EAX/EDX/EFLAGS registers.
482 /// This method returns null if the instruction has no implicit defs.
483 const uint16_t *getImplicitDefs() const { return ImplicitDefs; }
485 /// \brief Return the number of implicit defs this instruct has.
486 unsigned getNumImplicitDefs() const {
490 for (; ImplicitDefs[i]; ++i) /*empty*/
495 /// \brief Return true if this instruction implicitly
496 /// uses the specified physical register.
497 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
498 if (const uint16_t *ImpUses = ImplicitUses)
499 for (; *ImpUses; ++ImpUses)
505 /// \brief Return true if this instruction implicitly
506 /// defines the specified physical register.
507 bool hasImplicitDefOfPhysReg(unsigned Reg,
508 const MCRegisterInfo *MRI = nullptr) const;
510 /// \brief Return the scheduling class for this instruction. The
511 /// scheduling class is an index into the InstrItineraryData table. This
512 /// returns zero if there is no known scheduling information for the
514 unsigned getSchedClass() const { return SchedClass; }
516 /// \brief Return the number of bytes in the encoding of this instruction,
517 /// or zero if the encoding size cannot be known from the opcode.
518 unsigned getSize() const { return Size; }
520 /// \brief Find the index of the first operand in the
521 /// operand list that is used to represent the predicate. It returns -1 if
523 int findFirstPredOperandIdx() const {
524 if (isPredicable()) {
525 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
526 if (OpInfo[i].isPredicate())
534 /// \brief Return true if this instruction defines the specified physical
535 /// register, either explicitly or implicitly.
536 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
537 const MCRegisterInfo &RI) const;
540 } // end namespace llvm