1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MCOperandInfo and MCInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_MC_MCINSTRDESC_H
16 #define LLVM_MC_MCINSTRDESC_H
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/DataTypes.h"
25 //===----------------------------------------------------------------------===//
26 // Machine Operand Flags and Description
27 //===----------------------------------------------------------------------===//
30 // Operand constraints
31 enum OperandConstraint {
32 TIED_TO = 0, // Must be allocated the same register as.
33 EARLY_CLOBBER // Operand is an early clobber register operand
36 /// OperandFlags - These are flags set on operands, but should be considered
37 /// private, all access should go through the MCOperandInfo accessors.
38 /// See the accessors for a description of what these are.
40 LookupPtrRegClass = 0,
45 /// Operand Type - Operands are tagged with one of the values of this enum.
48 OPERAND_IMMEDIATE = 1,
52 OPERAND_FIRST_TARGET = 5
56 /// MCOperandInfo - This holds information about one operand of a machine
57 /// instruction, indicating the register class for register operands, etc.
61 /// RegClass - This specifies the register class enumeration of the operand
62 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
63 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
64 /// get a dynamic register class.
67 /// Flags - These are flags from the MCOI::OperandFlags enum.
70 /// OperandType - Information about the type of the operand.
73 /// Lower 16 bits are used to specify which constraints are set. The higher 16
74 /// bits are used to specify the value of constraints (4 bits each).
76 /// Currently no other information.
78 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
79 /// requires a callback to look up its register class.
80 bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);}
82 /// isPredicate - Set if this is one of the operands that made up of
83 /// the predicate operand that controls an isPredicable() instruction.
84 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
86 /// isOptionalDef - Set if this operand is a optional def.
88 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
92 //===----------------------------------------------------------------------===//
93 // Machine Instruction Flags and Description
94 //===----------------------------------------------------------------------===//
96 /// MCInstrDesc flags - These should be considered private to the
97 /// implementation of the MCInstrDesc class. Clients should use the predicate
98 /// methods on MCInstrDesc, not use these directly. These all correspond to
99 /// bitfields in the MCInstrDesc::Flags field.
121 UnmodeledSideEffects,
136 /// MCInstrDesc - Describe properties that are true of each instruction in the
137 /// target description file. This captures information about side effects,
138 /// register use and many other things. There is one instance of this struct
139 /// for each target instruction class, and the MachineInstr class points to
140 /// this struct directly to describe itself.
143 unsigned short Opcode; // The opcode number
144 unsigned short NumOperands; // Num of args (may be more if variable_ops)
145 unsigned short NumDefs; // Num of args that are definitions
146 unsigned short SchedClass; // enum identifying instr sched class
147 unsigned short Size; // Number of bytes in encoding.
148 unsigned Flags; // Flags identifying machine instr class
149 uint64_t TSFlags; // Target Specific Flag values
150 const uint16_t *ImplicitUses; // Registers implicitly read by this instr
151 const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
152 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
153 uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any
154 // A complex method to determine is a certain is deprecated or not, and return
155 // the reason for deprecation.
156 bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);
158 /// \brief Returns the value of the specific constraint if
159 /// it is set. Returns -1 if it is not set.
160 int getOperandConstraint(unsigned OpNum,
161 MCOI::OperandConstraint Constraint) const {
162 if (OpNum < NumOperands &&
163 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
164 unsigned Pos = 16 + Constraint * 4;
165 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
170 /// \brief Returns true if a certain instruction is deprecated and if so
171 /// returns the reason in \p Info.
172 bool getDeprecatedInfo(MCInst &MI, MCSubtargetInfo &STI,
173 std::string &Info) const {
174 if (ComplexDeprecationInfo)
175 return ComplexDeprecationInfo(MI, STI, Info);
176 if ((DeprecatedFeatureMask & STI.getFeatureBits()) != 0) {
177 // FIXME: it would be nice to include the subtarget feature here.
184 /// \brief Return the opcode number for this descriptor.
185 unsigned getOpcode() const {
189 /// \brief Return the number of declared MachineOperands for this
190 /// MachineInstruction. Note that variadic (isVariadic() returns true)
191 /// instructions may have additional operands at the end of the list, and note
192 /// that the machine instruction may include implicit register def/uses as
194 unsigned getNumOperands() const {
198 /// \brief Return the number of MachineOperands that are register
199 /// definitions. Register definitions always occur at the start of the
200 /// machine operand list. This is the number of "outs" in the .td file,
201 /// and does not include implicit defs.
202 unsigned getNumDefs() const {
206 /// \brief Return flags of this instruction.
207 unsigned getFlags() const { return Flags; }
209 /// \brief Return true if this instruction can have a variable number of
210 /// operands. In this case, the variable operands will be after the normal
211 /// operands but before the implicit definitions and uses (if any are
213 bool isVariadic() const {
214 return Flags & (1 << MCID::Variadic);
217 /// \brief Set if this instruction has an optional definition, e.g.
218 /// ARM instructions which can set condition code if 's' bit is set.
219 bool hasOptionalDef() const {
220 return Flags & (1 << MCID::HasOptionalDef);
223 /// \brief Return true if this is a pseudo instruction that doesn't
224 /// correspond to a real machine instruction.
226 bool isPseudo() const {
227 return Flags & (1 << MCID::Pseudo);
230 /// \brief Return true if the instruction is a return.
231 bool isReturn() const {
232 return Flags & (1 << MCID::Return);
235 /// \brief Return true if the instruction is a call.
236 bool isCall() const {
237 return Flags & (1 << MCID::Call);
240 /// \brief Returns true if the specified instruction stops control flow
241 /// from executing the instruction immediately following it. Examples include
242 /// unconditional branches and return instructions.
243 bool isBarrier() const {
244 return Flags & (1 << MCID::Barrier);
247 /// \brief Returns true if this instruction part of the terminator for
248 /// a basic block. Typically this is things like return and branch
251 /// Various passes use this to insert code into the bottom of a basic block,
252 /// but before control flow occurs.
253 bool isTerminator() const {
254 return Flags & (1 << MCID::Terminator);
257 /// \brief Returns true if this is a conditional, unconditional, or
258 /// indirect branch. Predicates below can be used to discriminate between
259 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
260 /// get more information.
261 bool isBranch() const {
262 return Flags & (1 << MCID::Branch);
265 /// \brief Return true if this is an indirect branch, such as a
266 /// branch through a register.
267 bool isIndirectBranch() const {
268 return Flags & (1 << MCID::IndirectBranch);
271 /// \brief Return true if this is a branch which may fall
272 /// through to the next instruction or may transfer control flow to some other
273 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
274 /// information about this branch.
275 bool isConditionalBranch() const {
276 return isBranch() & !isBarrier() & !isIndirectBranch();
279 /// \brief Return true if this is a branch which always
280 /// transfers control flow to some other block. The
281 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
282 /// about this branch.
283 bool isUnconditionalBranch() const {
284 return isBranch() & isBarrier() & !isIndirectBranch();
287 /// \brief Return true if this is a branch or an instruction which directly
288 /// writes to the program counter. Considered 'may' affect rather than
289 /// 'does' affect as things like predication are not taken into account.
290 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const {
291 if (isBranch() || isCall() || isReturn() || isIndirectBranch())
293 unsigned PC = RI.getProgramCounter();
296 if (hasDefOfPhysReg(MI, PC, RI))
298 // A variadic instruction may define PC in the variable operand list.
299 // There's currently no indication of which entries in a variable
300 // list are defs and which are uses. While that's the case, this function
301 // needs to assume they're defs in order to be conservatively correct.
302 for (int i = NumOperands, e = MI.getNumOperands(); i != e; ++i) {
303 if (MI.getOperand(i).isReg() &&
304 RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
310 /// \brief Return true if this instruction has a predicate operand
311 /// that controls execution. It may be set to 'always', or may be set to other
312 /// values. There are various methods in TargetInstrInfo that can be used to
313 /// control and modify the predicate in this instruction.
314 bool isPredicable() const {
315 return Flags & (1 << MCID::Predicable);
318 /// \brief Return true if this instruction is a comparison.
319 bool isCompare() const {
320 return Flags & (1 << MCID::Compare);
323 /// \brief Return true if this instruction is a move immediate
324 /// (including conditional moves) instruction.
325 bool isMoveImmediate() const {
326 return Flags & (1 << MCID::MoveImm);
329 /// \brief Return true if this instruction is a bitcast instruction.
330 bool isBitcast() const {
331 return Flags & (1 << MCID::Bitcast);
334 /// \brief Return true if this is a select instruction.
335 bool isSelect() const {
336 return Flags & (1 << MCID::Select);
339 /// \brief Return true if this instruction cannot be safely
340 /// duplicated. For example, if the instruction has a unique labels attached
341 /// to it, duplicating it would cause multiple definition errors.
342 bool isNotDuplicable() const {
343 return Flags & (1 << MCID::NotDuplicable);
346 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
347 /// which must be filled by the code generator.
348 bool hasDelaySlot() const {
349 return Flags & (1 << MCID::DelaySlot);
352 /// canFoldAsLoad - Return true for instructions that can be folded as
353 /// memory operands in other instructions. The most common use for this
354 /// is instructions that are simple loads from memory that don't modify
355 /// the loaded value in any way, but it can also be used for instructions
356 /// that can be expressed as constant-pool loads, such as V_SETALLONES
357 /// on x86, to allow them to be folded when it is beneficial.
358 /// This should only be set on instructions that return a value in their
359 /// only virtual register definition.
360 bool canFoldAsLoad() const {
361 return Flags & (1 << MCID::FoldableAsLoad);
364 /// \brief Return true if this instruction behaves
365 /// the same way as the generic REG_SEQUENCE instructions.
367 /// dX VMOVDRR rY, rZ
369 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
371 /// Note that for the optimizers to be able to take advantage of
372 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
373 /// override accordingly.
374 bool isRegSequenceLike() const { return Flags & (1 << MCID::RegSequence); }
376 /// \brief Return true if this instruction behaves
377 /// the same way as the generic EXTRACT_SUBREG instructions.
379 /// rX, rY VMOVRRD dZ
380 /// is equivalent to two EXTRACT_SUBREG:
381 /// rX = EXTRACT_SUBREG dZ, ssub_0
382 /// rY = EXTRACT_SUBREG dZ, ssub_1
384 /// Note that for the optimizers to be able to take advantage of
385 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
386 /// override accordingly.
387 bool isExtractSubregLike() const {
388 return Flags & (1 << MCID::ExtractSubreg);
391 /// \brief Return true if this instruction behaves
392 /// the same way as the generic INSERT_SUBREG instructions.
394 /// dX = VSETLNi32 dY, rZ, Imm
395 /// is equivalent to a INSERT_SUBREG:
396 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
398 /// Note that for the optimizers to be able to take advantage of
399 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
400 /// override accordingly.
401 bool isInsertSubregLike() const {
402 return Flags & (1 << MCID::InsertSubreg);
405 //===--------------------------------------------------------------------===//
406 // Side Effect Analysis
407 //===--------------------------------------------------------------------===//
409 /// \brief Return true if this instruction could possibly read memory.
410 /// Instructions with this flag set are not necessarily simple load
411 /// instructions, they may load a value and modify it, for example.
412 bool mayLoad() const {
413 return Flags & (1 << MCID::MayLoad);
417 /// \brief Return true if this instruction could possibly modify memory.
418 /// Instructions with this flag set are not necessarily simple store
419 /// instructions, they may store a modified value based on their operands, or
420 /// may not actually modify anything, for example.
421 bool mayStore() const {
422 return Flags & (1 << MCID::MayStore);
425 /// hasUnmodeledSideEffects - Return true if this instruction has side
426 /// effects that are not modeled by other flags. This does not return true
427 /// for instructions whose effects are captured by:
429 /// 1. Their operand list and implicit definition/use list. Register use/def
430 /// info is explicit for instructions.
431 /// 2. Memory accesses. Use mayLoad/mayStore.
432 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
434 /// Examples of side effects would be modifying 'invisible' machine state like
435 /// a control register, flushing a cache, modifying a register invisible to
438 bool hasUnmodeledSideEffects() const {
439 return Flags & (1 << MCID::UnmodeledSideEffects);
442 //===--------------------------------------------------------------------===//
443 // Flags that indicate whether an instruction can be modified by a method.
444 //===--------------------------------------------------------------------===//
446 /// isCommutable - Return true if this may be a 2- or 3-address
447 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
448 /// result if Y and Z are exchanged. If this flag is set, then the
449 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
452 /// Note that this flag may be set on instructions that are only commutable
453 /// sometimes. In these cases, the call to commuteInstruction will fail.
454 /// Also note that some instructions require non-trivial modification to
456 bool isCommutable() const {
457 return Flags & (1 << MCID::Commutable);
460 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
461 /// which can be changed into a 3-address instruction if needed. Doing this
462 /// transformation can be profitable in the register allocator, because it
463 /// means that the instruction can use a 2-address form if possible, but
464 /// degrade into a less efficient form if the source and dest register cannot
465 /// be assigned to the same register. For example, this allows the x86
466 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
467 /// is the same speed as the shift but has bigger code size.
469 /// If this returns true, then the target must implement the
470 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
471 /// is allowed to fail if the transformation isn't valid for this specific
472 /// instruction (e.g. shl reg, 4 on x86).
474 bool isConvertibleTo3Addr() const {
475 return Flags & (1 << MCID::ConvertibleTo3Addr);
478 /// usesCustomInsertionHook - Return true if this instruction requires
479 /// custom insertion support when the DAG scheduler is inserting it into a
480 /// machine basic block. If this is true for the instruction, it basically
481 /// means that it is a pseudo instruction used at SelectionDAG time that is
482 /// expanded out into magic code by the target when MachineInstrs are formed.
484 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
485 /// is used to insert this into the MachineBasicBlock.
486 bool usesCustomInsertionHook() const {
487 return Flags & (1 << MCID::UsesCustomInserter);
490 /// hasPostISelHook - Return true if this instruction requires *adjustment*
491 /// after instruction selection by calling a target hook. For example, this
492 /// can be used to fill in ARM 's' optional operand depending on whether
493 /// the conditional flag register is used.
494 bool hasPostISelHook() const {
495 return Flags & (1 << MCID::HasPostISelHook);
498 /// isRematerializable - Returns true if this instruction is a candidate for
499 /// remat. This flag is only used in TargetInstrInfo method
500 /// isTriviallyRematerializable.
502 /// If this flag is set, the isReallyTriviallyReMaterializable()
503 /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
504 /// the instruction is really rematable.
505 bool isRematerializable() const {
506 return Flags & (1 << MCID::Rematerializable);
509 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
510 /// less) than a move instruction. This is useful during certain types of
511 /// optimizations (e.g., remat during two-address conversion or machine licm)
512 /// where we would like to remat or hoist the instruction, but not if it costs
513 /// more than moving the instruction into the appropriate register. Note, we
514 /// are not marking copies from and to the same register class with this flag.
516 /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
517 /// for different subtargets.
518 bool isAsCheapAsAMove() const {
519 return Flags & (1 << MCID::CheapAsAMove);
522 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
523 /// have special register allocation requirements that are not captured by the
524 /// operand register classes. e.g. ARM::STRD's two source registers must be an
525 /// even / odd pair, ARM::STM registers have to be in ascending order.
526 /// Post-register allocation passes should not attempt to change allocations
527 /// for sources of instructions with this flag.
528 bool hasExtraSrcRegAllocReq() const {
529 return Flags & (1 << MCID::ExtraSrcRegAllocReq);
532 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
533 /// have special register allocation requirements that are not captured by the
534 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
535 /// even / odd pair, ARM::LDM registers have to be in ascending order.
536 /// Post-register allocation passes should not attempt to change allocations
537 /// for definitions of instructions with this flag.
538 bool hasExtraDefRegAllocReq() const {
539 return Flags & (1 << MCID::ExtraDefRegAllocReq);
543 /// getImplicitUses - Return a list of registers that are potentially
544 /// read by any instance of this machine instruction. For example, on X86,
545 /// the "adc" instruction adds two register operands and adds the carry bit in
546 /// from the flags register. In this case, the instruction is marked as
547 /// implicitly reading the flags. Likewise, the variable shift instruction on
548 /// X86 is marked as implicitly reading the 'CL' register, which it always
551 /// This method returns null if the instruction has no implicit uses.
552 const uint16_t *getImplicitUses() const {
556 /// \brief Return the number of implicit uses this instruction has.
557 unsigned getNumImplicitUses() const {
558 if (!ImplicitUses) return 0;
560 for (; ImplicitUses[i]; ++i) /*empty*/;
564 /// getImplicitDefs - Return a list of registers that are potentially
565 /// written by any instance of this machine instruction. For example, on X86,
566 /// many instructions implicitly set the flags register. In this case, they
567 /// are marked as setting the FLAGS. Likewise, many instructions always
568 /// deposit their result in a physical register. For example, the X86 divide
569 /// instruction always deposits the quotient and remainder in the EAX/EDX
570 /// registers. For that instruction, this will return a list containing the
571 /// EAX/EDX/EFLAGS registers.
573 /// This method returns null if the instruction has no implicit defs.
574 const uint16_t *getImplicitDefs() const {
578 /// \brief Return the number of implicit defs this instruct has.
579 unsigned getNumImplicitDefs() const {
580 if (!ImplicitDefs) return 0;
582 for (; ImplicitDefs[i]; ++i) /*empty*/;
586 /// \brief Return true if this instruction implicitly
587 /// uses the specified physical register.
588 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
589 if (const uint16_t *ImpUses = ImplicitUses)
590 for (; *ImpUses; ++ImpUses)
591 if (*ImpUses == Reg) return true;
595 /// \brief Return true if this instruction implicitly
596 /// defines the specified physical register.
597 bool hasImplicitDefOfPhysReg(unsigned Reg,
598 const MCRegisterInfo *MRI = nullptr) const {
599 if (const uint16_t *ImpDefs = ImplicitDefs)
600 for (; *ImpDefs; ++ImpDefs)
601 if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
606 /// \brief Return true if this instruction defines the specified physical
607 /// register, either explicitly or implicitly.
608 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
609 const MCRegisterInfo &RI) const {
610 for (int i = 0, e = NumDefs; i != e; ++i)
611 if (MI.getOperand(i).isReg() &&
612 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
614 return hasImplicitDefOfPhysReg(Reg, &RI);
617 /// \brief Return the scheduling class for this instruction. The
618 /// scheduling class is an index into the InstrItineraryData table. This
619 /// returns zero if there is no known scheduling information for the
621 unsigned getSchedClass() const {
625 /// \brief Return the number of bytes in the encoding of this instruction,
626 /// or zero if the encoding size cannot be known from the opcode.
627 unsigned getSize() const {
631 /// \brief Find the index of the first operand in the
632 /// operand list that is used to represent the predicate. It returns -1 if
634 int findFirstPredOperandIdx() const {
635 if (isPredicable()) {
636 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
637 if (OpInfo[i].isPredicate())
644 } // end namespace llvm