1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MCOperandInfo and MCInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_MC_MCINSTRDESC_H
16 #define LLVM_MC_MCINSTRDESC_H
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/DataTypes.h"
25 //===----------------------------------------------------------------------===//
26 // Machine Operand Flags and Description
27 //===----------------------------------------------------------------------===//
30 // Operand constraints
31 enum OperandConstraint {
32 TIED_TO = 0, // Must be allocated the same register as.
33 EARLY_CLOBBER // Operand is an early clobber register operand
36 /// \brief These are flags set on operands, but should be considered
37 /// private, all access should go through the MCOperandInfo accessors.
38 /// See the accessors for a description of what these are.
39 enum OperandFlags { LookupPtrRegClass = 0, Predicate, OptionalDef };
41 /// \brief Operands are tagged with one of the values of this enum.
44 OPERAND_IMMEDIATE = 1,
48 OPERAND_FIRST_TARGET = 5
52 /// \brief This holds information about one operand of a machine instruction,
53 /// indicating the register class for register operands, etc.
56 /// \brief This specifies the register class enumeration of the operand
57 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
58 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
59 /// get a dynamic register class.
62 /// \brief These are flags from the MCOI::OperandFlags enum.
65 /// \brief Information about the type of the operand.
67 /// \brief The lower 16 bits are used to specify which constraints are set.
68 /// The higher 16 bits are used to specify the value of constraints (4 bits
72 /// \brief Set if this operand is a pointer value and it requires a callback
73 /// to look up its register class.
74 bool isLookupPtrRegClass() const {
75 return Flags & (1 << MCOI::LookupPtrRegClass);
78 /// \brief Set if this is one of the operands that made up of the predicate
79 /// operand that controls an isPredicable() instruction.
80 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
82 /// \brief Set if this operand is a optional def.
83 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
86 //===----------------------------------------------------------------------===//
87 // Machine Instruction Flags and Description
88 //===----------------------------------------------------------------------===//
91 /// \brief These should be considered private to the implementation of the
92 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc,
93 /// not use these directly. These all correspond to bitfields in the
94 /// MCInstrDesc::Flags field.
115 UnmodeledSideEffects,
130 /// \brief Describe properties that are true of each instruction in the target
131 /// description file. This captures information about side effects, register
132 /// use and many other things. There is one instance of this struct for each
133 /// target instruction class, and the MachineInstr class points to this struct
134 /// directly to describe itself.
137 unsigned short Opcode; // The opcode number
138 unsigned short NumOperands; // Num of args (may be more if variable_ops)
139 unsigned short NumDefs; // Num of args that are definitions
140 unsigned short SchedClass; // enum identifying instr sched class
141 unsigned short Size; // Number of bytes in encoding.
142 unsigned Flags; // Flags identifying machine instr class
143 uint64_t TSFlags; // Target Specific Flag values
144 const uint16_t *ImplicitUses; // Registers implicitly read by this instr
145 const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
146 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
148 DeprecatedFeatureMask; // Feature bits that this is deprecated on, if any
150 // A complex method to determine is a certain is deprecated or not, and return
151 // the reason for deprecation.
152 bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);
154 /// \brief Returns the value of the specific constraint if
155 /// it is set. Returns -1 if it is not set.
156 int getOperandConstraint(unsigned OpNum,
157 MCOI::OperandConstraint Constraint) const {
158 if (OpNum < NumOperands &&
159 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
160 unsigned Pos = 16 + Constraint * 4;
161 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
166 /// \brief Returns true if a certain instruction is deprecated and if so
167 /// returns the reason in \p Info.
168 bool getDeprecatedInfo(MCInst &MI, MCSubtargetInfo &STI,
169 std::string &Info) const {
170 if (ComplexDeprecationInfo)
171 return ComplexDeprecationInfo(MI, STI, Info);
172 if ((STI.getFeatureBits() & DeprecatedFeatureMask).any()) {
173 // FIXME: it would be nice to include the subtarget feature here.
180 /// \brief Return the opcode number for this descriptor.
181 unsigned getOpcode() const { return Opcode; }
183 /// \brief Return the number of declared MachineOperands for this
184 /// MachineInstruction. Note that variadic (isVariadic() returns true)
185 /// instructions may have additional operands at the end of the list, and note
186 /// that the machine instruction may include implicit register def/uses as
188 unsigned getNumOperands() const { return NumOperands; }
190 /// \brief Return the number of MachineOperands that are register
191 /// definitions. Register definitions always occur at the start of the
192 /// machine operand list. This is the number of "outs" in the .td file,
193 /// and does not include implicit defs.
194 unsigned getNumDefs() const { return NumDefs; }
196 /// \brief Return flags of this instruction.
197 unsigned getFlags() const { return Flags; }
199 /// \brief Return true if this instruction can have a variable number of
200 /// operands. In this case, the variable operands will be after the normal
201 /// operands but before the implicit definitions and uses (if any are
203 bool isVariadic() const { return Flags & (1 << MCID::Variadic); }
205 /// \brief Set if this instruction has an optional definition, e.g.
206 /// ARM instructions which can set condition code if 's' bit is set.
207 bool hasOptionalDef() const { return Flags & (1 << MCID::HasOptionalDef); }
209 /// \brief Return true if this is a pseudo instruction that doesn't
210 /// correspond to a real machine instruction.
211 bool isPseudo() const { return Flags & (1 << MCID::Pseudo); }
213 /// \brief Return true if the instruction is a return.
214 bool isReturn() const { return Flags & (1 << MCID::Return); }
216 /// \brief Return true if the instruction is a call.
217 bool isCall() const { return Flags & (1 << MCID::Call); }
219 /// \brief Returns true if the specified instruction stops control flow
220 /// from executing the instruction immediately following it. Examples include
221 /// unconditional branches and return instructions.
222 bool isBarrier() const { return Flags & (1 << MCID::Barrier); }
224 /// \brief Returns true if this instruction part of the terminator for
225 /// a basic block. Typically this is things like return and branch
228 /// Various passes use this to insert code into the bottom of a basic block,
229 /// but before control flow occurs.
230 bool isTerminator() const { return Flags & (1 << MCID::Terminator); }
232 /// \brief Returns true if this is a conditional, unconditional, or
233 /// indirect branch. Predicates below can be used to discriminate between
234 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
235 /// get more information.
236 bool isBranch() const { return Flags & (1 << MCID::Branch); }
238 /// \brief Return true if this is an indirect branch, such as a
239 /// branch through a register.
240 bool isIndirectBranch() const { return Flags & (1 << MCID::IndirectBranch); }
242 /// \brief Return true if this is a branch which may fall
243 /// through to the next instruction or may transfer control flow to some other
244 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
245 /// information about this branch.
246 bool isConditionalBranch() const {
247 return isBranch() & !isBarrier() & !isIndirectBranch();
250 /// \brief Return true if this is a branch which always
251 /// transfers control flow to some other block. The
252 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
253 /// about this branch.
254 bool isUnconditionalBranch() const {
255 return isBranch() & isBarrier() & !isIndirectBranch();
258 /// \brief Return true if this is a branch or an instruction which directly
259 /// writes to the program counter. Considered 'may' affect rather than
260 /// 'does' affect as things like predication are not taken into account.
261 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const {
262 if (isBranch() || isCall() || isReturn() || isIndirectBranch())
264 unsigned PC = RI.getProgramCounter();
267 if (hasDefOfPhysReg(MI, PC, RI))
269 // A variadic instruction may define PC in the variable operand list.
270 // There's currently no indication of which entries in a variable
271 // list are defs and which are uses. While that's the case, this function
272 // needs to assume they're defs in order to be conservatively correct.
273 for (int i = NumOperands, e = MI.getNumOperands(); i != e; ++i) {
274 if (MI.getOperand(i).isReg() &&
275 RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
281 /// \brief Return true if this instruction has a predicate operand
282 /// that controls execution. It may be set to 'always', or may be set to other
283 /// values. There are various methods in TargetInstrInfo that can be used to
284 /// control and modify the predicate in this instruction.
285 bool isPredicable() const { return Flags & (1 << MCID::Predicable); }
287 /// \brief Return true if this instruction is a comparison.
288 bool isCompare() const { return Flags & (1 << MCID::Compare); }
290 /// \brief Return true if this instruction is a move immediate
291 /// (including conditional moves) instruction.
292 bool isMoveImmediate() const { return Flags & (1 << MCID::MoveImm); }
294 /// \brief Return true if this instruction is a bitcast instruction.
295 bool isBitcast() const { return Flags & (1 << MCID::Bitcast); }
297 /// \brief Return true if this is a select instruction.
298 bool isSelect() const { return Flags & (1 << MCID::Select); }
300 /// \brief Return true if this instruction cannot be safely
301 /// duplicated. For example, if the instruction has a unique labels attached
302 /// to it, duplicating it would cause multiple definition errors.
303 bool isNotDuplicable() const { return Flags & (1 << MCID::NotDuplicable); }
305 /// \brief Returns true if the specified instruction has a delay slot which
306 /// must be filled by the code generator.
307 bool hasDelaySlot() const { return Flags & (1 << MCID::DelaySlot); }
309 /// \brief Return true for instructions that can be folded as memory operands
310 /// in other instructions. The most common use for this is instructions that
311 /// are simple loads from memory that don't modify the loaded value in any
312 /// way, but it can also be used for instructions that can be expressed as
313 /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
314 /// folded when it is beneficial. This should only be set on instructions
315 /// that return a value in their only virtual register definition.
316 bool canFoldAsLoad() const { return Flags & (1 << MCID::FoldableAsLoad); }
318 /// \brief Return true if this instruction behaves
319 /// the same way as the generic REG_SEQUENCE instructions.
321 /// dX VMOVDRR rY, rZ
323 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
325 /// Note that for the optimizers to be able to take advantage of
326 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
327 /// override accordingly.
328 bool isRegSequenceLike() const { return Flags & (1 << MCID::RegSequence); }
330 /// \brief Return true if this instruction behaves
331 /// the same way as the generic EXTRACT_SUBREG instructions.
333 /// rX, rY VMOVRRD dZ
334 /// is equivalent to two EXTRACT_SUBREG:
335 /// rX = EXTRACT_SUBREG dZ, ssub_0
336 /// rY = EXTRACT_SUBREG dZ, ssub_1
338 /// Note that for the optimizers to be able to take advantage of
339 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
340 /// override accordingly.
341 bool isExtractSubregLike() const {
342 return Flags & (1 << MCID::ExtractSubreg);
345 /// \brief Return true if this instruction behaves
346 /// the same way as the generic INSERT_SUBREG instructions.
348 /// dX = VSETLNi32 dY, rZ, Imm
349 /// is equivalent to a INSERT_SUBREG:
350 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
352 /// Note that for the optimizers to be able to take advantage of
353 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
354 /// override accordingly.
355 bool isInsertSubregLike() const { return Flags & (1 << MCID::InsertSubreg); }
357 //===--------------------------------------------------------------------===//
358 // Side Effect Analysis
359 //===--------------------------------------------------------------------===//
361 /// \brief Return true if this instruction could possibly read memory.
362 /// Instructions with this flag set are not necessarily simple load
363 /// instructions, they may load a value and modify it, for example.
364 bool mayLoad() const { return Flags & (1 << MCID::MayLoad); }
366 /// \brief Return true if this instruction could possibly modify memory.
367 /// Instructions with this flag set are not necessarily simple store
368 /// instructions, they may store a modified value based on their operands, or
369 /// may not actually modify anything, for example.
370 bool mayStore() const { return Flags & (1 << MCID::MayStore); }
372 /// \brief Return true if this instruction has side
373 /// effects that are not modeled by other flags. This does not return true
374 /// for instructions whose effects are captured by:
376 /// 1. Their operand list and implicit definition/use list. Register use/def
377 /// info is explicit for instructions.
378 /// 2. Memory accesses. Use mayLoad/mayStore.
379 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
381 /// Examples of side effects would be modifying 'invisible' machine state like
382 /// a control register, flushing a cache, modifying a register invisible to
384 bool hasUnmodeledSideEffects() const {
385 return Flags & (1 << MCID::UnmodeledSideEffects);
388 //===--------------------------------------------------------------------===//
389 // Flags that indicate whether an instruction can be modified by a method.
390 //===--------------------------------------------------------------------===//
392 /// \brief Return true if this may be a 2- or 3-address instruction (of the
393 /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
394 /// exchanged. If this flag is set, then the
395 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
398 /// Note that this flag may be set on instructions that are only commutable
399 /// sometimes. In these cases, the call to commuteInstruction will fail.
400 /// Also note that some instructions require non-trivial modification to
402 bool isCommutable() const { return Flags & (1 << MCID::Commutable); }
404 /// \brief Return true if this is a 2-address instruction which can be changed
405 /// into a 3-address instruction if needed. Doing this transformation can be
406 /// profitable in the register allocator, because it means that the
407 /// instruction can use a 2-address form if possible, but degrade into a less
408 /// efficient form if the source and dest register cannot be assigned to the
409 /// same register. For example, this allows the x86 backend to turn a "shl
410 /// reg, 3" instruction into an LEA instruction, which is the same speed as
411 /// the shift but has bigger code size.
413 /// If this returns true, then the target must implement the
414 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
415 /// is allowed to fail if the transformation isn't valid for this specific
416 /// instruction (e.g. shl reg, 4 on x86).
418 bool isConvertibleTo3Addr() const {
419 return Flags & (1 << MCID::ConvertibleTo3Addr);
422 /// \brief Return true if this instruction requires custom insertion support
423 /// when the DAG scheduler is inserting it into a machine basic block. If
424 /// this is true for the instruction, it basically means that it is a pseudo
425 /// instruction used at SelectionDAG time that is expanded out into magic code
426 /// by the target when MachineInstrs are formed.
428 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
429 /// is used to insert this into the MachineBasicBlock.
430 bool usesCustomInsertionHook() const {
431 return Flags & (1 << MCID::UsesCustomInserter);
434 /// \brief Return true if this instruction requires *adjustment* after
435 /// instruction selection by calling a target hook. For example, this can be
436 /// used to fill in ARM 's' optional operand depending on whether the
437 /// conditional flag register is used.
438 bool hasPostISelHook() const { return Flags & (1 << MCID::HasPostISelHook); }
440 /// \brief Returns true if this instruction is a candidate for remat. This
441 /// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
443 /// If this flag is set, the isReallyTriviallyReMaterializable()
444 /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
445 /// the instruction is really rematable.
446 bool isRematerializable() const {
447 return Flags & (1 << MCID::Rematerializable);
450 /// \brief Returns true if this instruction has the same cost (or less) than a
451 /// move instruction. This is useful during certain types of optimizations
452 /// (e.g., remat during two-address conversion or machine licm) where we would
453 /// like to remat or hoist the instruction, but not if it costs more than
454 /// moving the instruction into the appropriate register. Note, we are not
455 /// marking copies from and to the same register class with this flag.
457 /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
458 /// for different subtargets.
459 bool isAsCheapAsAMove() const { return Flags & (1 << MCID::CheapAsAMove); }
461 /// \brief Returns true if this instruction source operands have special
462 /// register allocation requirements that are not captured by the operand
463 /// register classes. e.g. ARM::STRD's two source registers must be an even /
464 /// odd pair, ARM::STM registers have to be in ascending order. Post-register
465 /// allocation passes should not attempt to change allocations for sources of
466 /// instructions with this flag.
467 bool hasExtraSrcRegAllocReq() const {
468 return Flags & (1 << MCID::ExtraSrcRegAllocReq);
471 /// \brief Returns true if this instruction def operands have special register
472 /// allocation requirements that are not captured by the operand register
473 /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
474 /// ARM::LDM registers have to be in ascending order. Post-register
475 /// allocation passes should not attempt to change allocations for definitions
476 /// of instructions with this flag.
477 bool hasExtraDefRegAllocReq() const {
478 return Flags & (1 << MCID::ExtraDefRegAllocReq);
481 /// \brief Return a list of registers that are potentially read by any
482 /// instance of this machine instruction. For example, on X86, the "adc"
483 /// instruction adds two register operands and adds the carry bit in from the
484 /// flags register. In this case, the instruction is marked as implicitly
485 /// reading the flags. Likewise, the variable shift instruction on X86 is
486 /// marked as implicitly reading the 'CL' register, which it always does.
488 /// This method returns null if the instruction has no implicit uses.
489 const uint16_t *getImplicitUses() const { return ImplicitUses; }
491 /// \brief Return the number of implicit uses this instruction has.
492 unsigned getNumImplicitUses() const {
496 for (; ImplicitUses[i]; ++i) /*empty*/
501 /// \brief Return a list of registers that are potentially written by any
502 /// instance of this machine instruction. For example, on X86, many
503 /// instructions implicitly set the flags register. In this case, they are
504 /// marked as setting the FLAGS. Likewise, many instructions always deposit
505 /// their result in a physical register. For example, the X86 divide
506 /// instruction always deposits the quotient and remainder in the EAX/EDX
507 /// registers. For that instruction, this will return a list containing the
508 /// EAX/EDX/EFLAGS registers.
510 /// This method returns null if the instruction has no implicit defs.
511 const uint16_t *getImplicitDefs() const { return ImplicitDefs; }
513 /// \brief Return the number of implicit defs this instruct has.
514 unsigned getNumImplicitDefs() const {
518 for (; ImplicitDefs[i]; ++i) /*empty*/
523 /// \brief Return true if this instruction implicitly
524 /// uses the specified physical register.
525 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
526 if (const uint16_t *ImpUses = ImplicitUses)
527 for (; *ImpUses; ++ImpUses)
533 /// \brief Return true if this instruction implicitly
534 /// defines the specified physical register.
535 bool hasImplicitDefOfPhysReg(unsigned Reg,
536 const MCRegisterInfo *MRI = nullptr) const {
537 if (const uint16_t *ImpDefs = ImplicitDefs)
538 for (; *ImpDefs; ++ImpDefs)
539 if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
544 /// \brief Return true if this instruction defines the specified physical
545 /// register, either explicitly or implicitly.
546 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
547 const MCRegisterInfo &RI) const {
548 for (int i = 0, e = NumDefs; i != e; ++i)
549 if (MI.getOperand(i).isReg() &&
550 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
552 return hasImplicitDefOfPhysReg(Reg, &RI);
555 /// \brief Return the scheduling class for this instruction. The
556 /// scheduling class is an index into the InstrItineraryData table. This
557 /// returns zero if there is no known scheduling information for the
559 unsigned getSchedClass() const { return SchedClass; }
561 /// \brief Return the number of bytes in the encoding of this instruction,
562 /// or zero if the encoding size cannot be known from the opcode.
563 unsigned getSize() const { return Size; }
565 /// \brief Find the index of the first operand in the
566 /// operand list that is used to represent the predicate. It returns -1 if
568 int findFirstPredOperandIdx() const {
569 if (isPredicable()) {
570 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
571 if (OpInfo[i].isPredicate())
578 } // end namespace llvm