1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MCOperandInfo and MCInstrDesc classes, which
11 // are used to describe target instructions and their operands.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_MC_MCINSTRDESC_H
16 #define LLVM_MC_MCINSTRDESC_H
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/DataTypes.h"
25 //===----------------------------------------------------------------------===//
26 // Machine Operand Flags and Description
27 //===----------------------------------------------------------------------===//
30 // Operand constraints
31 enum OperandConstraint {
32 TIED_TO = 0, // Must be allocated the same register as.
33 EARLY_CLOBBER // Operand is an early clobber register operand
36 /// OperandFlags - These are flags set on operands, but should be considered
37 /// private, all access should go through the MCOperandInfo accessors.
38 /// See the accessors for a description of what these are.
40 LookupPtrRegClass = 0,
45 /// Operand Type - Operands are tagged with one of the values of this enum.
55 /// MCOperandInfo - This holds information about one operand of a machine
56 /// instruction, indicating the register class for register operands, etc.
60 /// RegClass - This specifies the register class enumeration of the operand
61 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
62 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
63 /// get a dynamic register class.
66 /// Flags - These are flags from the MCOI::OperandFlags enum.
69 /// OperandType - Information about the type of the operand.
72 /// Lower 16 bits are used to specify which constraints are set. The higher 16
73 /// bits are used to specify the value of constraints (4 bits each).
75 /// Currently no other information.
77 /// isLookupPtrRegClass - Set if this operand is a pointer value and it
78 /// requires a callback to look up its register class.
79 bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);}
81 /// isPredicate - Set if this is one of the operands that made up of
82 /// the predicate operand that controls an isPredicable() instruction.
83 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
85 /// isOptionalDef - Set if this operand is a optional def.
87 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
91 //===----------------------------------------------------------------------===//
92 // Machine Instruction Flags and Description
93 //===----------------------------------------------------------------------===//
95 /// MCInstrDesc flags - These should be considered private to the
96 /// implementation of the MCInstrDesc class. Clients should use the predicate
97 /// methods on MCInstrDesc, not use these directly. These all correspond to
98 /// bitfields in the MCInstrDesc::Flags field.
120 UnmodeledSideEffects,
134 /// MCInstrDesc - Describe properties that are true of each instruction in the
135 /// target description file. This captures information about side effects,
136 /// register use and many other things. There is one instance of this struct
137 /// for each target instruction class, and the MachineInstr class points to
138 /// this struct directly to describe itself.
141 unsigned short Opcode; // The opcode number
142 unsigned short NumOperands; // Num of args (may be more if variable_ops)
143 unsigned short NumDefs; // Num of args that are definitions
144 unsigned short SchedClass; // enum identifying instr sched class
145 unsigned short Size; // Number of bytes in encoding.
146 unsigned Flags; // Flags identifying machine instr class
147 uint64_t TSFlags; // Target Specific Flag values
148 const uint16_t *ImplicitUses; // Registers implicitly read by this instr
149 const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
150 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
151 uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any
152 // A complex method to determine is a certain is deprecated or not, and return
153 // the reason for deprecation.
154 bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);
156 /// \brief Returns the value of the specific constraint if
157 /// it is set. Returns -1 if it is not set.
158 int getOperandConstraint(unsigned OpNum,
159 MCOI::OperandConstraint Constraint) const {
160 if (OpNum < NumOperands &&
161 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
162 unsigned Pos = 16 + Constraint * 4;
163 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
168 /// \brief Returns true if a certain instruction is deprecated and if so
169 /// returns the reason in \p Info.
170 bool getDeprecatedInfo(MCInst &MI, MCSubtargetInfo &STI,
171 std::string &Info) const {
172 if (ComplexDeprecationInfo)
173 return ComplexDeprecationInfo(MI, STI, Info);
174 if ((DeprecatedFeatureMask & STI.getFeatureBits()) != 0) {
175 // FIXME: it would be nice to include the subtarget feature here.
182 /// \brief Return the opcode number for this descriptor.
183 unsigned getOpcode() const {
187 /// \brief Return the number of declared MachineOperands for this
188 /// MachineInstruction. Note that variadic (isVariadic() returns true)
189 /// instructions may have additional operands at the end of the list, and note
190 /// that the machine instruction may include implicit register def/uses as
192 unsigned getNumOperands() const {
196 /// \brief Return the number of MachineOperands that are register
197 /// definitions. Register definitions always occur at the start of the
198 /// machine operand list. This is the number of "outs" in the .td file,
199 /// and does not include implicit defs.
200 unsigned getNumDefs() const {
204 /// \brief Return flags of this instruction.
205 unsigned getFlags() const { return Flags; }
207 /// \brief Return true if this instruction can have a variable number of
208 /// operands. In this case, the variable operands will be after the normal
209 /// operands but before the implicit definitions and uses (if any are
211 bool isVariadic() const {
212 return Flags & (1 << MCID::Variadic);
215 /// \brief Set if this instruction has an optional definition, e.g.
216 /// ARM instructions which can set condition code if 's' bit is set.
217 bool hasOptionalDef() const {
218 return Flags & (1 << MCID::HasOptionalDef);
221 /// \brief Return true if this is a pseudo instruction that doesn't
222 /// correspond to a real machine instruction.
224 bool isPseudo() const {
225 return Flags & (1 << MCID::Pseudo);
228 /// \brief Return true if the instruction is a return.
229 bool isReturn() const {
230 return Flags & (1 << MCID::Return);
233 /// \brief Return true if the instruction is a call.
234 bool isCall() const {
235 return Flags & (1 << MCID::Call);
238 /// \brief Returns true if the specified instruction stops control flow
239 /// from executing the instruction immediately following it. Examples include
240 /// unconditional branches and return instructions.
241 bool isBarrier() const {
242 return Flags & (1 << MCID::Barrier);
245 /// \brief Returns true if this instruction part of the terminator for
246 /// a basic block. Typically this is things like return and branch
249 /// Various passes use this to insert code into the bottom of a basic block,
250 /// but before control flow occurs.
251 bool isTerminator() const {
252 return Flags & (1 << MCID::Terminator);
255 /// \brief Returns true if this is a conditional, unconditional, or
256 /// indirect branch. Predicates below can be used to discriminate between
257 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
258 /// get more information.
259 bool isBranch() const {
260 return Flags & (1 << MCID::Branch);
263 /// \brief Return true if this is an indirect branch, such as a
264 /// branch through a register.
265 bool isIndirectBranch() const {
266 return Flags & (1 << MCID::IndirectBranch);
269 /// \brief Return true if this is a branch which may fall
270 /// through to the next instruction or may transfer control flow to some other
271 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
272 /// information about this branch.
273 bool isConditionalBranch() const {
274 return isBranch() & !isBarrier() & !isIndirectBranch();
277 /// \brief Return true if this is a branch which always
278 /// transfers control flow to some other block. The
279 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
280 /// about this branch.
281 bool isUnconditionalBranch() const {
282 return isBranch() & isBarrier() & !isIndirectBranch();
285 /// \brief Return true if this is a branch or an instruction which directly
286 /// writes to the program counter. Considered 'may' affect rather than
287 /// 'does' affect as things like predication are not taken into account.
288 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const {
289 if (isBranch() || isCall() || isReturn() || isIndirectBranch())
291 unsigned PC = RI.getProgramCounter();
294 if (hasDefOfPhysReg(MI, PC, RI))
296 // A variadic instruction may define PC in the variable operand list.
297 // There's currently no indication of which entries in a variable
298 // list are defs and which are uses. While that's the case, this function
299 // needs to assume they're defs in order to be conservatively correct.
300 for (int i = NumOperands, e = MI.getNumOperands(); i != e; ++i) {
301 if (MI.getOperand(i).isReg() &&
302 RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
308 /// \brief Return true if this instruction has a predicate operand
309 /// that controls execution. It may be set to 'always', or may be set to other
310 /// values. There are various methods in TargetInstrInfo that can be used to
311 /// control and modify the predicate in this instruction.
312 bool isPredicable() const {
313 return Flags & (1 << MCID::Predicable);
316 /// \brief Return true if this instruction is a comparison.
317 bool isCompare() const {
318 return Flags & (1 << MCID::Compare);
321 /// \brief Return true if this instruction is a move immediate
322 /// (including conditional moves) instruction.
323 bool isMoveImmediate() const {
324 return Flags & (1 << MCID::MoveImm);
327 /// \brief Return true if this instruction is a bitcast instruction.
328 bool isBitcast() const {
329 return Flags & (1 << MCID::Bitcast);
332 /// \brief Return true if this is a select instruction.
333 bool isSelect() const {
334 return Flags & (1 << MCID::Select);
337 /// \brief Return true if this instruction cannot be safely
338 /// duplicated. For example, if the instruction has a unique labels attached
339 /// to it, duplicating it would cause multiple definition errors.
340 bool isNotDuplicable() const {
341 return Flags & (1 << MCID::NotDuplicable);
344 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
345 /// which must be filled by the code generator.
346 bool hasDelaySlot() const {
347 return Flags & (1 << MCID::DelaySlot);
350 /// canFoldAsLoad - Return true for instructions that can be folded as
351 /// memory operands in other instructions. The most common use for this
352 /// is instructions that are simple loads from memory that don't modify
353 /// the loaded value in any way, but it can also be used for instructions
354 /// that can be expressed as constant-pool loads, such as V_SETALLONES
355 /// on x86, to allow them to be folded when it is beneficial.
356 /// This should only be set on instructions that return a value in their
357 /// only virtual register definition.
358 bool canFoldAsLoad() const {
359 return Flags & (1 << MCID::FoldableAsLoad);
362 /// \brief Return true if this instruction behaves
363 /// the same way as the generic REG_SEQUENCE instructions.
365 /// dX VMOVDRR rY, rZ
367 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
369 /// Note that for the optimizers to be able to take advantage of
370 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
371 /// override accordingly.
372 bool isRegSequenceLike() const { return Flags & (1 << MCID::RegSequence); }
374 /// \brief Return true if this instruction behaves
375 /// the same way as the generic EXTRACT_SUBREG instructions.
377 /// rX, rY VMOVRRD dZ
378 /// is equivalent to two EXTRACT_SUBREG:
379 /// rX = EXTRACT_SUBREG dZ, ssub_0
380 /// rY = EXTRACT_SUBREG dZ, ssub_1
382 /// Note that for the optimizers to be able to take advantage of
383 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
384 /// override accordingly.
385 bool isExtractSubregLike() const {
386 return Flags & (1 << MCID::ExtractSubreg);
389 //===--------------------------------------------------------------------===//
390 // Side Effect Analysis
391 //===--------------------------------------------------------------------===//
393 /// \brief Return true if this instruction could possibly read memory.
394 /// Instructions with this flag set are not necessarily simple load
395 /// instructions, they may load a value and modify it, for example.
396 bool mayLoad() const {
397 return Flags & (1 << MCID::MayLoad);
401 /// \brief Return true if this instruction could possibly modify memory.
402 /// Instructions with this flag set are not necessarily simple store
403 /// instructions, they may store a modified value based on their operands, or
404 /// may not actually modify anything, for example.
405 bool mayStore() const {
406 return Flags & (1 << MCID::MayStore);
409 /// hasUnmodeledSideEffects - Return true if this instruction has side
410 /// effects that are not modeled by other flags. This does not return true
411 /// for instructions whose effects are captured by:
413 /// 1. Their operand list and implicit definition/use list. Register use/def
414 /// info is explicit for instructions.
415 /// 2. Memory accesses. Use mayLoad/mayStore.
416 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
418 /// Examples of side effects would be modifying 'invisible' machine state like
419 /// a control register, flushing a cache, modifying a register invisible to
422 bool hasUnmodeledSideEffects() const {
423 return Flags & (1 << MCID::UnmodeledSideEffects);
426 //===--------------------------------------------------------------------===//
427 // Flags that indicate whether an instruction can be modified by a method.
428 //===--------------------------------------------------------------------===//
430 /// isCommutable - Return true if this may be a 2- or 3-address
431 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
432 /// result if Y and Z are exchanged. If this flag is set, then the
433 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
436 /// Note that this flag may be set on instructions that are only commutable
437 /// sometimes. In these cases, the call to commuteInstruction will fail.
438 /// Also note that some instructions require non-trivial modification to
440 bool isCommutable() const {
441 return Flags & (1 << MCID::Commutable);
444 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
445 /// which can be changed into a 3-address instruction if needed. Doing this
446 /// transformation can be profitable in the register allocator, because it
447 /// means that the instruction can use a 2-address form if possible, but
448 /// degrade into a less efficient form if the source and dest register cannot
449 /// be assigned to the same register. For example, this allows the x86
450 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
451 /// is the same speed as the shift but has bigger code size.
453 /// If this returns true, then the target must implement the
454 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
455 /// is allowed to fail if the transformation isn't valid for this specific
456 /// instruction (e.g. shl reg, 4 on x86).
458 bool isConvertibleTo3Addr() const {
459 return Flags & (1 << MCID::ConvertibleTo3Addr);
462 /// usesCustomInsertionHook - Return true if this instruction requires
463 /// custom insertion support when the DAG scheduler is inserting it into a
464 /// machine basic block. If this is true for the instruction, it basically
465 /// means that it is a pseudo instruction used at SelectionDAG time that is
466 /// expanded out into magic code by the target when MachineInstrs are formed.
468 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
469 /// is used to insert this into the MachineBasicBlock.
470 bool usesCustomInsertionHook() const {
471 return Flags & (1 << MCID::UsesCustomInserter);
474 /// hasPostISelHook - Return true if this instruction requires *adjustment*
475 /// after instruction selection by calling a target hook. For example, this
476 /// can be used to fill in ARM 's' optional operand depending on whether
477 /// the conditional flag register is used.
478 bool hasPostISelHook() const {
479 return Flags & (1 << MCID::HasPostISelHook);
482 /// isRematerializable - Returns true if this instruction is a candidate for
483 /// remat. This flag is only used in TargetInstrInfo method
484 /// isTriviallyRematerializable.
486 /// If this flag is set, the isReallyTriviallyReMaterializable()
487 /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
488 /// the instruction is really rematable.
489 bool isRematerializable() const {
490 return Flags & (1 << MCID::Rematerializable);
493 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
494 /// less) than a move instruction. This is useful during certain types of
495 /// optimizations (e.g., remat during two-address conversion or machine licm)
496 /// where we would like to remat or hoist the instruction, but not if it costs
497 /// more than moving the instruction into the appropriate register. Note, we
498 /// are not marking copies from and to the same register class with this flag.
500 /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
501 /// for different subtargets.
502 bool isAsCheapAsAMove() const {
503 return Flags & (1 << MCID::CheapAsAMove);
506 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
507 /// have special register allocation requirements that are not captured by the
508 /// operand register classes. e.g. ARM::STRD's two source registers must be an
509 /// even / odd pair, ARM::STM registers have to be in ascending order.
510 /// Post-register allocation passes should not attempt to change allocations
511 /// for sources of instructions with this flag.
512 bool hasExtraSrcRegAllocReq() const {
513 return Flags & (1 << MCID::ExtraSrcRegAllocReq);
516 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
517 /// have special register allocation requirements that are not captured by the
518 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
519 /// even / odd pair, ARM::LDM registers have to be in ascending order.
520 /// Post-register allocation passes should not attempt to change allocations
521 /// for definitions of instructions with this flag.
522 bool hasExtraDefRegAllocReq() const {
523 return Flags & (1 << MCID::ExtraDefRegAllocReq);
527 /// getImplicitUses - Return a list of registers that are potentially
528 /// read by any instance of this machine instruction. For example, on X86,
529 /// the "adc" instruction adds two register operands and adds the carry bit in
530 /// from the flags register. In this case, the instruction is marked as
531 /// implicitly reading the flags. Likewise, the variable shift instruction on
532 /// X86 is marked as implicitly reading the 'CL' register, which it always
535 /// This method returns null if the instruction has no implicit uses.
536 const uint16_t *getImplicitUses() const {
540 /// \brief Return the number of implicit uses this instruction has.
541 unsigned getNumImplicitUses() const {
542 if (!ImplicitUses) return 0;
544 for (; ImplicitUses[i]; ++i) /*empty*/;
548 /// getImplicitDefs - Return a list of registers that are potentially
549 /// written by any instance of this machine instruction. For example, on X86,
550 /// many instructions implicitly set the flags register. In this case, they
551 /// are marked as setting the FLAGS. Likewise, many instructions always
552 /// deposit their result in a physical register. For example, the X86 divide
553 /// instruction always deposits the quotient and remainder in the EAX/EDX
554 /// registers. For that instruction, this will return a list containing the
555 /// EAX/EDX/EFLAGS registers.
557 /// This method returns null if the instruction has no implicit defs.
558 const uint16_t *getImplicitDefs() const {
562 /// \brief Return the number of implicit defs this instruct has.
563 unsigned getNumImplicitDefs() const {
564 if (!ImplicitDefs) return 0;
566 for (; ImplicitDefs[i]; ++i) /*empty*/;
570 /// \brief Return true if this instruction implicitly
571 /// uses the specified physical register.
572 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
573 if (const uint16_t *ImpUses = ImplicitUses)
574 for (; *ImpUses; ++ImpUses)
575 if (*ImpUses == Reg) return true;
579 /// \brief Return true if this instruction implicitly
580 /// defines the specified physical register.
581 bool hasImplicitDefOfPhysReg(unsigned Reg,
582 const MCRegisterInfo *MRI = nullptr) const {
583 if (const uint16_t *ImpDefs = ImplicitDefs)
584 for (; *ImpDefs; ++ImpDefs)
585 if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
590 /// \brief Return true if this instruction defines the specified physical
591 /// register, either explicitly or implicitly.
592 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
593 const MCRegisterInfo &RI) const {
594 for (int i = 0, e = NumDefs; i != e; ++i)
595 if (MI.getOperand(i).isReg() &&
596 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
598 return hasImplicitDefOfPhysReg(Reg, &RI);
601 /// \brief Return the scheduling class for this instruction. The
602 /// scheduling class is an index into the InstrItineraryData table. This
603 /// returns zero if there is no known scheduling information for the
605 unsigned getSchedClass() const {
609 /// \brief Return the number of bytes in the encoding of this instruction,
610 /// or zero if the encoding size cannot be known from the opcode.
611 unsigned getSize() const {
615 /// \brief Find the index of the first operand in the
616 /// operand list that is used to represent the predicate. It returns -1 if
618 int findFirstPredOperandIdx() const {
619 if (isPredicable()) {
620 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
621 if (OpInfo[i].isPredicate())
628 } // end namespace llvm