1 //===- IntrinsicsX86.td - Defines X86 intrinsics -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines all of the X86-specific intrinsics.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
19 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
20 def int_x86_sse_add_ss : GCCBuiltin<"__builtin_ia32_addss">,
21 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
22 llvm_v4f32_ty], [IntrNoMem]>;
23 def int_x86_sse_sub_ss : GCCBuiltin<"__builtin_ia32_subss">,
24 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
25 llvm_v4f32_ty], [IntrNoMem]>;
26 def int_x86_sse_mul_ss : GCCBuiltin<"__builtin_ia32_mulss">,
27 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
28 llvm_v4f32_ty], [IntrNoMem]>;
29 def int_x86_sse_div_ss : GCCBuiltin<"__builtin_ia32_divss">,
30 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
31 llvm_v4f32_ty], [IntrNoMem]>;
32 def int_x86_sse_sqrt_ss : GCCBuiltin<"__builtin_ia32_sqrtss">,
33 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
35 def int_x86_sse_sqrt_ps : GCCBuiltin<"__builtin_ia32_sqrtps">,
36 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
38 def int_x86_sse_rcp_ss : GCCBuiltin<"__builtin_ia32_rcpss">,
39 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
41 def int_x86_sse_rcp_ps : GCCBuiltin<"__builtin_ia32_rcpps">,
42 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
44 def int_x86_sse_rsqrt_ss : GCCBuiltin<"__builtin_ia32_rsqrtss">,
45 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
47 def int_x86_sse_rsqrt_ps : GCCBuiltin<"__builtin_ia32_rsqrtps">,
48 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty],
50 def int_x86_sse_min_ss : GCCBuiltin<"__builtin_ia32_minss">,
51 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
52 llvm_v4f32_ty], [IntrNoMem]>;
53 def int_x86_sse_min_ps : GCCBuiltin<"__builtin_ia32_minps">,
54 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
55 llvm_v4f32_ty], [IntrNoMem]>;
56 def int_x86_sse_max_ss : GCCBuiltin<"__builtin_ia32_maxss">,
57 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
58 llvm_v4f32_ty], [IntrNoMem]>;
59 def int_x86_sse_max_ps : GCCBuiltin<"__builtin_ia32_maxps">,
60 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
61 llvm_v4f32_ty], [IntrNoMem]>;
65 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
66 def int_x86_sse_cmp_ss :
67 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
68 llvm_v4f32_ty, llvm_sbyte_ty], [IntrNoMem]>;
69 def int_x86_sse_cmp_ps :
70 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
71 llvm_v4f32_ty, llvm_sbyte_ty], [IntrNoMem]>;
72 def int_x86_sse_comieq_ss : GCCBuiltin<"__builtin_ia32_comieq">,
73 Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
74 llvm_v4f32_ty], [IntrNoMem]>;
75 def int_x86_sse_comilt_ss : GCCBuiltin<"__builtin_ia32_comilt">,
76 Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
77 llvm_v4f32_ty], [IntrNoMem]>;
78 def int_x86_sse_comile_ss : GCCBuiltin<"__builtin_ia32_comile">,
79 Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
80 llvm_v4f32_ty], [IntrNoMem]>;
81 def int_x86_sse_comigt_ss : GCCBuiltin<"__builtin_ia32_comigt">,
82 Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
83 llvm_v4f32_ty], [IntrNoMem]>;
84 def int_x86_sse_comige_ss : GCCBuiltin<"__builtin_ia32_comige">,
85 Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
86 llvm_v4f32_ty], [IntrNoMem]>;
87 def int_x86_sse_comineq_ss : GCCBuiltin<"__builtin_ia32_comineq">,
88 Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
89 llvm_v4f32_ty], [IntrNoMem]>;
90 def int_x86_sse_ucomieq_ss : GCCBuiltin<"__builtin_ia32_ucomieq">,
91 Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
92 llvm_v4f32_ty], [IntrNoMem]>;
93 def int_x86_sse_ucomilt_ss : GCCBuiltin<"__builtin_ia32_ucomilt">,
94 Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
95 llvm_v4f32_ty], [IntrNoMem]>;
96 def int_x86_sse_ucomile_ss : GCCBuiltin<"__builtin_ia32_ucomile">,
97 Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
98 llvm_v4f32_ty], [IntrNoMem]>;
99 def int_x86_sse_ucomigt_ss : GCCBuiltin<"__builtin_ia32_ucomigt">,
100 Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
101 llvm_v4f32_ty], [IntrNoMem]>;
102 def int_x86_sse_ucomige_ss : GCCBuiltin<"__builtin_ia32_ucomige">,
103 Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
104 llvm_v4f32_ty], [IntrNoMem]>;
105 def int_x86_sse_ucomineq_ss : GCCBuiltin<"__builtin_ia32_ucomineq">,
106 Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
107 llvm_v4f32_ty], [IntrNoMem]>;
112 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
113 def int_x86_sse_cvtss2si : GCCBuiltin<"__builtin_ia32_cvtss2si">,
114 Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [IntrNoMem]>;
115 def int_x86_sse_cvtps2pi : GCCBuiltin<"__builtin_ia32_cvtps2pi">,
116 Intrinsic<[llvm_v2i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
117 def int_x86_sse_cvttss2si : GCCBuiltin<"__builtin_ia32_cvttss2si">,
118 Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [IntrNoMem]>;
119 def int_x86_sse_cvttps2pi : GCCBuiltin<"__builtin_ia32_cvttps2pi">,
120 Intrinsic<[llvm_v2i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
121 def int_x86_sse_cvtsi2ss : GCCBuiltin<"__builtin_ia32_cvtsi2ss">,
122 Intrinsic<[llvm_v4f32_ty, llvm_int_ty], [IntrNoMem]>;
123 def int_x86_sse_cvtpi2ps : GCCBuiltin<"__builtin_ia32_cvtpi2ps">,
124 Intrinsic<[llvm_v4f32_ty, llvm_v2i32_ty], [IntrNoMem]>;
128 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
129 def int_x86_sse_loadu_ps : GCCBuiltin<"__builtin_ia32_loadups">,
130 Intrinsic<[llvm_v4f32_ty, llvm_ptr_ty], [IntrReadMem]>;
134 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
135 def int_x86_sse_storeu_ps : GCCBuiltin<"__builtin_ia32_storeups">,
136 Intrinsic<[llvm_void_ty, llvm_ptr_ty,
137 llvm_v4f32_ty], [IntrWriteMem]>;
140 // Cacheability support ops
141 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
142 def int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">,
143 Intrinsic<[llvm_void_ty, llvm_ptr_ty,
144 llvm_v4f32_ty], [IntrWriteMem]>;
145 def int_x86_sse_sfence : GCCBuiltin<"__builtin_ia32_sfence">,
146 Intrinsic<[llvm_void_ty], [IntrWriteMem]>;
150 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
151 def int_x86_sse_stmxcsr :
152 Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>;
153 def int_x86_sse_ldmxcsr :
154 Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>;
158 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
159 def int_x86_sse_movmsk_ps : GCCBuiltin<"__builtin_ia32_movmskps">,
160 Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [IntrNoMem]>;
163 //===----------------------------------------------------------------------===//
167 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
168 def int_x86_sse2_add_sd : GCCBuiltin<"__builtin_ia32_addsd">,
169 Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
170 llvm_v2f64_ty], [IntrNoMem]>;
171 def int_x86_sse2_sub_sd : GCCBuiltin<"__builtin_ia32_subsd">,
172 Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
173 llvm_v2f64_ty], [IntrNoMem]>;
174 def int_x86_sse2_mul_sd : GCCBuiltin<"__builtin_ia32_mulsd">,
175 Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
176 llvm_v2f64_ty], [IntrNoMem]>;
177 def int_x86_sse2_div_sd : GCCBuiltin<"__builtin_ia32_divsd">,
178 Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
179 llvm_v2f64_ty], [IntrNoMem]>;
180 def int_x86_sse2_sqrt_sd : GCCBuiltin<"__builtin_ia32_sqrtsd">,
181 Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty],
183 def int_x86_sse2_sqrt_pd : GCCBuiltin<"__builtin_ia32_sqrtpd">,
184 Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty],
186 def int_x86_sse2_rcp_sd : GCCBuiltin<"__builtin_ia32_rcpsd">,
187 Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty],
189 def int_x86_sse2_rcp_pd : GCCBuiltin<"__builtin_ia32_rcppd">,
190 Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty],
192 def int_x86_sse2_rsqrt_sd : GCCBuiltin<"__builtin_ia32_rsqrtsd">,
193 Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty],
195 def int_x86_sse2_rsqrt_pd : GCCBuiltin<"__builtin_ia32_rsqrtpd">,
196 Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty],
198 def int_x86_sse2_min_sd : GCCBuiltin<"__builtin_ia32_minsd">,
199 Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
200 llvm_v2f64_ty], [IntrNoMem]>;
201 def int_x86_sse2_min_pd : GCCBuiltin<"__builtin_ia32_minpd">,
202 Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
203 llvm_v2f64_ty], [IntrNoMem]>;
204 def int_x86_sse2_max_sd : GCCBuiltin<"__builtin_ia32_maxsd">,
205 Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
206 llvm_v2f64_ty], [IntrNoMem]>;
207 def int_x86_sse2_max_pd : GCCBuiltin<"__builtin_ia32_maxpd">,
208 Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
209 llvm_v2f64_ty], [IntrNoMem]>;
213 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
214 def int_x86_sse2_cmp_sd :
215 Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
216 llvm_v2f64_ty, llvm_sbyte_ty], [IntrNoMem]>;
217 def int_x86_sse2_cmp_pd :
218 Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
219 llvm_v2f64_ty, llvm_sbyte_ty], [IntrNoMem]>;
220 def int_x86_sse2_comieq_sd : GCCBuiltin<"__builtin_ia32_comisdeq">,
221 Intrinsic<[llvm_int_ty, llvm_v2f64_ty,
222 llvm_v2f64_ty], [IntrNoMem]>;
223 def int_x86_sse2_comilt_sd : GCCBuiltin<"__builtin_ia32_comisdlt">,
224 Intrinsic<[llvm_int_ty, llvm_v2f64_ty,
225 llvm_v2f64_ty], [IntrNoMem]>;
226 def int_x86_sse2_comile_sd : GCCBuiltin<"__builtin_ia32_comisdle">,
227 Intrinsic<[llvm_int_ty, llvm_v2f64_ty,
228 llvm_v2f64_ty], [IntrNoMem]>;
229 def int_x86_sse2_comigt_sd : GCCBuiltin<"__builtin_ia32_comisdgt">,
230 Intrinsic<[llvm_int_ty, llvm_v2f64_ty,
231 llvm_v2f64_ty], [IntrNoMem]>;
232 def int_x86_sse2_comige_sd : GCCBuiltin<"__builtin_ia32_comisdge">,
233 Intrinsic<[llvm_int_ty, llvm_v2f64_ty,
234 llvm_v2f64_ty], [IntrNoMem]>;
235 def int_x86_sse2_comineq_sd : GCCBuiltin<"__builtin_ia32_comisdneq">,
236 Intrinsic<[llvm_int_ty, llvm_v2f64_ty,
237 llvm_v2f64_ty], [IntrNoMem]>;
238 def int_x86_sse2_ucomieq_sd : GCCBuiltin<"__builtin_ia32_ucomisdeq">,
239 Intrinsic<[llvm_int_ty, llvm_v2f64_ty,
240 llvm_v2f64_ty], [IntrNoMem]>;
241 def int_x86_sse2_ucomilt_sd : GCCBuiltin<"__builtin_ia32_ucomisdlt">,
242 Intrinsic<[llvm_int_ty, llvm_v2f64_ty,
243 llvm_v2f64_ty], [IntrNoMem]>;
244 def int_x86_sse2_ucomile_sd : GCCBuiltin<"__builtin_ia32_ucomisdle">,
245 Intrinsic<[llvm_int_ty, llvm_v2f64_ty,
246 llvm_v2f64_ty], [IntrNoMem]>;
247 def int_x86_sse2_ucomigt_sd : GCCBuiltin<"__builtin_ia32_ucomisdgt">,
248 Intrinsic<[llvm_int_ty, llvm_v2f64_ty,
249 llvm_v2f64_ty], [IntrNoMem]>;
250 def int_x86_sse2_ucomige_sd : GCCBuiltin<"__builtin_ia32_ucomisdge">,
251 Intrinsic<[llvm_int_ty, llvm_v2f64_ty,
252 llvm_v2f64_ty], [IntrNoMem]>;
253 def int_x86_sse2_ucomineq_sd : GCCBuiltin<"__builtin_ia32_ucomisdneq">,
254 Intrinsic<[llvm_int_ty, llvm_v2f64_ty,
255 llvm_v2f64_ty], [IntrNoMem]>;
258 // Integer shift ops.
259 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
260 def int_x86_sse2_psll_dq : GCCBuiltin<"__builtin_ia32_pslldqi128">,
261 Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty,
262 llvm_int_ty], [IntrNoMem]>;
263 def int_x86_sse2_psrl_dq : GCCBuiltin<"__builtin_ia32_psrldqi128">,
264 Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty,
265 llvm_int_ty], [IntrNoMem]>;
269 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
270 def int_x86_sse2_loadu_pd : GCCBuiltin<"__builtin_ia32_loadupd">,
271 Intrinsic<[llvm_v2f64_ty, llvm_ptr_ty], [IntrReadMem]>;
272 def int_x86_sse2_loadu_dq : GCCBuiltin<"__builtin_ia32_loaddqu">,
273 Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [IntrReadMem]>;
277 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
278 def int_x86_sse2_storeu_pd : GCCBuiltin<"__builtin_ia32_storeupd">,
279 Intrinsic<[llvm_void_ty, llvm_ptr_ty,
280 llvm_v2f64_ty], [IntrWriteMem]>;
281 def int_x86_sse2_storeu_dq : GCCBuiltin<"__builtin_ia32_storedqu">,
282 Intrinsic<[llvm_void_ty, llvm_ptr_ty,
283 llvm_v16i8_ty], [IntrWriteMem]>;
284 def int_x86_sse2_storel_dq : GCCBuiltin<"__builtin_ia32_storelv4si">,
285 Intrinsic<[llvm_void_ty, llvm_ptr_ty,
286 llvm_v4i32_ty], [IntrWriteMem]>;
289 // Cacheability support ops
290 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
291 def int_x86_sse2_movnt_dq : GCCBuiltin<"__builtin_ia32_movntdq">,
292 Intrinsic<[llvm_void_ty, llvm_ptr_ty,
293 llvm_v2i64_ty], [IntrWriteMem]>;
294 def int_x86_sse2_movnt_pd : GCCBuiltin<"__builtin_ia32_movntpd">,
295 Intrinsic<[llvm_void_ty, llvm_ptr_ty,
296 llvm_v2f64_ty], [IntrWriteMem]>;
297 def int_x86_sse2_movnt_i : GCCBuiltin<"__builtin_ia32_movnti">,
298 Intrinsic<[llvm_void_ty, llvm_ptr_ty,
299 llvm_int_ty], [IntrWriteMem]>;
303 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
304 def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">,
305 Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
306 llvm_v8i16_ty], [IntrNoMem]>;
307 def int_x86_sse2_packssdw_128 : GCCBuiltin<"__builtin_ia32_packssdw128">,
308 Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty,
309 llvm_v4i32_ty], [IntrNoMem]>;
310 def int_x86_sse2_packuswb_128 : GCCBuiltin<"__builtin_ia32_packuswb128">,
311 Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
312 llvm_v8i16_ty], [IntrNoMem]>;
313 // FIXME: Temporary workaround since 2-wide shuffle is broken.
314 def int_x86_sse2_movl_dq : GCCBuiltin<"__builtin_ia32_movqv4si">,
315 Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
316 def int_x86_sse2_movmskpd : GCCBuiltin<"__builtin_ia32_movmskpd">,
317 Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [IntrNoMem]>;
318 def int_x86_sse2_pmovmskb_128 : GCCBuiltin<"__builtin_ia32_pmovmskb128">,
319 Intrinsic<[llvm_int_ty, llvm_v16i8_ty], [IntrNoMem]>;
320 def int_x86_sse2_maskmov_dqu : GCCBuiltin<"__builtin_ia32_maskmovdqu">,
321 Intrinsic<[llvm_void_ty, llvm_v16i8_ty,
322 llvm_v16i8_ty, llvm_ptr_ty], [IntrWriteMem]>;
325 //===----------------------------------------------------------------------===//
329 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
330 def int_x86_sse3_hadd_ps : GCCBuiltin<"__builtin_ia32_haddps">,
331 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
332 llvm_v4f32_ty], [IntrNoMem]>;
333 def int_x86_sse3_hadd_pd : GCCBuiltin<"__builtin_ia32_haddpd">,
334 Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
335 llvm_v2f64_ty], [IntrNoMem]>;
336 def int_x86_sse3_hsub_ps : GCCBuiltin<"__builtin_ia32_hsubps">,
337 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
338 llvm_v4f32_ty], [IntrNoMem]>;
339 def int_x86_sse3_hsub_pd : GCCBuiltin<"__builtin_ia32_hsubpd">,
340 Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
341 llvm_v2f64_ty], [IntrNoMem]>;