1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines all of the ARM-specific intrinsics.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
19 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
20 Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
23 //===----------------------------------------------------------------------===//
24 // Advanced SIMD (NEON)
26 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
28 // The following classes do not correspond directly to GCC builtins.
29 class Neon_1Arg_Intrinsic
30 : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
31 class Neon_1Arg_Float_Intrinsic
32 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
33 class Neon_1Arg_Narrow_Intrinsic
34 : Intrinsic<[llvm_anyint_ty],
35 [LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
36 class Neon_1Arg_Long_Intrinsic
37 : Intrinsic<[llvm_anyint_ty],
38 [LLVMTruncatedElementVectorType<0>], [IntrNoMem]>;
39 class Neon_2Arg_Intrinsic
40 : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
42 class Neon_2Arg_Float_Intrinsic
43 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
45 class Neon_2Arg_Vector_Intrinsic
46 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
48 class Neon_2Arg_Narrow_Intrinsic
49 : Intrinsic<[llvm_anyint_ty],
50 [LLVMExtendedElementVectorType<0>,
51 LLVMExtendedElementVectorType<0>],
53 class Neon_2Arg_Long_Intrinsic
54 : Intrinsic<[llvm_anyint_ty],
55 [LLVMTruncatedElementVectorType<0>,
56 LLVMTruncatedElementVectorType<0>],
58 class Neon_2Arg_Wide_Intrinsic
59 : Intrinsic<[llvm_anyint_ty],
60 [LLVMMatchType<0>, LLVMTruncatedElementVectorType<0>],
62 class Neon_3Arg_Intrinsic
63 : Intrinsic<[llvm_anyint_ty],
64 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
66 class Neon_3Arg_Long_Intrinsic
67 : Intrinsic<[llvm_anyint_ty],
69 LLVMTruncatedElementVectorType<0>,
70 LLVMTruncatedElementVectorType<0>],
72 class Neon_2Result_Intrinsic
73 : Intrinsic<[llvm_anyint_ty, LLVMMatchType<0>],
74 [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
75 class Neon_2Result_Float_Intrinsic
76 : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>],
77 [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
78 class Neon_CvtFxToFP_Intrinsic
79 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
80 class Neon_CvtFPToFx_Intrinsic
81 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
83 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
84 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
85 // Overall, the classes range from 2 to 6 v8i8 arguments.
86 class Neon_Tbl2Arg_Intrinsic
87 : Intrinsic<[llvm_v8i8_ty],
88 [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
89 class Neon_Tbl3Arg_Intrinsic
90 : Intrinsic<[llvm_v8i8_ty],
91 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
92 class Neon_Tbl4Arg_Intrinsic
93 : Intrinsic<[llvm_v8i8_ty],
94 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
96 class Neon_Tbl5Arg_Intrinsic
97 : Intrinsic<[llvm_v8i8_ty],
98 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
99 llvm_v8i8_ty], [IntrNoMem]>;
100 class Neon_Tbl6Arg_Intrinsic
101 : Intrinsic<[llvm_v8i8_ty],
102 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
103 llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
108 let Properties = [IntrNoMem, Commutative] in {
111 def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
112 def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
113 def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
114 def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
115 def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
116 def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
117 def int_arm_neon_vaddhn : Neon_2Arg_Narrow_Intrinsic;
118 def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
119 def int_arm_neon_vaddls : Neon_2Arg_Long_Intrinsic;
120 def int_arm_neon_vaddlu : Neon_2Arg_Long_Intrinsic;
121 def int_arm_neon_vaddws : Neon_2Arg_Wide_Intrinsic;
122 def int_arm_neon_vaddwu : Neon_2Arg_Wide_Intrinsic;
125 def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
126 def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
127 def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
128 def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
129 def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
130 def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
131 def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
133 // Vector Multiply and Accumulate/Subtract.
134 def int_arm_neon_vmlals : Neon_3Arg_Long_Intrinsic;
135 def int_arm_neon_vmlalu : Neon_3Arg_Long_Intrinsic;
136 def int_arm_neon_vmlsls : Neon_3Arg_Long_Intrinsic;
137 def int_arm_neon_vmlslu : Neon_3Arg_Long_Intrinsic;
138 def int_arm_neon_vqdmlal : Neon_3Arg_Long_Intrinsic;
139 def int_arm_neon_vqdmlsl : Neon_3Arg_Long_Intrinsic;
142 def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
143 def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
144 def int_arm_neon_vmaxf : Neon_2Arg_Float_Intrinsic;
147 def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
148 def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
149 def int_arm_neon_vminf : Neon_2Arg_Float_Intrinsic;
151 // Vector Reciprocal Step.
152 def int_arm_neon_vrecps : Neon_2Arg_Float_Intrinsic;
154 // Vector Reciprocal Square Root Step.
155 def int_arm_neon_vrsqrts : Neon_2Arg_Float_Intrinsic;
159 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
160 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
161 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
162 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
163 def int_arm_neon_vsubhn : Neon_2Arg_Narrow_Intrinsic;
164 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
165 def int_arm_neon_vsubls : Neon_2Arg_Long_Intrinsic;
166 def int_arm_neon_vsublu : Neon_2Arg_Long_Intrinsic;
167 def int_arm_neon_vsubws : Neon_2Arg_Wide_Intrinsic;
168 def int_arm_neon_vsubwu : Neon_2Arg_Wide_Intrinsic;
170 // Vector Absolute Compare.
171 let TargetPrefix = "arm" in {
172 def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
173 [llvm_v2f32_ty, llvm_v2f32_ty],
175 def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
176 [llvm_v4f32_ty, llvm_v4f32_ty],
178 def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
179 [llvm_v2f32_ty, llvm_v2f32_ty],
181 def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
182 [llvm_v4f32_ty, llvm_v4f32_ty],
186 // Vector Absolute Differences.
187 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
188 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
189 def int_arm_neon_vabdf : Neon_2Arg_Float_Intrinsic;
190 def int_arm_neon_vabdls : Neon_2Arg_Long_Intrinsic;
191 def int_arm_neon_vabdlu : Neon_2Arg_Long_Intrinsic;
193 // Vector Absolute Difference and Accumulate.
194 def int_arm_neon_vabas : Neon_3Arg_Intrinsic;
195 def int_arm_neon_vabau : Neon_3Arg_Intrinsic;
196 def int_arm_neon_vabals : Neon_3Arg_Long_Intrinsic;
197 def int_arm_neon_vabalu : Neon_3Arg_Long_Intrinsic;
199 // Vector Pairwise Add.
200 def int_arm_neon_vpadd : Neon_2Arg_Vector_Intrinsic;
202 // Vector Pairwise Add Long.
203 // Note: This is different than the other "long" NEON intrinsics because
204 // the result vector has half as many elements as the source vector.
205 // The source and destination vector types must be specified separately.
206 let TargetPrefix = "arm" in {
207 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty],
209 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty],
213 // Vector Pairwise Add and Accumulate Long.
214 // Note: This is similar to vpaddl but the destination vector also appears
215 // as the first argument.
216 let TargetPrefix = "arm" in {
217 def int_arm_neon_vpadals : Intrinsic<[llvm_anyint_ty],
218 [LLVMMatchType<0>, llvm_anyint_ty],
220 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyint_ty],
221 [LLVMMatchType<0>, llvm_anyint_ty],
225 // Vector Pairwise Maximum and Minimum.
226 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
227 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
228 def int_arm_neon_vpmaxf : Neon_2Arg_Float_Intrinsic;
229 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
230 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
231 def int_arm_neon_vpminf : Neon_2Arg_Float_Intrinsic;
235 // The various saturating and rounding vector shift operations need to be
236 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
237 // operation cannot be safely translated to LLVM's shift operators. VSHL can
238 // be used for both left and right shifts, or even combinations of the two,
239 // depending on the signs of the shift amounts. It also has well-defined
240 // behavior for shift amounts that LLVM leaves undefined. Only basic shifts
241 // by constants can be represented with LLVM's shift operators.
243 // The shift counts for these intrinsics are always vectors, even for constant
244 // shifts, where the constant is replicated. For consistency with VSHL (and
245 // other variable shift instructions), left shifts have positive shift counts
246 // and right shifts have negative shift counts. This convention is also used
247 // for constant right shift intrinsics, and to help preserve sanity, the
248 // intrinsic names use "shift" instead of either "shl" or "shr". Where
249 // applicable, signed and unsigned versions of the intrinsics are
250 // distinguished with "s" and "u" suffixes. A few NEON shift instructions,
251 // such as VQSHLU, take signed operands but produce unsigned results; these
252 // use a "su" suffix.
255 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
256 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
257 def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic;
258 def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic;
259 def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic;
261 // Vector Rounding Shift.
262 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
263 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
264 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
266 // Vector Saturating Shift.
267 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
268 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
269 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
270 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
271 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
272 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
274 // Vector Saturating Rounding Shift.
275 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
276 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
277 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
278 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
279 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
281 // Vector Shift and Insert.
282 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
284 // Vector Absolute Value and Saturating Absolute Value.
285 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
286 def int_arm_neon_vabsf : Neon_1Arg_Float_Intrinsic;
287 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
289 // Vector Saturating Negate.
290 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
292 // Vector Count Leading Sign/Zero Bits.
293 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
294 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
296 // Vector Count One Bits.
297 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
299 // Vector Reciprocal Estimate.
300 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
301 def int_arm_neon_vrecpef : Neon_1Arg_Float_Intrinsic;
303 // Vector Reciprocal Square Root Estimate.
304 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
305 def int_arm_neon_vrsqrtef : Neon_1Arg_Float_Intrinsic;
307 // Vector Conversions Between Floating-point and Fixed-point.
308 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
309 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
310 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
311 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
313 // Narrowing and Lengthening Vector Moves.
314 def int_arm_neon_vmovn : Neon_1Arg_Narrow_Intrinsic;
315 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
316 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
317 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
318 def int_arm_neon_vmovls : Neon_1Arg_Long_Intrinsic;
319 def int_arm_neon_vmovlu : Neon_1Arg_Long_Intrinsic;
321 // Vector Table Lookup.
322 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
323 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
324 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
325 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
327 // Vector Table Extension.
328 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
329 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
330 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
331 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
334 def int_arm_neon_vtrni : Neon_2Result_Intrinsic;
335 def int_arm_neon_vtrnf : Neon_2Result_Float_Intrinsic;
337 // Vector Interleave (vzip).
338 def int_arm_neon_vzipi : Neon_2Result_Intrinsic;
339 def int_arm_neon_vzipf : Neon_2Result_Float_Intrinsic;
341 // Vector Deinterleave (vuzp).
342 def int_arm_neon_vuzpi : Neon_2Result_Intrinsic;
343 def int_arm_neon_vuzpf : Neon_2Result_Float_Intrinsic;
345 let TargetPrefix = "arm" in {
347 // De-interleaving vector loads from N-element structures.
348 def int_arm_neon_vld1i : Intrinsic<[llvm_anyint_ty],
349 [llvm_ptr_ty], [IntrReadArgMem]>;
350 def int_arm_neon_vld1f : Intrinsic<[llvm_anyfloat_ty],
351 [llvm_ptr_ty], [IntrReadArgMem]>;
352 def int_arm_neon_vld2i : Intrinsic<[llvm_anyint_ty, LLVMMatchType<0>],
353 [llvm_ptr_ty], [IntrReadArgMem]>;
354 def int_arm_neon_vld2f : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>],
355 [llvm_ptr_ty], [IntrReadArgMem]>;
356 def int_arm_neon_vld3i : Intrinsic<[llvm_anyint_ty, LLVMMatchType<0>,
358 [llvm_ptr_ty], [IntrReadArgMem]>;
359 def int_arm_neon_vld3f : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>,
361 [llvm_ptr_ty], [IntrReadArgMem]>;
362 def int_arm_neon_vld4i : Intrinsic<[llvm_anyint_ty, LLVMMatchType<0>,
363 LLVMMatchType<0>, LLVMMatchType<0>],
364 [llvm_ptr_ty], [IntrReadArgMem]>;
365 def int_arm_neon_vld4f : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>,
366 LLVMMatchType<0>, LLVMMatchType<0>],
367 [llvm_ptr_ty], [IntrReadArgMem]>;
369 // Interleaving vector stores from N-element structures.
370 def int_arm_neon_vst1i : Intrinsic<[llvm_void_ty],
371 [llvm_ptr_ty, llvm_anyint_ty],
373 def int_arm_neon_vst1f : Intrinsic<[llvm_void_ty],
374 [llvm_ptr_ty, llvm_anyfloat_ty],
376 def int_arm_neon_vst2i : Intrinsic<[llvm_void_ty],
377 [llvm_ptr_ty, llvm_anyint_ty,
378 LLVMMatchType<0>], [IntrWriteArgMem]>;
379 def int_arm_neon_vst2f : Intrinsic<[llvm_void_ty],
380 [llvm_ptr_ty, llvm_anyfloat_ty,
381 LLVMMatchType<0>], [IntrWriteArgMem]>;
382 def int_arm_neon_vst3i : Intrinsic<[llvm_void_ty],
383 [llvm_ptr_ty, llvm_anyint_ty,
384 LLVMMatchType<0>, LLVMMatchType<0>],
386 def int_arm_neon_vst3f : Intrinsic<[llvm_void_ty],
387 [llvm_ptr_ty, llvm_anyfloat_ty,
388 LLVMMatchType<0>, LLVMMatchType<0>],
390 def int_arm_neon_vst4i : Intrinsic<[llvm_void_ty],
391 [llvm_ptr_ty, llvm_anyint_ty,
392 LLVMMatchType<0>, LLVMMatchType<0>,
393 LLVMMatchType<0>], [IntrWriteArgMem]>;
394 def int_arm_neon_vst4f : Intrinsic<[llvm_void_ty],
395 [llvm_ptr_ty, llvm_anyfloat_ty,
396 LLVMMatchType<0>, LLVMMatchType<0>,
397 LLVMMatchType<0>], [IntrWriteArgMem]>;