1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines all of the ARM-specific intrinsics.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
19 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
20 Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
23 //===----------------------------------------------------------------------===//
24 // Advanced SIMD (NEON)
26 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
28 // The following classes do not correspond directly to GCC builtins.
29 class Neon_1Arg_Intrinsic
30 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
31 class Neon_1Arg_Narrow_Intrinsic
32 : Intrinsic<[llvm_anyvector_ty],
33 [LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
34 class Neon_1Arg_Long_Intrinsic
35 : Intrinsic<[llvm_anyvector_ty],
36 [LLVMTruncatedElementVectorType<0>], [IntrNoMem]>;
37 class Neon_2Arg_Intrinsic
38 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
40 class Neon_2Arg_Narrow_Intrinsic
41 : Intrinsic<[llvm_anyvector_ty],
42 [LLVMExtendedElementVectorType<0>,
43 LLVMExtendedElementVectorType<0>],
45 class Neon_2Arg_Long_Intrinsic
46 : Intrinsic<[llvm_anyvector_ty],
47 [LLVMTruncatedElementVectorType<0>,
48 LLVMTruncatedElementVectorType<0>],
50 class Neon_2Arg_Wide_Intrinsic
51 : Intrinsic<[llvm_anyvector_ty],
52 [LLVMMatchType<0>, LLVMTruncatedElementVectorType<0>],
54 class Neon_3Arg_Intrinsic
55 : Intrinsic<[llvm_anyvector_ty],
56 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
58 class Neon_3Arg_Long_Intrinsic
59 : Intrinsic<[llvm_anyvector_ty],
61 LLVMTruncatedElementVectorType<0>,
62 LLVMTruncatedElementVectorType<0>],
64 class Neon_2Result_Intrinsic
65 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
66 [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
67 class Neon_CvtFxToFP_Intrinsic
68 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
69 class Neon_CvtFPToFx_Intrinsic
70 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
72 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
73 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
74 // Overall, the classes range from 2 to 6 v8i8 arguments.
75 class Neon_Tbl2Arg_Intrinsic
76 : Intrinsic<[llvm_v8i8_ty],
77 [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
78 class Neon_Tbl3Arg_Intrinsic
79 : Intrinsic<[llvm_v8i8_ty],
80 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
81 class Neon_Tbl4Arg_Intrinsic
82 : Intrinsic<[llvm_v8i8_ty],
83 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
85 class Neon_Tbl5Arg_Intrinsic
86 : Intrinsic<[llvm_v8i8_ty],
87 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
88 llvm_v8i8_ty], [IntrNoMem]>;
89 class Neon_Tbl6Arg_Intrinsic
90 : Intrinsic<[llvm_v8i8_ty],
91 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
92 llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
97 let Properties = [IntrNoMem, Commutative] in {
100 def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
101 def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
102 def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
103 def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
104 def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
105 def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
106 def int_arm_neon_vaddhn : Neon_2Arg_Narrow_Intrinsic;
107 def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
108 def int_arm_neon_vaddls : Neon_2Arg_Long_Intrinsic;
109 def int_arm_neon_vaddlu : Neon_2Arg_Long_Intrinsic;
110 def int_arm_neon_vaddws : Neon_2Arg_Wide_Intrinsic;
111 def int_arm_neon_vaddwu : Neon_2Arg_Wide_Intrinsic;
114 def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
115 def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
116 def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
117 def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
118 def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
119 def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
120 def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
122 // Vector Multiply and Accumulate/Subtract.
123 def int_arm_neon_vmlals : Neon_3Arg_Long_Intrinsic;
124 def int_arm_neon_vmlalu : Neon_3Arg_Long_Intrinsic;
125 def int_arm_neon_vmlsls : Neon_3Arg_Long_Intrinsic;
126 def int_arm_neon_vmlslu : Neon_3Arg_Long_Intrinsic;
127 def int_arm_neon_vqdmlal : Neon_3Arg_Long_Intrinsic;
128 def int_arm_neon_vqdmlsl : Neon_3Arg_Long_Intrinsic;
131 def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
132 def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
135 def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
136 def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
138 // Vector Reciprocal Step.
139 def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
141 // Vector Reciprocal Square Root Step.
142 def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
146 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
147 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
148 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
149 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
150 def int_arm_neon_vsubhn : Neon_2Arg_Narrow_Intrinsic;
151 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
152 def int_arm_neon_vsubls : Neon_2Arg_Long_Intrinsic;
153 def int_arm_neon_vsublu : Neon_2Arg_Long_Intrinsic;
154 def int_arm_neon_vsubws : Neon_2Arg_Wide_Intrinsic;
155 def int_arm_neon_vsubwu : Neon_2Arg_Wide_Intrinsic;
157 // Vector Absolute Compare.
158 let TargetPrefix = "arm" in {
159 def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
160 [llvm_v2f32_ty, llvm_v2f32_ty],
162 def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
163 [llvm_v4f32_ty, llvm_v4f32_ty],
165 def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
166 [llvm_v2f32_ty, llvm_v2f32_ty],
168 def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
169 [llvm_v4f32_ty, llvm_v4f32_ty],
173 // Vector Absolute Differences.
174 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
175 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
176 def int_arm_neon_vabdls : Neon_2Arg_Long_Intrinsic;
177 def int_arm_neon_vabdlu : Neon_2Arg_Long_Intrinsic;
179 // Vector Absolute Difference and Accumulate.
180 def int_arm_neon_vabas : Neon_3Arg_Intrinsic;
181 def int_arm_neon_vabau : Neon_3Arg_Intrinsic;
182 def int_arm_neon_vabals : Neon_3Arg_Long_Intrinsic;
183 def int_arm_neon_vabalu : Neon_3Arg_Long_Intrinsic;
185 // Vector Pairwise Add.
186 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
188 // Vector Pairwise Add Long.
189 // Note: This is different than the other "long" NEON intrinsics because
190 // the result vector has half as many elements as the source vector.
191 // The source and destination vector types must be specified separately.
192 let TargetPrefix = "arm" in {
193 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
195 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
199 // Vector Pairwise Add and Accumulate Long.
200 // Note: This is similar to vpaddl but the destination vector also appears
201 // as the first argument.
202 let TargetPrefix = "arm" in {
203 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
204 [LLVMMatchType<0>, llvm_anyvector_ty],
206 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
207 [LLVMMatchType<0>, llvm_anyvector_ty],
211 // Vector Pairwise Maximum and Minimum.
212 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
213 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
214 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
215 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
219 // The various saturating and rounding vector shift operations need to be
220 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
221 // operation cannot be safely translated to LLVM's shift operators. VSHL can
222 // be used for both left and right shifts, or even combinations of the two,
223 // depending on the signs of the shift amounts. It also has well-defined
224 // behavior for shift amounts that LLVM leaves undefined. Only basic shifts
225 // by constants can be represented with LLVM's shift operators.
227 // The shift counts for these intrinsics are always vectors, even for constant
228 // shifts, where the constant is replicated. For consistency with VSHL (and
229 // other variable shift instructions), left shifts have positive shift counts
230 // and right shifts have negative shift counts. This convention is also used
231 // for constant right shift intrinsics, and to help preserve sanity, the
232 // intrinsic names use "shift" instead of either "shl" or "shr". Where
233 // applicable, signed and unsigned versions of the intrinsics are
234 // distinguished with "s" and "u" suffixes. A few NEON shift instructions,
235 // such as VQSHLU, take signed operands but produce unsigned results; these
236 // use a "su" suffix.
239 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
240 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
241 def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic;
242 def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic;
243 def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic;
245 // Vector Rounding Shift.
246 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
247 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
248 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
250 // Vector Saturating Shift.
251 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
252 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
253 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
254 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
255 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
256 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
258 // Vector Saturating Rounding Shift.
259 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
260 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
261 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
262 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
263 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
265 // Vector Shift and Insert.
266 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
268 // Vector Absolute Value and Saturating Absolute Value.
269 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
270 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
272 // Vector Saturating Negate.
273 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
275 // Vector Count Leading Sign/Zero Bits.
276 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
277 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
279 // Vector Count One Bits.
280 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
282 // Vector Reciprocal Estimate.
283 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
285 // Vector Reciprocal Square Root Estimate.
286 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
288 // Vector Conversions Between Floating-point and Fixed-point.
289 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
290 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
291 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
292 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
294 // Narrowing and Lengthening Vector Moves.
295 def int_arm_neon_vmovn : Neon_1Arg_Narrow_Intrinsic;
296 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
297 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
298 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
299 def int_arm_neon_vmovls : Neon_1Arg_Long_Intrinsic;
300 def int_arm_neon_vmovlu : Neon_1Arg_Long_Intrinsic;
302 // Vector Table Lookup.
303 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
304 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
305 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
306 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
308 // Vector Table Extension.
309 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
310 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
311 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
312 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
315 def int_arm_neon_vtrn : Neon_2Result_Intrinsic;
317 // Vector Interleave (vzip).
318 def int_arm_neon_vzip : Neon_2Result_Intrinsic;
320 // Vector Deinterleave (vuzp).
321 def int_arm_neon_vuzp : Neon_2Result_Intrinsic;
323 let TargetPrefix = "arm" in {
325 // De-interleaving vector loads from N-element structures.
326 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
327 [llvm_ptr_ty], [IntrReadArgMem]>;
328 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
329 [llvm_ptr_ty], [IntrReadArgMem]>;
330 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
332 [llvm_ptr_ty], [IntrReadArgMem]>;
333 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
334 LLVMMatchType<0>, LLVMMatchType<0>],
335 [llvm_ptr_ty], [IntrReadArgMem]>;
337 // Interleaving vector stores from N-element structures.
338 def int_arm_neon_vst1 : Intrinsic<[llvm_void_ty],
339 [llvm_ptr_ty, llvm_anyvector_ty],
341 def int_arm_neon_vst2 : Intrinsic<[llvm_void_ty],
342 [llvm_ptr_ty, llvm_anyvector_ty,
343 LLVMMatchType<0>], [IntrWriteArgMem]>;
344 def int_arm_neon_vst3 : Intrinsic<[llvm_void_ty],
345 [llvm_ptr_ty, llvm_anyvector_ty,
346 LLVMMatchType<0>, LLVMMatchType<0>],
348 def int_arm_neon_vst4 : Intrinsic<[llvm_void_ty],
349 [llvm_ptr_ty, llvm_anyvector_ty,
350 LLVMMatchType<0>, LLVMMatchType<0>,
351 LLVMMatchType<0>], [IntrWriteArgMem]>;