1 //===- IntrinsicsARM64.td - Defines ARM64 intrinsics -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines all of the ARM64-specific intrinsics.
12 //===----------------------------------------------------------------------===//
14 let TargetPrefix = "arm64" in {
16 def int_arm64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
17 def int_arm64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
18 def int_arm64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
19 def int_arm64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
21 def int_arm64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
22 def int_arm64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
23 def int_arm64_stxp : Intrinsic<[llvm_i32_ty],
24 [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>;
25 def int_arm64_stlxp : Intrinsic<[llvm_i32_ty],
26 [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>;
28 def int_arm64_clrex : Intrinsic<[]>;
30 def int_arm64_sdiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
31 LLVMMatchType<0>], [IntrNoMem]>;
32 def int_arm64_udiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
33 LLVMMatchType<0>], [IntrNoMem]>;
36 //===----------------------------------------------------------------------===//
37 // Advanced SIMD (NEON)
39 let TargetPrefix = "arm64" in { // All intrinsics start with "llvm.arm64.".
40 class AdvSIMD_2Scalar_Float_Intrinsic
41 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
44 class AdvSIMD_FPToIntRounding_Intrinsic
45 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
47 class AdvSIMD_1IntArg_Intrinsic
48 : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
49 class AdvSIMD_1FloatArg_Intrinsic
50 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
51 class AdvSIMD_1VectorArg_Intrinsic
52 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
53 class AdvSIMD_1VectorArg_Expand_Intrinsic
54 : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
55 class AdvSIMD_1VectorArg_Long_Intrinsic
56 : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>], [IntrNoMem]>;
57 class AdvSIMD_1IntArg_Narrow_Intrinsic
58 : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrNoMem]>;
59 class AdvSIMD_1VectorArg_Narrow_Intrinsic
60 : Intrinsic<[llvm_anyint_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
61 class AdvSIMD_1VectorArg_Int_Across_Intrinsic
62 : Intrinsic<[llvm_anyint_ty], [llvm_anyvector_ty], [IntrNoMem]>;
63 class AdvSIMD_1VectorArg_Float_Across_Intrinsic
64 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>;
66 class AdvSIMD_2IntArg_Intrinsic
67 : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
69 class AdvSIMD_2FloatArg_Intrinsic
70 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
72 class AdvSIMD_2VectorArg_Intrinsic
73 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
75 class AdvSIMD_2VectorArg_Compare_Intrinsic
76 : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
78 class AdvSIMD_2Arg_FloatCompare_Intrinsic
79 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, LLVMMatchType<1>],
81 class AdvSIMD_2VectorArg_Long_Intrinsic
82 : Intrinsic<[llvm_anyvector_ty],
83 [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
85 class AdvSIMD_2VectorArg_Wide_Intrinsic
86 : Intrinsic<[llvm_anyvector_ty],
87 [LLVMMatchType<0>, LLVMTruncatedType<0>],
89 class AdvSIMD_2VectorArg_Narrow_Intrinsic
90 : Intrinsic<[llvm_anyvector_ty],
91 [LLVMExtendedType<0>, LLVMExtendedType<0>],
93 class AdvSIMD_2Arg_Scalar_Narrow_Intrinsic
94 : Intrinsic<[llvm_anyint_ty],
95 [LLVMExtendedType<0>, llvm_i32_ty],
97 class AdvSIMD_2VectorArg_Scalar_Expand_BySize_Intrinsic
98 : Intrinsic<[llvm_anyvector_ty],
101 class AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic
102 : Intrinsic<[llvm_anyvector_ty],
103 [LLVMTruncatedType<0>],
105 class AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic
106 : Intrinsic<[llvm_anyvector_ty],
107 [LLVMTruncatedType<0>, llvm_i32_ty],
109 class AdvSIMD_2VectorArg_Tied_Narrow_Intrinsic
110 : Intrinsic<[llvm_anyvector_ty],
111 [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty],
114 class AdvSIMD_3VectorArg_Intrinsic
115 : Intrinsic<[llvm_anyvector_ty],
116 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
118 class AdvSIMD_3VectorArg_Scalar_Intrinsic
119 : Intrinsic<[llvm_anyvector_ty],
120 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
122 class AdvSIMD_3VectorArg_Tied_Narrow_Intrinsic
123 : Intrinsic<[llvm_anyvector_ty],
124 [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty,
125 LLVMMatchType<1>], [IntrNoMem]>;
126 class AdvSIMD_3VectorArg_Scalar_Tied_Narrow_Intrinsic
127 : Intrinsic<[llvm_anyvector_ty],
128 [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty, llvm_i32_ty],
130 class AdvSIMD_CvtFxToFP_Intrinsic
131 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty],
133 class AdvSIMD_CvtFPToFx_Intrinsic
134 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty],
140 let Properties = [IntrNoMem] in {
141 // Vector Add Across Lanes
142 def int_arm64_neon_saddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
143 def int_arm64_neon_uaddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
144 def int_arm64_neon_faddv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
146 // Vector Long Add Across Lanes
147 def int_arm64_neon_saddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
148 def int_arm64_neon_uaddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
150 // Vector Halving Add
151 def int_arm64_neon_shadd : AdvSIMD_2VectorArg_Intrinsic;
152 def int_arm64_neon_uhadd : AdvSIMD_2VectorArg_Intrinsic;
154 // Vector Rounding Halving Add
155 def int_arm64_neon_srhadd : AdvSIMD_2VectorArg_Intrinsic;
156 def int_arm64_neon_urhadd : AdvSIMD_2VectorArg_Intrinsic;
158 // Vector Saturating Add
159 def int_arm64_neon_sqadd : AdvSIMD_2IntArg_Intrinsic;
160 def int_arm64_neon_suqadd : AdvSIMD_2IntArg_Intrinsic;
161 def int_arm64_neon_usqadd : AdvSIMD_2IntArg_Intrinsic;
162 def int_arm64_neon_uqadd : AdvSIMD_2IntArg_Intrinsic;
164 // Vector Add High-Half
165 // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that
166 // header is no longer supported.
167 def int_arm64_neon_addhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
169 // Vector Rounding Add High-Half
170 def int_arm64_neon_raddhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
172 // Vector Saturating Doubling Multiply High
173 def int_arm64_neon_sqdmulh : AdvSIMD_2IntArg_Intrinsic;
175 // Vector Saturating Rounding Doubling Multiply High
176 def int_arm64_neon_sqrdmulh : AdvSIMD_2IntArg_Intrinsic;
178 // Vector Polynominal Multiply
179 def int_arm64_neon_pmul : AdvSIMD_2VectorArg_Intrinsic;
181 // Vector Long Multiply
182 def int_arm64_neon_smull : AdvSIMD_2VectorArg_Long_Intrinsic;
183 def int_arm64_neon_umull : AdvSIMD_2VectorArg_Long_Intrinsic;
184 def int_arm64_neon_pmull : AdvSIMD_2VectorArg_Long_Intrinsic;
186 // 64-bit polynomial multiply really returns an i128, which is not legal. Fake
188 def int_arm64_neon_pmull64 :
189 Intrinsic<[llvm_v16i8_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
191 // Vector Extending Multiply
192 def int_arm64_neon_fmulx : AdvSIMD_2FloatArg_Intrinsic {
193 let Properties = [IntrNoMem, Commutative];
196 // Vector Saturating Doubling Long Multiply
197 def int_arm64_neon_sqdmull : AdvSIMD_2VectorArg_Long_Intrinsic;
198 def int_arm64_neon_sqdmulls_scalar
199 : Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
201 // Vector Halving Subtract
202 def int_arm64_neon_shsub : AdvSIMD_2VectorArg_Intrinsic;
203 def int_arm64_neon_uhsub : AdvSIMD_2VectorArg_Intrinsic;
205 // Vector Saturating Subtract
206 def int_arm64_neon_sqsub : AdvSIMD_2IntArg_Intrinsic;
207 def int_arm64_neon_uqsub : AdvSIMD_2IntArg_Intrinsic;
209 // Vector Subtract High-Half
210 // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that
211 // header is no longer supported.
212 def int_arm64_neon_subhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
214 // Vector Rounding Subtract High-Half
215 def int_arm64_neon_rsubhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
217 // Vector Compare Absolute Greater-than-or-equal
218 def int_arm64_neon_facge : AdvSIMD_2Arg_FloatCompare_Intrinsic;
220 // Vector Compare Absolute Greater-than
221 def int_arm64_neon_facgt : AdvSIMD_2Arg_FloatCompare_Intrinsic;
223 // Vector Absolute Difference
224 def int_arm64_neon_sabd : AdvSIMD_2VectorArg_Intrinsic;
225 def int_arm64_neon_uabd : AdvSIMD_2VectorArg_Intrinsic;
226 def int_arm64_neon_fabd : AdvSIMD_2VectorArg_Intrinsic;
228 // Scalar Absolute Difference
229 def int_arm64_sisd_fabd : AdvSIMD_2Scalar_Float_Intrinsic;
232 def int_arm64_neon_smax : AdvSIMD_2VectorArg_Intrinsic;
233 def int_arm64_neon_umax : AdvSIMD_2VectorArg_Intrinsic;
234 def int_arm64_neon_fmax : AdvSIMD_2VectorArg_Intrinsic;
235 def int_arm64_neon_fmaxnmp : AdvSIMD_2VectorArg_Intrinsic;
237 // Vector Max Across Lanes
238 def int_arm64_neon_smaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
239 def int_arm64_neon_umaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
240 def int_arm64_neon_fmaxv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
241 def int_arm64_neon_fmaxnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
244 def int_arm64_neon_smin : AdvSIMD_2VectorArg_Intrinsic;
245 def int_arm64_neon_umin : AdvSIMD_2VectorArg_Intrinsic;
246 def int_arm64_neon_fmin : AdvSIMD_2VectorArg_Intrinsic;
247 def int_arm64_neon_fminnmp : AdvSIMD_2VectorArg_Intrinsic;
249 // Vector Min/Max Number
250 def int_arm64_neon_fminnm : AdvSIMD_2FloatArg_Intrinsic;
251 def int_arm64_neon_fmaxnm : AdvSIMD_2FloatArg_Intrinsic;
253 // Vector Min Across Lanes
254 def int_arm64_neon_sminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
255 def int_arm64_neon_uminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
256 def int_arm64_neon_fminv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
257 def int_arm64_neon_fminnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
260 def int_arm64_neon_addp : AdvSIMD_2VectorArg_Intrinsic;
263 // FIXME: In theory, we shouldn't need intrinsics for saddlp or
264 // uaddlp, but tblgen's type inference currently can't handle the
265 // pattern fragments this ends up generating.
266 def int_arm64_neon_saddlp : AdvSIMD_1VectorArg_Expand_Intrinsic;
267 def int_arm64_neon_uaddlp : AdvSIMD_1VectorArg_Expand_Intrinsic;
270 def int_arm64_neon_smaxp : AdvSIMD_2VectorArg_Intrinsic;
271 def int_arm64_neon_umaxp : AdvSIMD_2VectorArg_Intrinsic;
272 def int_arm64_neon_fmaxp : AdvSIMD_2VectorArg_Intrinsic;
275 def int_arm64_neon_sminp : AdvSIMD_2VectorArg_Intrinsic;
276 def int_arm64_neon_uminp : AdvSIMD_2VectorArg_Intrinsic;
277 def int_arm64_neon_fminp : AdvSIMD_2VectorArg_Intrinsic;
279 // Reciprocal Estimate/Step
280 def int_arm64_neon_frecps : AdvSIMD_2FloatArg_Intrinsic;
281 def int_arm64_neon_frsqrts : AdvSIMD_2FloatArg_Intrinsic;
283 // Reciprocal Exponent
284 def int_arm64_neon_frecpx : AdvSIMD_1FloatArg_Intrinsic;
286 // Vector Saturating Shift Left
287 def int_arm64_neon_sqshl : AdvSIMD_2IntArg_Intrinsic;
288 def int_arm64_neon_uqshl : AdvSIMD_2IntArg_Intrinsic;
290 // Vector Rounding Shift Left
291 def int_arm64_neon_srshl : AdvSIMD_2IntArg_Intrinsic;
292 def int_arm64_neon_urshl : AdvSIMD_2IntArg_Intrinsic;
294 // Vector Saturating Rounding Shift Left
295 def int_arm64_neon_sqrshl : AdvSIMD_2IntArg_Intrinsic;
296 def int_arm64_neon_uqrshl : AdvSIMD_2IntArg_Intrinsic;
298 // Vector Signed->Unsigned Shift Left by Constant
299 def int_arm64_neon_sqshlu : AdvSIMD_2IntArg_Intrinsic;
301 // Vector Signed->Unsigned Narrowing Saturating Shift Right by Constant
302 def int_arm64_neon_sqshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
304 // Vector Signed->Unsigned Rounding Narrowing Saturating Shift Right by Const
305 def int_arm64_neon_sqrshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
307 // Vector Narrowing Shift Right by Constant
308 def int_arm64_neon_sqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
309 def int_arm64_neon_uqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
311 // Vector Rounding Narrowing Shift Right by Constant
312 def int_arm64_neon_rshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
314 // Vector Rounding Narrowing Saturating Shift Right by Constant
315 def int_arm64_neon_sqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
316 def int_arm64_neon_uqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
319 def int_arm64_neon_sshl : AdvSIMD_2IntArg_Intrinsic;
320 def int_arm64_neon_ushl : AdvSIMD_2IntArg_Intrinsic;
322 // Vector Widening Shift Left by Constant
323 def int_arm64_neon_shll : AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic;
324 def int_arm64_neon_sshll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic;
325 def int_arm64_neon_ushll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic;
327 // Vector Shift Right by Constant and Insert
328 def int_arm64_neon_vsri : AdvSIMD_3VectorArg_Scalar_Intrinsic;
330 // Vector Shift Left by Constant and Insert
331 def int_arm64_neon_vsli : AdvSIMD_3VectorArg_Scalar_Intrinsic;
333 // Vector Saturating Narrow
334 def int_arm64_neon_scalar_sqxtn: AdvSIMD_1IntArg_Narrow_Intrinsic;
335 def int_arm64_neon_scalar_uqxtn : AdvSIMD_1IntArg_Narrow_Intrinsic;
336 def int_arm64_neon_sqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic;
337 def int_arm64_neon_uqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic;
339 // Vector Saturating Extract and Unsigned Narrow
340 def int_arm64_neon_scalar_sqxtun : AdvSIMD_1IntArg_Narrow_Intrinsic;
341 def int_arm64_neon_sqxtun : AdvSIMD_1VectorArg_Narrow_Intrinsic;
343 // Vector Absolute Value
344 def int_arm64_neon_abs : AdvSIMD_1IntArg_Intrinsic;
346 // Vector Saturating Absolute Value
347 def int_arm64_neon_sqabs : AdvSIMD_1IntArg_Intrinsic;
349 // Vector Saturating Negation
350 def int_arm64_neon_sqneg : AdvSIMD_1IntArg_Intrinsic;
352 // Vector Count Leading Sign Bits
353 def int_arm64_neon_cls : AdvSIMD_1VectorArg_Intrinsic;
355 // Vector Reciprocal Estimate
356 def int_arm64_neon_urecpe : AdvSIMD_1VectorArg_Intrinsic;
357 def int_arm64_neon_frecpe : AdvSIMD_1FloatArg_Intrinsic;
359 // Vector Square Root Estimate
360 def int_arm64_neon_ursqrte : AdvSIMD_1VectorArg_Intrinsic;
361 def int_arm64_neon_frsqrte : AdvSIMD_1FloatArg_Intrinsic;
363 // Vector Bitwise Reverse
364 def int_arm64_neon_rbit : AdvSIMD_1VectorArg_Intrinsic;
366 // Vector Conversions Between Half-Precision and Single-Precision.
367 def int_arm64_neon_vcvtfp2hf
368 : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
369 def int_arm64_neon_vcvthf2fp
370 : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
372 // Vector Conversions Between Floating-point and Fixed-point.
373 def int_arm64_neon_vcvtfp2fxs : AdvSIMD_CvtFPToFx_Intrinsic;
374 def int_arm64_neon_vcvtfp2fxu : AdvSIMD_CvtFPToFx_Intrinsic;
375 def int_arm64_neon_vcvtfxs2fp : AdvSIMD_CvtFxToFP_Intrinsic;
376 def int_arm64_neon_vcvtfxu2fp : AdvSIMD_CvtFxToFP_Intrinsic;
378 // Vector FP->Int Conversions
379 def int_arm64_neon_fcvtas : AdvSIMD_FPToIntRounding_Intrinsic;
380 def int_arm64_neon_fcvtau : AdvSIMD_FPToIntRounding_Intrinsic;
381 def int_arm64_neon_fcvtms : AdvSIMD_FPToIntRounding_Intrinsic;
382 def int_arm64_neon_fcvtmu : AdvSIMD_FPToIntRounding_Intrinsic;
383 def int_arm64_neon_fcvtns : AdvSIMD_FPToIntRounding_Intrinsic;
384 def int_arm64_neon_fcvtnu : AdvSIMD_FPToIntRounding_Intrinsic;
385 def int_arm64_neon_fcvtps : AdvSIMD_FPToIntRounding_Intrinsic;
386 def int_arm64_neon_fcvtpu : AdvSIMD_FPToIntRounding_Intrinsic;
387 def int_arm64_neon_fcvtzs : AdvSIMD_FPToIntRounding_Intrinsic;
388 def int_arm64_neon_fcvtzu : AdvSIMD_FPToIntRounding_Intrinsic;
390 // Vector FP Rounding: only ties to even is unrepresented by a normal
392 def int_arm64_neon_frintn : AdvSIMD_1FloatArg_Intrinsic;
394 // Scalar FP->Int conversions
396 // Vector FP Inexact Narrowing
397 def int_arm64_neon_fcvtxn : AdvSIMD_1VectorArg_Expand_Intrinsic;
399 // Scalar FP Inexact Narrowing
400 def int_arm64_sisd_fcvtxn : Intrinsic<[llvm_float_ty], [llvm_double_ty],
404 let TargetPrefix = "arm64" in { // All intrinsics start with "llvm.arm64.".
405 class AdvSIMD_2Vector2Index_Intrinsic
406 : Intrinsic<[llvm_anyvector_ty],
407 [llvm_anyvector_ty, llvm_i64_ty, LLVMMatchType<0>, llvm_i64_ty],
411 // Vector element to element moves
412 def int_arm64_neon_vcopy_lane: AdvSIMD_2Vector2Index_Intrinsic;
414 let TargetPrefix = "arm64" in { // All intrinsics start with "llvm.arm64.".
415 class AdvSIMD_1Vec_Load_Intrinsic
416 : Intrinsic<[llvm_anyvector_ty], [LLVMAnyPointerType<LLVMMatchType<0>>],
418 class AdvSIMD_1Vec_Store_Lane_Intrinsic
419 : Intrinsic<[], [llvm_anyvector_ty, llvm_i64_ty, llvm_anyptr_ty],
420 [IntrReadWriteArgMem, NoCapture<2>]>;
422 class AdvSIMD_2Vec_Load_Intrinsic
423 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
424 [LLVMAnyPointerType<LLVMMatchType<0>>],
426 class AdvSIMD_2Vec_Load_Lane_Intrinsic
427 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
428 [LLVMMatchType<0>, LLVMMatchType<0>,
429 llvm_i64_ty, llvm_anyptr_ty],
431 class AdvSIMD_2Vec_Store_Intrinsic
432 : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
433 LLVMAnyPointerType<LLVMMatchType<0>>],
434 [IntrReadWriteArgMem, NoCapture<2>]>;
435 class AdvSIMD_2Vec_Store_Lane_Intrinsic
436 : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
437 llvm_i64_ty, llvm_anyptr_ty],
438 [IntrReadWriteArgMem, NoCapture<3>]>;
440 class AdvSIMD_3Vec_Load_Intrinsic
441 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
442 [LLVMAnyPointerType<LLVMMatchType<0>>],
444 class AdvSIMD_3Vec_Load_Lane_Intrinsic
445 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
446 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
447 llvm_i64_ty, llvm_anyptr_ty],
449 class AdvSIMD_3Vec_Store_Intrinsic
450 : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
451 LLVMMatchType<0>, LLVMAnyPointerType<LLVMMatchType<0>>],
452 [IntrReadWriteArgMem, NoCapture<3>]>;
453 class AdvSIMD_3Vec_Store_Lane_Intrinsic
454 : Intrinsic<[], [llvm_anyvector_ty,
455 LLVMMatchType<0>, LLVMMatchType<0>,
456 llvm_i64_ty, llvm_anyptr_ty],
457 [IntrReadWriteArgMem, NoCapture<4>]>;
459 class AdvSIMD_4Vec_Load_Intrinsic
460 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
461 LLVMMatchType<0>, LLVMMatchType<0>],
462 [LLVMAnyPointerType<LLVMMatchType<0>>],
464 class AdvSIMD_4Vec_Load_Lane_Intrinsic
465 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
466 LLVMMatchType<0>, LLVMMatchType<0>],
467 [LLVMMatchType<0>, LLVMMatchType<0>,
468 LLVMMatchType<0>, LLVMMatchType<0>,
469 llvm_i64_ty, llvm_anyptr_ty],
471 class AdvSIMD_4Vec_Store_Intrinsic
472 : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
473 LLVMMatchType<0>, LLVMMatchType<0>,
474 LLVMAnyPointerType<LLVMMatchType<0>>],
475 [IntrReadWriteArgMem, NoCapture<4>]>;
476 class AdvSIMD_4Vec_Store_Lane_Intrinsic
477 : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
478 LLVMMatchType<0>, LLVMMatchType<0>,
479 llvm_i64_ty, llvm_anyptr_ty],
480 [IntrReadWriteArgMem, NoCapture<5>]>;
485 def int_arm64_neon_ld1x2 : AdvSIMD_2Vec_Load_Intrinsic;
486 def int_arm64_neon_ld1x3 : AdvSIMD_3Vec_Load_Intrinsic;
487 def int_arm64_neon_ld1x4 : AdvSIMD_4Vec_Load_Intrinsic;
489 def int_arm64_neon_st1x2 : AdvSIMD_2Vec_Store_Intrinsic;
490 def int_arm64_neon_st1x3 : AdvSIMD_3Vec_Store_Intrinsic;
491 def int_arm64_neon_st1x4 : AdvSIMD_4Vec_Store_Intrinsic;
493 def int_arm64_neon_ld2 : AdvSIMD_2Vec_Load_Intrinsic;
494 def int_arm64_neon_ld3 : AdvSIMD_3Vec_Load_Intrinsic;
495 def int_arm64_neon_ld4 : AdvSIMD_4Vec_Load_Intrinsic;
497 def int_arm64_neon_ld2lane : AdvSIMD_2Vec_Load_Lane_Intrinsic;
498 def int_arm64_neon_ld3lane : AdvSIMD_3Vec_Load_Lane_Intrinsic;
499 def int_arm64_neon_ld4lane : AdvSIMD_4Vec_Load_Lane_Intrinsic;
501 def int_arm64_neon_ld2r : AdvSIMD_2Vec_Load_Intrinsic;
502 def int_arm64_neon_ld3r : AdvSIMD_3Vec_Load_Intrinsic;
503 def int_arm64_neon_ld4r : AdvSIMD_4Vec_Load_Intrinsic;
505 def int_arm64_neon_st2 : AdvSIMD_2Vec_Store_Intrinsic;
506 def int_arm64_neon_st3 : AdvSIMD_3Vec_Store_Intrinsic;
507 def int_arm64_neon_st4 : AdvSIMD_4Vec_Store_Intrinsic;
509 def int_arm64_neon_st2lane : AdvSIMD_2Vec_Store_Lane_Intrinsic;
510 def int_arm64_neon_st3lane : AdvSIMD_3Vec_Store_Lane_Intrinsic;
511 def int_arm64_neon_st4lane : AdvSIMD_4Vec_Store_Lane_Intrinsic;
513 let TargetPrefix = "arm64" in { // All intrinsics start with "llvm.arm64.".
514 class AdvSIMD_Tbl1_Intrinsic
515 : Intrinsic<[llvm_anyvector_ty], [llvm_v16i8_ty, LLVMMatchType<0>],
517 class AdvSIMD_Tbl2_Intrinsic
518 : Intrinsic<[llvm_anyvector_ty],
519 [llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>;
520 class AdvSIMD_Tbl3_Intrinsic
521 : Intrinsic<[llvm_anyvector_ty],
522 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
525 class AdvSIMD_Tbl4_Intrinsic
526 : Intrinsic<[llvm_anyvector_ty],
527 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
531 class AdvSIMD_Tbx1_Intrinsic
532 : Intrinsic<[llvm_anyvector_ty],
533 [LLVMMatchType<0>, llvm_v16i8_ty, LLVMMatchType<0>],
535 class AdvSIMD_Tbx2_Intrinsic
536 : Intrinsic<[llvm_anyvector_ty],
537 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
540 class AdvSIMD_Tbx3_Intrinsic
541 : Intrinsic<[llvm_anyvector_ty],
542 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
543 llvm_v16i8_ty, LLVMMatchType<0>],
545 class AdvSIMD_Tbx4_Intrinsic
546 : Intrinsic<[llvm_anyvector_ty],
547 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
548 llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>],
551 def int_arm64_neon_tbl1 : AdvSIMD_Tbl1_Intrinsic;
552 def int_arm64_neon_tbl2 : AdvSIMD_Tbl2_Intrinsic;
553 def int_arm64_neon_tbl3 : AdvSIMD_Tbl3_Intrinsic;
554 def int_arm64_neon_tbl4 : AdvSIMD_Tbl4_Intrinsic;
556 def int_arm64_neon_tbx1 : AdvSIMD_Tbx1_Intrinsic;
557 def int_arm64_neon_tbx2 : AdvSIMD_Tbx2_Intrinsic;
558 def int_arm64_neon_tbx3 : AdvSIMD_Tbx3_Intrinsic;
559 def int_arm64_neon_tbx4 : AdvSIMD_Tbx4_Intrinsic;
561 let TargetPrefix = "arm64" in {
562 class Crypto_AES_DataKey_Intrinsic
563 : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
565 class Crypto_AES_Data_Intrinsic
566 : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
568 // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule
570 class Crypto_SHA_5Hash4Schedule_Intrinsic
571 : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
574 // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule
576 class Crypto_SHA_1Hash_Intrinsic
577 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
579 // SHA intrinsic taking 8 words of the schedule
580 class Crypto_SHA_8Schedule_Intrinsic
581 : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
583 // SHA intrinsic taking 12 words of the schedule
584 class Crypto_SHA_12Schedule_Intrinsic
585 : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
588 // SHA intrinsic taking 8 words of the hash and 4 of the schedule.
589 class Crypto_SHA_8Hash4Schedule_Intrinsic
590 : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
595 def int_arm64_crypto_aese : Crypto_AES_DataKey_Intrinsic;
596 def int_arm64_crypto_aesd : Crypto_AES_DataKey_Intrinsic;
597 def int_arm64_crypto_aesmc : Crypto_AES_Data_Intrinsic;
598 def int_arm64_crypto_aesimc : Crypto_AES_Data_Intrinsic;
601 def int_arm64_crypto_sha1c : Crypto_SHA_5Hash4Schedule_Intrinsic;
602 def int_arm64_crypto_sha1p : Crypto_SHA_5Hash4Schedule_Intrinsic;
603 def int_arm64_crypto_sha1m : Crypto_SHA_5Hash4Schedule_Intrinsic;
604 def int_arm64_crypto_sha1h : Crypto_SHA_1Hash_Intrinsic;
606 def int_arm64_crypto_sha1su0 : Crypto_SHA_12Schedule_Intrinsic;
607 def int_arm64_crypto_sha1su1 : Crypto_SHA_8Schedule_Intrinsic;
610 def int_arm64_crypto_sha256h : Crypto_SHA_8Hash4Schedule_Intrinsic;
611 def int_arm64_crypto_sha256h2 : Crypto_SHA_8Hash4Schedule_Intrinsic;
612 def int_arm64_crypto_sha256su0 : Crypto_SHA_8Schedule_Intrinsic;
613 def int_arm64_crypto_sha256su1 : Crypto_SHA_12Schedule_Intrinsic;
615 //===----------------------------------------------------------------------===//
618 let TargetPrefix = "arm64" in {
620 def int_arm64_crc32b : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
622 def int_arm64_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
624 def int_arm64_crc32h : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
626 def int_arm64_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
628 def int_arm64_crc32w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
630 def int_arm64_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
632 def int_arm64_crc32x : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
634 def int_arm64_crc32cx : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],