1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAGISEL_H
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/IR/BasicBlock.h"
21 #include "llvm/Target/TargetSubtargetInfo.h"
22 #include "llvm/Pass.h"
26 class SelectionDAGBuilder;
28 class MachineRegisterInfo;
29 class MachineBasicBlock;
30 class MachineFunction;
33 class TargetLibraryInfo;
34 class FunctionLoweringInfo;
35 class ScheduleHazardRecognizer;
37 class ScheduleDAGSDNodes;
40 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
41 /// pattern-matching instruction selectors.
42 class SelectionDAGISel : public MachineFunctionPass {
45 const TargetLibraryInfo *LibInfo;
46 FunctionLoweringInfo *FuncInfo;
48 MachineRegisterInfo *RegInfo;
50 SelectionDAGBuilder *SDB;
53 CodeGenOpt::Level OptLevel;
54 const TargetInstrInfo *TII;
58 explicit SelectionDAGISel(TargetMachine &tm,
59 CodeGenOpt::Level OL = CodeGenOpt::Default);
60 virtual ~SelectionDAGISel();
62 const TargetLowering *getTargetLowering() const {
63 return TM.getSubtargetImpl()->getTargetLowering();
66 void getAnalysisUsage(AnalysisUsage &AU) const override;
68 bool runOnMachineFunction(MachineFunction &MF) override;
70 virtual void EmitFunctionEntryCode() {}
72 /// PreprocessISelDAG - This hook allows targets to hack on the graph before
73 /// instruction selection starts.
74 virtual void PreprocessISelDAG() {}
76 /// PostprocessISelDAG() - This hook allows the target to hack on the graph
77 /// right after selection.
78 virtual void PostprocessISelDAG() {}
80 /// Select - Main hook targets implement to select a node.
81 virtual SDNode *Select(SDNode *N) = 0;
83 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
84 /// addressing mode, according to the specified constraint code. If this does
85 /// not match or is not implemented, return true. The resultant operands
86 /// (which will appear in the machine instruction) should be added to the
88 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
90 std::vector<SDValue> &OutOps) {
94 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
95 /// operand node N of U during instruction selection that starts at Root.
96 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
98 /// IsLegalToFold - Returns true if the specific operand node N of
99 /// U can be folded during instruction selection that starts at Root.
100 /// FIXME: This is a static member function because the MSP430/X86
101 /// targets, which uses it during isel. This could become a proper member.
102 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
103 CodeGenOpt::Level OptLevel,
104 bool IgnoreChains = false);
106 // Opcodes used by the DAG state machine:
107 enum BuiltinOpcodes {
110 OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
111 OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
113 OPC_CaptureGlueInput,
117 OPC_CheckChild0Same, OPC_CheckChild1Same,
118 OPC_CheckChild2Same, OPC_CheckChild3Same,
119 OPC_CheckPatternPredicate,
125 OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
126 OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
127 OPC_CheckChild6Type, OPC_CheckChild7Type,
129 OPC_CheckChild0Integer, OPC_CheckChild1Integer, OPC_CheckChild2Integer,
130 OPC_CheckChild3Integer, OPC_CheckChild4Integer,
134 OPC_CheckAndImm, OPC_CheckOrImm,
135 OPC_CheckFoldableChainNode,
140 OPC_EmitConvertToTarget,
141 OPC_EmitMergeInputChains,
142 OPC_EmitMergeInputChains1_0,
143 OPC_EmitMergeInputChains1_1,
153 OPFL_None = 0, // Node has no chain or glue input and isn't variadic.
154 OPFL_Chain = 1, // Node has a chain input.
155 OPFL_GlueInput = 2, // Node has a glue input.
156 OPFL_GlueOutput = 4, // Node has a glue output.
157 OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
158 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs.
159 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs.
160 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs.
161 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs.
162 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs.
163 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs.
164 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs.
166 OPFL_VariadicInfo = OPFL_Variadic6
169 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
170 /// number of fixed arity values that should be skipped when copying from the
172 static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
173 return ((Flags&OPFL_VariadicInfo) >> 4)-1;
178 /// DAGSize - Size of DAG being instruction selected.
182 /// ReplaceUses - replace all uses of the old node F with the use
183 /// of the new node T.
184 void ReplaceUses(SDValue F, SDValue T) {
185 CurDAG->ReplaceAllUsesOfValueWith(F, T);
188 /// ReplaceUses - replace all uses of the old nodes F with the use
189 /// of the new nodes T.
190 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
191 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num);
194 /// ReplaceUses - replace all uses of the old node F with the use
195 /// of the new node T.
196 void ReplaceUses(SDNode *F, SDNode *T) {
197 CurDAG->ReplaceAllUsesWith(F, T);
201 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
202 /// by tblgen. Others should not call it.
203 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
207 // Calls to these predicates are generated by tblgen.
208 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
209 int64_t DesiredMaskS) const;
210 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
211 int64_t DesiredMaskS) const;
214 /// CheckPatternPredicate - This function is generated by tblgen in the
215 /// target. It runs the specified pattern predicate and returns true if it
216 /// succeeds or false if it fails. The number is a private implementation
217 /// detail to the code tblgen produces.
218 virtual bool CheckPatternPredicate(unsigned PredNo) const {
219 llvm_unreachable("Tblgen should generate the implementation of this!");
222 /// CheckNodePredicate - This function is generated by tblgen in the target.
223 /// It runs node predicate number PredNo and returns true if it succeeds or
224 /// false if it fails. The number is a private implementation
225 /// detail to the code tblgen produces.
226 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
227 llvm_unreachable("Tblgen should generate the implementation of this!");
230 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
232 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
233 llvm_unreachable("Tblgen should generate the implementation of this!");
236 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
237 llvm_unreachable("Tblgen should generate this!");
240 SDNode *SelectCodeCommon(SDNode *NodeToMatch,
241 const unsigned char *MatcherTable,
244 /// \brief Return true if complex patterns for this target can mutate the
246 virtual bool ComplexPatternFuncMutatesDAG() const {
252 // Calls to these functions are generated by tblgen.
253 SDNode *Select_INLINEASM(SDNode *N);
254 SDNode *Select_READ_REGISTER(SDNode *N);
255 SDNode *Select_WRITE_REGISTER(SDNode *N);
256 SDNode *Select_UNDEF(SDNode *N);
257 void CannotYetSelect(SDNode *N);
260 void DoInstructionSelection();
261 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs,
262 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
264 void PrepareEHLandingPad();
266 /// \brief Perform instruction selection on all basic blocks in the function.
267 void SelectAllBasicBlocks(const Function &Fn);
269 /// \brief Perform instruction selection on a single basic block, for
270 /// instructions between \p Begin and \p End. \p HadTailCall will be set
271 /// to true if a call in the block was translated as a tail call.
272 void SelectBasicBlock(BasicBlock::const_iterator Begin,
273 BasicBlock::const_iterator End,
275 void FinishBasicBlock();
277 void CodeGenAndEmitDAG();
279 /// \brief Generate instructions for lowering the incoming arguments of the
281 void LowerArguments(const Function &F);
283 void ComputeLiveOutVRegInfo();
285 /// Create the scheduler. If a specific scheduler was specified
286 /// via the SchedulerRegistry, use it, otherwise select the
287 /// one preferred by the target.
289 ScheduleDAGSDNodes *CreateScheduler();
291 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
292 /// state machines that start with a OPC_SwitchOpcode node.
293 std::vector<unsigned> OpcodeOffset;
295 void UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
296 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
297 SDValue InputGlue, const SmallVectorImpl<SDNode*> &F,
304 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */