1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/BasicBlock.h"
19 #include "llvm/Pass.h"
20 #include "llvm/Constant.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
25 class SelectionDAGLowering;
27 class MachineRegisterInfo;
28 class MachineBasicBlock;
29 class MachineFunction;
31 class MachineModuleInfo;
34 class TargetInstrInfo;
35 class FunctionLoweringInfo;
36 class ScheduleHazardRecognizer;
38 class ScheduleDAGSDNodes;
40 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
41 /// pattern-matching instruction selectors.
42 class SelectionDAGISel : public FunctionPass {
44 const TargetMachine &TM;
46 FunctionLoweringInfo *FuncInfo;
48 MachineRegisterInfo *RegInfo;
50 SelectionDAGLowering *SDL;
51 MachineBasicBlock *BB;
54 CodeGenOpt::Level OptLevel;
57 explicit SelectionDAGISel(TargetMachine &tm,
58 CodeGenOpt::Level OL = CodeGenOpt::Default);
59 virtual ~SelectionDAGISel();
61 TargetLowering &getTargetLowering() { return TLI; }
63 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
65 virtual bool runOnFunction(Function &Fn);
67 unsigned MakeReg(MVT VT);
69 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
70 virtual void InstructionSelect() = 0;
72 void SelectRootInit() {
73 DAGSize = CurDAG->AssignTopologicalOrder();
76 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
77 /// addressing mode, according to the specified constraint code. If this does
78 /// not match or is not implemented, return true. The resultant operands
79 /// (which will appear in the machine instruction) should be added to the
81 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
83 std::vector<SDValue> &OutOps) {
87 /// IsLegalAndProfitableToFold - Returns true if the specific operand node N of
88 /// U can be folded during instruction selection that starts at Root and
89 /// folding N is profitable.
91 bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const;
93 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
94 /// to use for this target when scheduling the DAG.
95 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
98 /// DAGSize - Size of DAG being instruction selected.
102 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
103 /// by tblgen. Others should not call it.
104 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
106 // Calls to these predicates are generated by tblgen.
107 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
108 int64_t DesiredMaskS) const;
109 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
110 int64_t DesiredMaskS) const;
113 void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
114 MachineModuleInfo *MMI,
116 const TargetInstrInfo &TII);
117 void FinishBasicBlock();
119 void SelectBasicBlock(BasicBlock *LLVMBB,
120 BasicBlock::iterator Begin,
121 BasicBlock::iterator End);
122 void CodeGenAndEmitDAG();
123 void LowerArguments(BasicBlock *BB);
125 void ComputeLiveOutVRegInfo();
127 void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
129 bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
131 /// Create the scheduler. If a specific scheduler was specified
132 /// via the SchedulerRegistry, use it, otherwise select the
133 /// one preferred by the target.
135 ScheduleDAGSDNodes *CreateScheduler();
140 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */