1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/BasicBlock.h"
19 #include "llvm/Pass.h"
20 #include "llvm/Constant.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/raw_ostream.h"
27 class SelectionDAGLowering;
29 class MachineRegisterInfo;
30 class MachineBasicBlock;
31 class MachineFunction;
33 class MachineModuleInfo;
36 class TargetInstrInfo;
37 class FunctionLoweringInfo;
38 class ScheduleHazardRecognizer;
40 class ScheduleDAGSDNodes;
42 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
43 /// pattern-matching instruction selectors.
44 class SelectionDAGISel : public FunctionPass {
46 const TargetMachine &TM;
48 FunctionLoweringInfo *FuncInfo;
50 MachineRegisterInfo *RegInfo;
52 SelectionDAGLowering *SDL;
53 MachineBasicBlock *BB;
56 CodeGenOpt::Level OptLevel;
59 explicit SelectionDAGISel(TargetMachine &tm,
60 CodeGenOpt::Level OL = CodeGenOpt::Default);
61 virtual ~SelectionDAGISel();
63 TargetLowering &getTargetLowering() { return TLI; }
65 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
67 virtual bool runOnFunction(Function &Fn);
69 unsigned MakeReg(MVT VT);
71 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
72 virtual void InstructionSelect() = 0;
74 void SelectRootInit() {
75 DAGSize = CurDAG->AssignTopologicalOrder();
78 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
79 /// addressing mode, according to the specified constraint code. If this does
80 /// not match or is not implemented, return true. The resultant operands
81 /// (which will appear in the machine instruction) should be added to the
83 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
85 std::vector<SDValue> &OutOps) {
89 /// IsLegalAndProfitableToFold - Returns true if the specific operand node N of
90 /// U can be folded during instruction selection that starts at Root and
91 /// folding N is profitable.
93 bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const;
95 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
96 /// to use for this target when scheduling the DAG.
97 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
100 /// DAGSize - Size of DAG being instruction selected.
104 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
105 /// by tblgen. Others should not call it.
106 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
108 // Calls to these predicates are generated by tblgen.
109 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
110 int64_t DesiredMaskS) const;
111 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
112 int64_t DesiredMaskS) const;
115 void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
116 MachineModuleInfo *MMI,
118 const TargetInstrInfo &TII);
119 void FinishBasicBlock();
121 void SelectBasicBlock(BasicBlock *LLVMBB,
122 BasicBlock::iterator Begin,
123 BasicBlock::iterator End);
124 void CodeGenAndEmitDAG();
125 void LowerArguments(BasicBlock *BB);
127 void ComputeLiveOutVRegInfo();
129 void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
131 bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
133 /// Create the scheduler. If a specific scheduler was specified
134 /// via the SchedulerRegistry, use it, otherwise select the
135 /// one preferred by the target.
137 ScheduleDAGSDNodes *CreateScheduler();
142 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */