1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/Pass.h"
19 #include "llvm/Constant.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SelectionDAGNodes.h"
24 class SelectionDAGLowering;
27 class MachineBasicBlock;
28 class MachineFunction;
31 class FunctionLoweringInfo;
32 class HazardRecognizer;
34 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
35 /// pattern-matching instruction selectors.
36 class SelectionDAGISel : public FunctionPass {
41 MachineBasicBlock *BB;
43 std::vector<SDNode*> TopOrder;
47 explicit SelectionDAGISel(TargetLowering &tli) :
48 FunctionPass((intptr_t)&ID), TLI(tli), DAGSize(0) {}
50 TargetLowering &getTargetLowering() { return TLI; }
52 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
54 virtual bool runOnFunction(Function &Fn);
56 unsigned MakeReg(MVT::ValueType VT);
58 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
59 virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
60 virtual void SelectRootInit() {
61 DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);
64 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
65 /// addressing mode, according to the specified constraint code. If this does
66 /// not match or is not implemented, return true. The resultant operands
67 /// (which will appear in the machine instruction) should be added to the
69 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
71 std::vector<SDOperand> &OutOps,
76 /// CanBeFoldedBy - Returns true if the specific operand node N of U can be
77 /// folded during instruction selection that starts at Root?
78 virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const {
82 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
83 /// to use for this target when scheduling the DAG.
84 virtual HazardRecognizer *CreateTargetHazardRecognizer();
86 /// CaseBlock - This structure is used to communicate between SDLowering and
87 /// SDISel for the code generation of additional basic blocks needed by multi-
88 /// case switch statements.
90 CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
91 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
92 MachineBasicBlock *me)
93 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
94 TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
95 // CC - the condition code to use for the case block's setcc node
97 // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
98 // Emit by default LHS op RHS. MHS is used for range comparisons:
99 // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
100 Value *CmpLHS, *CmpMHS, *CmpRHS;
101 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
102 MachineBasicBlock *TrueBB, *FalseBB;
103 // ThisBB - the block into which to emit the code for the setcc and branches
104 MachineBasicBlock *ThisBB;
107 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
108 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
110 /// Reg - the virtual register containing the index of the jump table entry
113 /// JTI - the JumpTableIndex for this jump table in the function.
115 /// MBB - the MBB into which to emit the code for the indirect jump.
116 MachineBasicBlock *MBB;
117 /// Default - the MBB of the default bb, which is a successor of the range
118 /// check MBB. This is when updating PHI nodes in successors.
119 MachineBasicBlock *Default;
121 struct JumpTableHeader {
122 JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
124 First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
128 MachineBasicBlock *HeaderBB;
131 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
134 BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
135 Mask(M), ThisBB(T), TargetBB(Tr) { }
137 MachineBasicBlock* ThisBB;
138 MachineBasicBlock* TargetBB;
141 typedef SmallVector<BitTestCase, 3> BitTestInfo;
143 struct BitTestBlock {
144 BitTestBlock(uint64_t F, uint64_t R, Value* SV,
146 MachineBasicBlock* P, MachineBasicBlock* D,
147 const BitTestInfo& C):
148 First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
149 Parent(P), Default(D), Cases(C) { }
155 MachineBasicBlock *Parent;
156 MachineBasicBlock *Default;
160 /// Pick a safe ordering and emit instructions for each target node in the
162 void ScheduleAndEmitDAG(SelectionDAG &DAG);
164 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
165 /// by tblgen. Others should not call it.
166 void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
169 // Calls to these predicates are generated by tblgen.
170 bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
171 int64_t DesiredMaskS) const;
172 bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
173 int64_t DesiredMaskS) const;
176 void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
177 FunctionLoweringInfo &FuncInfo);
179 void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
180 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
181 FunctionLoweringInfo &FuncInfo);
182 void CodeGenAndEmitDAG(SelectionDAG &DAG);
183 void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
184 std::vector<SDOperand> &UnorderedChains);
186 /// SwitchCases - Vector of CaseBlock structures used to communicate
187 /// SwitchInst code generation information.
188 std::vector<CaseBlock> SwitchCases;
190 /// JTCases - Vector of JumpTable structures which holds necessary information
191 /// for emitting a jump tables during SwitchInst code generation.
192 std::vector<JumpTableBlock> JTCases;
194 std::vector<BitTestBlock> BitTestCases;
199 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */