1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/BasicBlock.h"
19 #include "llvm/Pass.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
25 class SelectionDAGBuilder;
27 class MachineRegisterInfo;
28 class MachineBasicBlock;
29 class MachineFunction;
32 class TargetLibraryInfo;
33 class TargetInstrInfo;
34 class FunctionLoweringInfo;
35 class ScheduleHazardRecognizer;
37 class ScheduleDAGSDNodes;
40 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
41 /// pattern-matching instruction selectors.
42 class SelectionDAGISel : public MachineFunctionPass {
44 const TargetMachine &TM;
45 const TargetLowering &TLI;
46 const TargetLibraryInfo *LibInfo;
47 FunctionLoweringInfo *FuncInfo;
49 MachineRegisterInfo *RegInfo;
51 SelectionDAGBuilder *SDB;
54 CodeGenOpt::Level OptLevel;
57 explicit SelectionDAGISel(const TargetMachine &tm,
58 CodeGenOpt::Level OL = CodeGenOpt::Default);
59 virtual ~SelectionDAGISel();
61 const TargetLowering &getTargetLowering() { return TLI; }
63 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
65 virtual bool runOnMachineFunction(MachineFunction &MF);
67 virtual void EmitFunctionEntryCode() {}
69 /// PreprocessISelDAG - This hook allows targets to hack on the graph before
70 /// instruction selection starts.
71 virtual void PreprocessISelDAG() {}
73 /// PostprocessISelDAG() - This hook allows the target to hack on the graph
74 /// right after selection.
75 virtual void PostprocessISelDAG() {}
77 /// Select - Main hook targets implement to select a node.
78 virtual SDNode *Select(SDNode *N) = 0;
80 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
81 /// addressing mode, according to the specified constraint code. If this does
82 /// not match or is not implemented, return true. The resultant operands
83 /// (which will appear in the machine instruction) should be added to the
85 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
87 std::vector<SDValue> &OutOps) {
91 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
92 /// operand node N of U during instruction selection that starts at Root.
93 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
95 /// IsLegalToFold - Returns true if the specific operand node N of
96 /// U can be folded during instruction selection that starts at Root.
97 /// FIXME: This is a static member function because the MSP430/X86
98 /// targets, which uses it during isel. This could become a proper member.
99 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
100 CodeGenOpt::Level OptLevel,
101 bool IgnoreChains = false);
103 // Opcodes used by the DAG state machine:
104 enum BuiltinOpcodes {
107 OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
108 OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
110 OPC_CaptureGlueInput,
114 OPC_CheckPatternPredicate,
120 OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
121 OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
122 OPC_CheckChild6Type, OPC_CheckChild7Type,
127 OPC_CheckAndImm, OPC_CheckOrImm,
128 OPC_CheckFoldableChainNode,
133 OPC_EmitConvertToTarget,
134 OPC_EmitMergeInputChains,
135 OPC_EmitMergeInputChains1_0,
136 OPC_EmitMergeInputChains1_1,
146 OPFL_None = 0, // Node has no chain or glue input and isn't variadic.
147 OPFL_Chain = 1, // Node has a chain input.
148 OPFL_GlueInput = 2, // Node has a glue input.
149 OPFL_GlueOutput = 4, // Node has a glue output.
150 OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
151 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs.
152 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs.
153 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs.
154 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs.
155 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs.
156 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs.
157 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs.
159 OPFL_VariadicInfo = OPFL_Variadic6
162 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
163 /// number of fixed arity values that should be skipped when copying from the
165 static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
166 return ((Flags&OPFL_VariadicInfo) >> 4)-1;
171 /// DAGSize - Size of DAG being instruction selected.
175 /// ReplaceUses - replace all uses of the old node F with the use
176 /// of the new node T.
177 void ReplaceUses(SDValue F, SDValue T) {
178 CurDAG->ReplaceAllUsesOfValueWith(F, T);
181 /// ReplaceUses - replace all uses of the old nodes F with the use
182 /// of the new nodes T.
183 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
184 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num);
187 /// ReplaceUses - replace all uses of the old node F with the use
188 /// of the new node T.
189 void ReplaceUses(SDNode *F, SDNode *T) {
190 CurDAG->ReplaceAllUsesWith(F, T);
194 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
195 /// by tblgen. Others should not call it.
196 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
200 // Calls to these predicates are generated by tblgen.
201 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
202 int64_t DesiredMaskS) const;
203 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
204 int64_t DesiredMaskS) const;
207 /// CheckPatternPredicate - This function is generated by tblgen in the
208 /// target. It runs the specified pattern predicate and returns true if it
209 /// succeeds or false if it fails. The number is a private implementation
210 /// detail to the code tblgen produces.
211 virtual bool CheckPatternPredicate(unsigned PredNo) const {
212 llvm_unreachable("Tblgen should generate the implementation of this!");
215 /// CheckNodePredicate - This function is generated by tblgen in the target.
216 /// It runs node predicate number PredNo and returns true if it succeeds or
217 /// false if it fails. The number is a private implementation
218 /// detail to the code tblgen produces.
219 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
220 llvm_unreachable("Tblgen should generate the implementation of this!");
223 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
225 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
226 llvm_unreachable("Tblgen should generate the implementation of this!");
229 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
230 llvm_unreachable("Tblgen should generate this!");
233 SDNode *SelectCodeCommon(SDNode *NodeToMatch,
234 const unsigned char *MatcherTable,
239 // Calls to these functions are generated by tblgen.
240 SDNode *Select_INLINEASM(SDNode *N);
241 SDNode *Select_UNDEF(SDNode *N);
242 void CannotYetSelect(SDNode *N);
245 void DoInstructionSelection();
246 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs,
247 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo);
249 void PrepareEHLandingPad();
250 void SelectAllBasicBlocks(const Function &Fn);
251 bool TryToFoldFastISelLoad(const LoadInst *LI, const Instruction *FoldInst,
253 void FinishBasicBlock();
255 void SelectBasicBlock(BasicBlock::const_iterator Begin,
256 BasicBlock::const_iterator End,
258 void CodeGenAndEmitDAG();
259 void LowerArguments(const BasicBlock *BB);
261 void ComputeLiveOutVRegInfo();
263 /// Create the scheduler. If a specific scheduler was specified
264 /// via the SchedulerRegistry, use it, otherwise select the
265 /// one preferred by the target.
267 ScheduleDAGSDNodes *CreateScheduler();
269 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
270 /// state machines that start with a OPC_SwitchOpcode node.
271 std::vector<unsigned> OpcodeOffset;
273 void UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
274 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
275 SDValue InputGlue, const SmallVectorImpl<SDNode*> &F,
282 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */