1 //===---- llvm/CodeGen/ScheduleDAGSDNodes.h - SDNode Scheduling -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAGSDNodes class, which implements
11 // scheduling for an SDNode-based dependency graph.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULEDAGSDNODES_H
16 #define LLVM_CODEGEN_SCHEDULEDAGSDNODES_H
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/ADT/SmallSet.h"
23 /// HazardRecognizer - This determines whether or not an instruction can be
24 /// issued this cycle, and whether or not a noop needs to be inserted to handle
26 class HazardRecognizer {
28 virtual ~HazardRecognizer();
31 NoHazard, // This instruction can be emitted at this cycle.
32 Hazard, // This instruction can't be emitted at this cycle.
33 NoopHazard // This instruction can't be emitted, and needs noops.
36 /// getHazardType - Return the hazard type of emitting this node. There are
37 /// three possible results. Either:
38 /// * NoHazard: it is legal to issue this instruction on this cycle.
39 /// * Hazard: issuing this instruction would stall the machine. If some
40 /// other instruction is available, issue it first.
41 /// * NoopHazard: issuing this instruction would break the program. If
42 /// some other instruction can be issued, do so, otherwise issue a noop.
43 virtual HazardType getHazardType(SDNode *) {
47 /// EmitInstruction - This callback is invoked when an instruction is
48 /// emitted, to advance the hazard state.
49 virtual void EmitInstruction(SDNode *) {}
51 /// AdvanceCycle - This callback is invoked when no instructions can be
52 /// issued on this cycle without a hazard. This should increment the
53 /// internal state of the hazard recognizer so that previously "Hazard"
54 /// instructions will now not be hazards.
55 virtual void AdvanceCycle() {}
57 /// EmitNoop - This callback is invoked when a noop was added to the
58 /// instruction stream.
59 virtual void EmitNoop() {}
62 class ScheduleDAGSDNodes : public ScheduleDAG {
64 SmallSet<SDNode*, 16> CommuteSet; // Nodes that should be commuted.
66 ScheduleDAGSDNodes(SelectionDAG *dag, MachineBasicBlock *bb,
67 const TargetMachine &tm);
69 virtual ~ScheduleDAGSDNodes() {}
71 /// isPassiveNode - Return true if the node is a non-scheduled leaf.
73 static bool isPassiveNode(SDNode *Node) {
74 if (isa<ConstantSDNode>(Node)) return true;
75 if (isa<ConstantFPSDNode>(Node)) return true;
76 if (isa<RegisterSDNode>(Node)) return true;
77 if (isa<GlobalAddressSDNode>(Node)) return true;
78 if (isa<BasicBlockSDNode>(Node)) return true;
79 if (isa<FrameIndexSDNode>(Node)) return true;
80 if (isa<ConstantPoolSDNode>(Node)) return true;
81 if (isa<JumpTableSDNode>(Node)) return true;
82 if (isa<ExternalSymbolSDNode>(Node)) return true;
83 if (isa<MemOperandSDNode>(Node)) return true;
84 if (Node->getOpcode() == ISD::EntryToken) return true;
88 /// NewSUnit - Creates a new SUnit and return a ptr to it.
90 SUnit *NewSUnit(SDNode *N) {
91 SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
92 SUnits.back().OrigNode = &SUnits.back();
93 return &SUnits.back();
96 /// Clone - Creates a clone of the specified SUnit. It does not copy the
97 /// predecessors / successors info nor the temporary scheduling states.
99 SUnit *Clone(SUnit *N);
101 virtual SelectionDAG *getDAG() { return DAG; }
103 /// BuildSchedUnits - Build SUnits from the selection dag that we are input.
104 /// This SUnit graph is similar to the SelectionDAG, but represents flagged
105 /// together nodes with a single SUnit.
106 virtual void BuildSchedUnits();
108 /// ComputeLatency - Compute node latency.
110 virtual void ComputeLatency(SUnit *SU);
112 /// CountResults - The results of target nodes have register or immediate
113 /// operands first, then an optional chain, and optional flag operands
114 /// (which do not go into the machine instrs.)
115 static unsigned CountResults(SDNode *Node);
117 /// CountOperands - The inputs to target nodes have any actual inputs first,
118 /// followed by special operands that describe memory references, then an
119 /// optional chain operand, then flag operands. Compute the number of
120 /// actual operands that will go into the resulting MachineInstr.
121 static unsigned CountOperands(SDNode *Node);
123 /// ComputeMemOperandsEnd - Find the index one past the last
124 /// MemOperandSDNode operand
125 static unsigned ComputeMemOperandsEnd(SDNode *Node);
127 /// EmitNode - Generate machine code for an node and needed dependencies.
128 /// VRBaseMap contains, for each already emitted node, the first virtual
129 /// register number for the results of the node.
131 void EmitNode(SDNode *Node, bool IsClone,
132 DenseMap<SDValue, unsigned> &VRBaseMap);
134 virtual MachineBasicBlock *EmitSchedule();
136 /// Schedule - Order nodes according to selected style, filling
137 /// in the Sequence member.
139 virtual void Schedule() = 0;
141 virtual void dumpNode(const SUnit *SU) const;
143 virtual std::string getGraphNodeLabel(const SUnit *SU) const;
145 virtual void getCustomGraphFeatures(GraphWriter<ScheduleDAG*> &GW) const;
148 /// EmitSubregNode - Generate machine code for subreg nodes.
150 void EmitSubregNode(SDNode *Node,
151 DenseMap<SDValue, unsigned> &VRBaseMap);
153 /// getVR - Return the virtual register corresponding to the specified result
154 /// of the specified node.
155 unsigned getVR(SDValue Op, DenseMap<SDValue, unsigned> &VRBaseMap);
157 /// getDstOfCopyToRegUse - If the only use of the specified result number of
158 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
159 unsigned getDstOfOnlyCopyToRegUse(SDNode *Node, unsigned ResNo) const;
161 void AddOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum,
162 const TargetInstrDesc *II,
163 DenseMap<SDValue, unsigned> &VRBaseMap);
165 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
166 /// implicit physical register output.
167 void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
169 DenseMap<SDValue, unsigned> &VRBaseMap);
171 void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
172 const TargetInstrDesc &II,
173 DenseMap<SDValue, unsigned> &VRBaseMap);