1 //===---- llvm/CodeGen/ScheduleDAGSDNodes.h - SDNode Scheduling -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAGSDNodes class, which implements
11 // scheduling for an SDNode-based dependency graph.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULEDAGSDNODES_H
16 #define LLVM_CODEGEN_SCHEDULEDAGSDNODES_H
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
22 /// HazardRecognizer - This determines whether or not an instruction can be
23 /// issued this cycle, and whether or not a noop needs to be inserted to handle
25 class HazardRecognizer {
27 virtual ~HazardRecognizer();
30 NoHazard, // This instruction can be emitted at this cycle.
31 Hazard, // This instruction can't be emitted at this cycle.
32 NoopHazard // This instruction can't be emitted, and needs noops.
35 /// getHazardType - Return the hazard type of emitting this node. There are
36 /// three possible results. Either:
37 /// * NoHazard: it is legal to issue this instruction on this cycle.
38 /// * Hazard: issuing this instruction would stall the machine. If some
39 /// other instruction is available, issue it first.
40 /// * NoopHazard: issuing this instruction would break the program. If
41 /// some other instruction can be issued, do so, otherwise issue a noop.
42 virtual HazardType getHazardType(SDNode *) {
46 /// EmitInstruction - This callback is invoked when an instruction is
47 /// emitted, to advance the hazard state.
48 virtual void EmitInstruction(SDNode *) {}
50 /// AdvanceCycle - This callback is invoked when no instructions can be
51 /// issued on this cycle without a hazard. This should increment the
52 /// internal state of the hazard recognizer so that previously "Hazard"
53 /// instructions will now not be hazards.
54 virtual void AdvanceCycle() {}
56 /// EmitNoop - This callback is invoked when a noop was added to the
57 /// instruction stream.
58 virtual void EmitNoop() {}
61 /// ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
63 /// Edges between SUnits are initially based on edges in the SelectionDAG,
64 /// and additional edges can be added by the schedulers as heuristics.
65 /// SDNodes such as Constants, Registers, and a few others that are not
66 /// interesting to schedulers are not allocated SUnits.
68 /// SDNodes with MVT::Flag operands are grouped along with the flagged
69 /// nodes into a single SUnit so that they are scheduled together.
71 /// SDNode-based scheduling graphs do not use SDep::Anti or SDep::Output
72 /// edges. Physical register dependence information is not carried in
73 /// the DAG and must be handled explicitly by schedulers.
75 class ScheduleDAGSDNodes : public ScheduleDAG {
77 explicit ScheduleDAGSDNodes(MachineFunction &mf);
79 virtual ~ScheduleDAGSDNodes() {}
81 /// isPassiveNode - Return true if the node is a non-scheduled leaf.
83 static bool isPassiveNode(SDNode *Node) {
84 if (isa<ConstantSDNode>(Node)) return true;
85 if (isa<ConstantFPSDNode>(Node)) return true;
86 if (isa<RegisterSDNode>(Node)) return true;
87 if (isa<GlobalAddressSDNode>(Node)) return true;
88 if (isa<BasicBlockSDNode>(Node)) return true;
89 if (isa<FrameIndexSDNode>(Node)) return true;
90 if (isa<ConstantPoolSDNode>(Node)) return true;
91 if (isa<JumpTableSDNode>(Node)) return true;
92 if (isa<ExternalSymbolSDNode>(Node)) return true;
93 if (isa<MemOperandSDNode>(Node)) return true;
94 if (Node->getOpcode() == ISD::EntryToken) return true;
98 /// NewSUnit - Creates a new SUnit and return a ptr to it.
100 SUnit *NewSUnit(SDNode *N) {
102 const SUnit *Addr = 0;
103 if (SUnits.size() > 0)
106 SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
107 assert((Addr == 0 || Addr == &SUnits[0]) &&
108 "SUnits std::vector reallocated on the fly!");
109 SUnits.back().OrigNode = &SUnits.back();
110 return &SUnits.back();
113 /// Clone - Creates a clone of the specified SUnit. It does not copy the
114 /// predecessors / successors info nor the temporary scheduling states.
116 SUnit *Clone(SUnit *N);
118 virtual SelectionDAG *getDAG() { return DAG; }
120 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
121 /// are input. This SUnit graph is similar to the SelectionDAG, but
122 /// excludes nodes that aren't interesting to scheduling, and represents
123 /// flagged together nodes with a single SUnit.
124 virtual void BuildSchedGraph();
126 /// ComputeLatency - Compute node latency.
128 virtual void ComputeLatency(SUnit *SU);
130 /// CountResults - The results of target nodes have register or immediate
131 /// operands first, then an optional chain, and optional flag operands
132 /// (which do not go into the machine instrs.)
133 static unsigned CountResults(SDNode *Node);
135 /// CountOperands - The inputs to target nodes have any actual inputs first,
136 /// followed by special operands that describe memory references, then an
137 /// optional chain operand, then flag operands. Compute the number of
138 /// actual operands that will go into the resulting MachineInstr.
139 static unsigned CountOperands(SDNode *Node);
141 /// ComputeMemOperandsEnd - Find the index one past the last
142 /// MemOperandSDNode operand
143 static unsigned ComputeMemOperandsEnd(SDNode *Node);
145 /// EmitNode - Generate machine code for an node and needed dependencies.
146 /// VRBaseMap contains, for each already emitted node, the first virtual
147 /// register number for the results of the node.
149 void EmitNode(SDNode *Node, bool IsClone,
150 DenseMap<SDValue, unsigned> &VRBaseMap);
152 virtual MachineBasicBlock *EmitSchedule();
154 /// Schedule - Order nodes according to selected style, filling
155 /// in the Sequence member.
157 virtual void Schedule() = 0;
159 virtual void dumpNode(const SUnit *SU) const;
161 virtual std::string getGraphNodeLabel(const SUnit *SU) const;
163 virtual void getCustomGraphFeatures(GraphWriter<ScheduleDAG*> &GW) const;
166 /// EmitSubregNode - Generate machine code for subreg nodes.
168 void EmitSubregNode(SDNode *Node,
169 DenseMap<SDValue, unsigned> &VRBaseMap);
171 /// getVR - Return the virtual register corresponding to the specified result
172 /// of the specified node.
173 unsigned getVR(SDValue Op, DenseMap<SDValue, unsigned> &VRBaseMap);
175 /// getDstOfCopyToRegUse - If the only use of the specified result number of
176 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
177 unsigned getDstOfOnlyCopyToRegUse(SDNode *Node, unsigned ResNo) const;
179 void AddOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum,
180 const TargetInstrDesc *II,
181 DenseMap<SDValue, unsigned> &VRBaseMap);
183 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
184 /// implicit physical register output.
185 void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
187 DenseMap<SDValue, unsigned> &VRBaseMap);
189 void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
190 const TargetInstrDesc &II, bool IsClone,
191 DenseMap<SDValue, unsigned> &VRBaseMap);
193 /// BuildSchedUnits, AddSchedEdges - Helper functions for BuildSchedGraph.
194 void BuildSchedUnits();
195 void AddSchedEdges();