1 //==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAGInstrs class, which implements
11 // scheduling for a MachineInstr-based dependency graph.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
16 #define LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
18 #include "llvm/ADT/SparseMultiSet.h"
19 #include "llvm/ADT/SparseSet.h"
20 #include "llvm/CodeGen/ScheduleDAG.h"
21 #include "llvm/CodeGen/TargetSchedule.h"
22 #include "llvm/Support/Compiler.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
26 class MachineFrameInfo;
27 class MachineLoopInfo;
28 class MachineDominatorTree;
30 class RegPressureTracker;
33 /// An individual mapping from virtual register number to SUnit.
39 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU)
40 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
42 unsigned getSparseSetIndex() const {
43 return TargetRegisterInfo::virtReg2Index(VirtReg);
47 /// Mapping from virtual register to SUnit including an operand index.
48 struct VReg2SUnitOperIdx : public VReg2SUnit {
49 unsigned OperandIndex;
51 VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask,
52 unsigned OperandIndex, SUnit *SU)
53 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {}
56 /// Record a physical register access.
57 /// For non-data-dependent uses, OpIdx == -1.
58 struct PhysRegSUOper {
63 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
65 unsigned getSparseSetIndex() const { return Reg; }
68 /// Use a SparseMultiSet to track physical registers. Storage is only
69 /// allocated once for the pass. It can be cleared in constant time and reused
70 /// without any frees.
71 typedef SparseMultiSet<PhysRegSUOper, llvm::identity<unsigned>, uint16_t>
74 /// Use SparseSet as a SparseMap by relying on the fact that it never
75 /// compares ValueT's, only unsigned keys. This allows the set to be cleared
76 /// between scheduling regions in constant time as long as ValueT does not
77 /// require a destructor.
78 typedef SparseSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2SUnitMap;
80 /// Track local uses of virtual registers. These uses are gathered by the DAG
81 /// builder and may be consulted by the scheduler to avoid iterating an entire
83 typedef SparseMultiSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2SUnitMultiMap;
85 typedef SparseMultiSet<VReg2SUnitOperIdx, VirtReg2IndexFunctor>
86 VReg2SUnitOperIdxMultiMap;
88 /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
90 class ScheduleDAGInstrs : public ScheduleDAG {
92 const MachineLoopInfo *MLI;
93 const MachineFrameInfo *MFI;
95 /// Live Intervals provides reaching defs in preRA scheduling.
98 /// TargetSchedModel provides an interface to the machine model.
99 TargetSchedModel SchedModel;
101 /// True if the DAG builder should remove kill flags (in preparation for
103 bool RemoveKillFlags;
105 /// The standard DAG builder does not normally include terminators as DAG
106 /// nodes because it does not create the necessary dependencies to prevent
107 /// reordering. A specialized scheduler can override
108 /// TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate
109 /// it has taken responsibility for scheduling the terminator correctly.
110 bool CanHandleTerminators;
112 /// Whether lane masks should get tracked.
115 /// State specific to the current scheduling region.
116 /// ------------------------------------------------
118 /// The block in which to insert instructions
119 MachineBasicBlock *BB;
121 /// The beginning of the range to be scheduled.
122 MachineBasicBlock::iterator RegionBegin;
124 /// The end of the range to be scheduled.
125 MachineBasicBlock::iterator RegionEnd;
127 /// Instructions in this region (distance(RegionBegin, RegionEnd)).
128 unsigned NumRegionInstrs;
130 /// After calling BuildSchedGraph, each machine instruction in the current
131 /// scheduling region is mapped to an SUnit.
132 DenseMap<MachineInstr*, SUnit*> MISUnitMap;
134 /// After calling BuildSchedGraph, each vreg used in the scheduling region
135 /// is mapped to a set of SUnits. These include all local vreg uses, not
136 /// just the uses for a singly defined vreg.
137 VReg2SUnitMultiMap VRegUses;
139 /// State internal to DAG building.
140 /// -------------------------------
142 /// Defs, Uses - Remember where defs and uses of each register are as we
143 /// iterate upward through the instructions. This is allocated here instead
144 /// of inside BuildSchedGraph to avoid the need for it to be initialized and
145 /// destructed for each block.
149 /// Tracks the last instruction(s) in this region defining each virtual
150 /// register. There may be multiple current definitions for a register with
151 /// disjunct lanemasks.
152 VReg2SUnitMultiMap CurrentVRegDefs;
153 /// Tracks the last instructions in this region using each virtual register.
154 VReg2SUnitOperIdxMultiMap CurrentVRegUses;
156 /// PendingLoads - Remember where unknown loads are after the most recent
157 /// unknown store, as we iterate. As with Defs and Uses, this is here
158 /// to minimize construction/destruction.
159 std::vector<SUnit *> PendingLoads;
161 /// DbgValues - Remember instruction that precedes DBG_VALUE.
162 /// These are generated by buildSchedGraph but persist so they can be
163 /// referenced when emitting the final schedule.
164 typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
166 DbgValueVector DbgValues;
167 MachineInstr *FirstDbgValue;
169 /// Set of live physical registers for updating kill flags.
173 explicit ScheduleDAGInstrs(MachineFunction &mf,
174 const MachineLoopInfo *mli,
175 LiveIntervals *LIS = nullptr,
176 bool RemoveKillFlags = false);
178 ~ScheduleDAGInstrs() override {}
180 /// \brief Expose LiveIntervals for use in DAG mutators and such.
181 LiveIntervals *getLIS() const { return LIS; }
183 /// \brief Get the machine model for instruction scheduling.
184 const TargetSchedModel *getSchedModel() const { return &SchedModel; }
186 /// \brief Resolve and cache a resolved scheduling class for an SUnit.
187 const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
188 if (!SU->SchedClass && SchedModel.hasInstrSchedModel())
189 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
190 return SU->SchedClass;
193 /// begin - Return an iterator to the top of the current scheduling region.
194 MachineBasicBlock::iterator begin() const { return RegionBegin; }
196 /// end - Return an iterator to the bottom of the current scheduling region.
197 MachineBasicBlock::iterator end() const { return RegionEnd; }
199 /// newSUnit - Creates a new SUnit and return a ptr to it.
200 SUnit *newSUnit(MachineInstr *MI);
202 /// getSUnit - Return an existing SUnit for this MI, or NULL.
203 SUnit *getSUnit(MachineInstr *MI) const;
205 /// startBlock - Prepare to perform scheduling in the given block.
206 virtual void startBlock(MachineBasicBlock *BB);
208 /// finishBlock - Clean up after scheduling in the given block.
209 virtual void finishBlock();
211 /// Initialize the scheduler state for the next scheduling region.
212 virtual void enterRegion(MachineBasicBlock *bb,
213 MachineBasicBlock::iterator begin,
214 MachineBasicBlock::iterator end,
215 unsigned regioninstrs);
217 /// Notify that the scheduler has finished scheduling the current region.
218 virtual void exitRegion();
220 /// buildSchedGraph - Build SUnits from the MachineBasicBlock that we are
222 void buildSchedGraph(AliasAnalysis *AA,
223 RegPressureTracker *RPTracker = nullptr,
224 PressureDiffs *PDiffs = nullptr,
225 bool TrackLaneMasks = false);
227 /// addSchedBarrierDeps - Add dependencies from instructions in the current
228 /// list of instructions being scheduled to scheduling barrier. We want to
229 /// make sure instructions which define registers that are either used by
230 /// the terminator or are live-out are properly scheduled. This is
231 /// especially important when the definition latency of the return value(s)
232 /// are too high to be hidden by the branch or when the liveout registers
233 /// used by instructions in the fallthrough block.
234 void addSchedBarrierDeps();
236 /// schedule - Order nodes according to selected style, filling
237 /// in the Sequence member.
239 /// Typically, a scheduling algorithm will implement schedule() without
240 /// overriding enterRegion() or exitRegion().
241 virtual void schedule() = 0;
243 /// finalizeSchedule - Allow targets to perform final scheduling actions at
244 /// the level of the whole MachineFunction. By default does nothing.
245 virtual void finalizeSchedule() {}
247 void dumpNode(const SUnit *SU) const override;
249 /// Return a label for a DAG node that points to an instruction.
250 std::string getGraphNodeLabel(const SUnit *SU) const override;
252 /// Return a label for the region of code covered by the DAG.
253 std::string getDAGName() const override;
255 /// \brief Fix register kill flags that scheduling has made invalid.
256 void fixupKills(MachineBasicBlock *MBB);
259 void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx);
260 void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
261 void addVRegDefDeps(SUnit *SU, unsigned OperIdx);
262 void addVRegUseDeps(SUnit *SU, unsigned OperIdx);
264 /// \brief PostRA helper for rewriting kill flags.
265 void startBlockForKills(MachineBasicBlock *BB);
267 /// \brief Toggle a register operand kill flag.
269 /// Other adjustments may be made to the instruction if necessary. Return
270 /// true if the operand has been deleted, false if not.
271 bool toggleKillFlag(MachineInstr *MI, MachineOperand &MO);
273 /// Returns a mask for which lanes get read/written by the given (register)
275 LaneBitmask getLaneMaskForMO(const MachineOperand &MO) const;
277 void collectVRegUses(SUnit *SU);
280 /// newSUnit - Creates a new SUnit and return a ptr to it.
281 inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) {
283 const SUnit *Addr = SUnits.empty() ? nullptr : &SUnits[0];
285 SUnits.emplace_back(MI, (unsigned)SUnits.size());
286 assert((Addr == nullptr || Addr == &SUnits[0]) &&
287 "SUnits std::vector reallocated on the fly!");
288 SUnits.back().OrigNode = &SUnits.back();
289 return &SUnits.back();
292 /// getSUnit - Return an existing SUnit for this MI, or NULL.
293 inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const {
294 DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI);
295 if (I == MISUnitMap.end())