1 //===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAG class, which is used as the common
11 // base class for SelectionDAG-based instruction scheduler.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULEDAG_H
16 #define LLVM_CODEGEN_SCHEDULEDAG_H
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/ADT/GraphTraits.h"
23 #include "llvm/ADT/SmallSet.h"
28 class MachineConstantPool;
29 class MachineFunction;
30 class MachineModuleInfo;
31 class MachineRegisterInfo;
33 class TargetRegisterInfo;
35 class SelectionDAGISel;
36 class TargetInstrInfo;
37 class TargetInstrDesc;
40 class TargetRegisterClass;
42 /// HazardRecognizer - This determines whether or not an instruction can be
43 /// issued this cycle, and whether or not a noop needs to be inserted to handle
45 class HazardRecognizer {
47 virtual ~HazardRecognizer();
50 NoHazard, // This instruction can be emitted at this cycle.
51 Hazard, // This instruction can't be emitted at this cycle.
52 NoopHazard // This instruction can't be emitted, and needs noops.
55 /// getHazardType - Return the hazard type of emitting this node. There are
56 /// three possible results. Either:
57 /// * NoHazard: it is legal to issue this instruction on this cycle.
58 /// * Hazard: issuing this instruction would stall the machine. If some
59 /// other instruction is available, issue it first.
60 /// * NoopHazard: issuing this instruction would break the program. If
61 /// some other instruction can be issued, do so, otherwise issue a noop.
62 virtual HazardType getHazardType(SDNode *Node) {
66 /// EmitInstruction - This callback is invoked when an instruction is
67 /// emitted, to advance the hazard state.
68 virtual void EmitInstruction(SDNode *Node) {
71 /// AdvanceCycle - This callback is invoked when no instructions can be
72 /// issued on this cycle without a hazard. This should increment the
73 /// internal state of the hazard recognizer so that previously "Hazard"
74 /// instructions will now not be hazards.
75 virtual void AdvanceCycle() {
78 /// EmitNoop - This callback is invoked when a noop was added to the
79 /// instruction stream.
80 virtual void EmitNoop() {
84 /// SDep - Scheduling dependency. It keeps track of dependent nodes,
85 /// cost of the depdenency, etc.
87 SUnit *Dep; // Dependent - either a predecessor or a successor.
88 unsigned Reg; // If non-zero, this dep is a phy register dependency.
89 int Cost; // Cost of the dependency.
90 bool isCtrl : 1; // True iff it's a control dependency.
91 bool isSpecial : 1; // True iff it's a special ctrl dep added during sched.
92 SDep(SUnit *d, unsigned r, int t, bool c, bool s)
93 : Dep(d), Reg(r), Cost(t), isCtrl(c), isSpecial(s) {}
96 /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
97 /// a group of nodes flagged together.
99 SDNode *Node; // Representative node.
100 SmallVector<SDNode*,4> FlaggedNodes;// All nodes flagged to Node.
101 unsigned InstanceNo; // Instance#. One SDNode can be multiple
102 // SUnit due to cloning.
104 // Preds/Succs - The SUnits before/after us in the graph. The boolean value
105 // is true if the edge is a token chain edge, false if it is a value edge.
106 SmallVector<SDep, 4> Preds; // All sunit predecessors.
107 SmallVector<SDep, 4> Succs; // All sunit successors.
109 typedef SmallVector<SDep, 4>::iterator pred_iterator;
110 typedef SmallVector<SDep, 4>::iterator succ_iterator;
111 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
112 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;
114 unsigned NodeNum; // Entry # of node in the node vector.
115 unsigned short Latency; // Node latency.
116 short NumPreds; // # of preds.
117 short NumSuccs; // # of sucss.
118 short NumPredsLeft; // # of preds not scheduled.
119 short NumSuccsLeft; // # of succs not scheduled.
120 bool isTwoAddress : 1; // Is a two-address instruction.
121 bool isCommutable : 1; // Is a commutable instruction.
122 bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
123 bool isPending : 1; // True once pending.
124 bool isAvailable : 1; // True once available.
125 bool isScheduled : 1; // True once scheduled.
126 unsigned CycleBound; // Upper/lower cycle to be scheduled at.
127 unsigned Cycle; // Once scheduled, the cycle of the op.
128 unsigned Depth; // Node depth;
129 unsigned Height; // Node height;
130 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
131 const TargetRegisterClass *CopySrcRC;
133 SUnit(SDNode *node, unsigned nodenum)
134 : Node(node), InstanceNo(0), NodeNum(nodenum), Latency(0),
135 NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
136 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
137 isPending(false), isAvailable(false), isScheduled(false),
138 CycleBound(0), Cycle(0), Depth(0), Height(0),
139 CopyDstRC(NULL), CopySrcRC(NULL) {}
141 /// addPred - This adds the specified node as a pred of the current node if
142 /// not already. This returns true if this is a new pred.
143 bool addPred(SUnit *N, bool isCtrl, bool isSpecial,
144 unsigned PhyReg = 0, int Cost = 1) {
145 for (unsigned i = 0, e = Preds.size(); i != e; ++i)
146 if (Preds[i].Dep == N &&
147 Preds[i].isCtrl == isCtrl && Preds[i].isSpecial == isSpecial)
149 Preds.push_back(SDep(N, PhyReg, Cost, isCtrl, isSpecial));
150 N->Succs.push_back(SDep(this, PhyReg, Cost, isCtrl, isSpecial));
162 bool removePred(SUnit *N, bool isCtrl, bool isSpecial) {
163 for (SmallVector<SDep, 4>::iterator I = Preds.begin(), E = Preds.end();
165 if (I->Dep == N && I->isCtrl == isCtrl && I->isSpecial == isSpecial) {
166 bool FoundSucc = false;
167 for (SmallVector<SDep, 4>::iterator II = N->Succs.begin(),
168 EE = N->Succs.end(); II != EE; ++II)
169 if (II->Dep == this &&
170 II->isCtrl == isCtrl && II->isSpecial == isSpecial) {
175 assert(FoundSucc && "Mismatching preds / succs lists!");
190 bool isPred(SUnit *N) {
191 for (unsigned i = 0, e = Preds.size(); i != e; ++i)
192 if (Preds[i].Dep == N)
197 bool isSucc(SUnit *N) {
198 for (unsigned i = 0, e = Succs.size(); i != e; ++i)
199 if (Succs[i].Dep == N)
204 void dump(const SelectionDAG *G) const;
205 void dumpAll(const SelectionDAG *G) const;
208 //===--------------------------------------------------------------------===//
209 /// SchedulingPriorityQueue - This interface is used to plug different
210 /// priorities computation algorithms into the list scheduler. It implements
211 /// the interface of a standard priority queue, where nodes are inserted in
212 /// arbitrary order and returned in priority order. The computation of the
213 /// priority and the representation of the queue are totally up to the
214 /// implementation to decide.
216 class SchedulingPriorityQueue {
218 virtual ~SchedulingPriorityQueue() {}
220 virtual void initNodes(DenseMap<SDNode*, std::vector<SUnit*> > &SUMap,
221 std::vector<SUnit> &SUnits) = 0;
222 virtual void addNode(const SUnit *SU) = 0;
223 virtual void updateNode(const SUnit *SU) = 0;
224 virtual void releaseState() = 0;
226 virtual unsigned size() const = 0;
227 virtual bool empty() const = 0;
228 virtual void push(SUnit *U) = 0;
230 virtual void push_all(const std::vector<SUnit *> &Nodes) = 0;
231 virtual SUnit *pop() = 0;
233 virtual void remove(SUnit *SU) = 0;
235 /// ScheduledNode - As each node is scheduled, this method is invoked. This
236 /// allows the priority function to adjust the priority of node that have
237 /// already been emitted.
238 virtual void ScheduledNode(SUnit *Node) {}
240 virtual void UnscheduledNode(SUnit *Node) {}
245 SelectionDAG &DAG; // DAG of the current basic block
246 MachineBasicBlock *BB; // Current basic block
247 const TargetMachine &TM; // Target processor
248 const TargetInstrInfo *TII; // Target instruction information
249 const TargetRegisterInfo *TRI; // Target processor register info
250 TargetLowering *TLI; // Target lowering info
251 MachineFunction *MF; // Machine function
252 MachineRegisterInfo &MRI; // Virtual/real register map
253 MachineConstantPool *ConstPool; // Target constant pool
254 std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s
255 // represent noop instructions.
256 DenseMap<SDNode*, std::vector<SUnit*> > SUnitMap;
257 // SDNode to SUnit mapping (n -> n).
258 std::vector<SUnit> SUnits; // The scheduling units.
259 SmallSet<SDNode*, 16> CommuteSet; // Nodes that should be commuted.
261 ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
262 const TargetMachine &tm);
264 virtual ~ScheduleDAG() {}
266 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
271 /// Run - perform scheduling.
273 MachineBasicBlock *Run();
275 /// isPassiveNode - Return true if the node is a non-scheduled leaf.
277 static bool isPassiveNode(SDNode *Node) {
278 if (isa<ConstantSDNode>(Node)) return true;
279 if (isa<ConstantFPSDNode>(Node)) return true;
280 if (isa<RegisterSDNode>(Node)) return true;
281 if (isa<GlobalAddressSDNode>(Node)) return true;
282 if (isa<BasicBlockSDNode>(Node)) return true;
283 if (isa<FrameIndexSDNode>(Node)) return true;
284 if (isa<ConstantPoolSDNode>(Node)) return true;
285 if (isa<JumpTableSDNode>(Node)) return true;
286 if (isa<ExternalSymbolSDNode>(Node)) return true;
287 if (isa<MemOperandSDNode>(Node)) return true;
288 if (Node->getOpcode() == ISD::EntryToken) return true;
292 /// NewSUnit - Creates a new SUnit and return a ptr to it.
294 SUnit *NewSUnit(SDNode *N) {
295 SUnits.push_back(SUnit(N, SUnits.size()));
296 return &SUnits.back();
299 /// Clone - Creates a clone of the specified SUnit. It does not copy the
300 /// predecessors / successors info nor the temporary scheduling states.
301 SUnit *Clone(SUnit *N);
303 /// BuildSchedUnits - Build SUnits from the selection dag that we are input.
304 /// This SUnit graph is similar to the SelectionDAG, but represents flagged
305 /// together nodes with a single SUnit.
306 void BuildSchedUnits();
308 /// ComputeLatency - Compute node latency.
310 void ComputeLatency(SUnit *SU);
312 /// CalculateDepths, CalculateHeights - Calculate node depth / height.
314 void CalculateDepths();
315 void CalculateHeights();
317 /// CountResults - The results of target nodes have register or immediate
318 /// operands first, then an optional chain, and optional flag operands
319 /// (which do not go into the machine instrs.)
320 static unsigned CountResults(SDNode *Node);
322 /// CountOperands - The inputs to target nodes have any actual inputs first,
323 /// followed by special operands that describe memory references, then an
324 /// optional chain operand, then flag operands. Compute the number of
325 /// actual operands that will go into the resulting MachineInstr.
326 static unsigned CountOperands(SDNode *Node);
328 /// ComputeMemOperandsEnd - Find the index one past the last
329 /// MemOperandSDNode operand
330 static unsigned ComputeMemOperandsEnd(SDNode *Node);
332 /// EmitNode - Generate machine code for an node and needed dependencies.
333 /// VRBaseMap contains, for each already emitted node, the first virtual
334 /// register number for the results of the node.
336 void EmitNode(SDNode *Node, unsigned InstNo,
337 DenseMap<SDOperandImpl, unsigned> &VRBaseMap);
339 /// EmitNoop - Emit a noop instruction.
345 void dumpSchedule() const;
347 /// Schedule - Order nodes according to selected style.
349 virtual void Schedule() {}
352 /// EmitSubregNode - Generate machine code for subreg nodes.
354 void EmitSubregNode(SDNode *Node,
355 DenseMap<SDOperandImpl, unsigned> &VRBaseMap);
357 /// getVR - Return the virtual register corresponding to the specified result
358 /// of the specified node.
359 unsigned getVR(SDOperand Op, DenseMap<SDOperandImpl, unsigned> &VRBaseMap);
361 /// getDstOfCopyToRegUse - If the only use of the specified result number of
362 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
363 unsigned getDstOfOnlyCopyToRegUse(SDNode *Node, unsigned ResNo) const;
365 void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
366 const TargetInstrDesc *II,
367 DenseMap<SDOperandImpl, unsigned> &VRBaseMap);
369 void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO);
371 void EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap);
373 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
374 /// implicit physical register output.
375 void EmitCopyFromReg(SDNode *Node, unsigned ResNo, unsigned InstNo,
377 DenseMap<SDOperandImpl, unsigned> &VRBaseMap);
379 void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
380 const TargetInstrDesc &II,
381 DenseMap<SDOperandImpl, unsigned> &VRBaseMap);
383 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
384 /// physical register has only a single copy use, then coalesced the copy
386 void EmitLiveInCopy(MachineBasicBlock *MBB,
387 MachineBasicBlock::iterator &InsertPos,
388 unsigned VirtReg, unsigned PhysReg,
389 const TargetRegisterClass *RC,
390 DenseMap<MachineInstr*, unsigned> &CopyRegMap);
392 /// EmitLiveInCopies - If this is the first basic block in the function,
393 /// and if it has live ins that need to be copied into vregs, emit the
394 /// copies into the top of the block.
395 void EmitLiveInCopies(MachineBasicBlock *MBB);
398 /// createBURRListDAGScheduler - This creates a bottom up register usage
399 /// reduction list scheduler.
400 ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
402 MachineBasicBlock *BB);
404 /// createTDRRListDAGScheduler - This creates a top down register usage
405 /// reduction list scheduler.
406 ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
408 MachineBasicBlock *BB);
410 /// createTDListDAGScheduler - This creates a top-down list scheduler with
411 /// a hazard recognizer.
412 ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
414 MachineBasicBlock *BB);
416 /// createDefaultScheduler - This creates an instruction scheduler appropriate
418 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
420 MachineBasicBlock *BB);
422 class SUnitIterator : public forward_iterator<SUnit, ptrdiff_t> {
426 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
428 bool operator==(const SUnitIterator& x) const {
429 return Operand == x.Operand;
431 bool operator!=(const SUnitIterator& x) const { return !operator==(x); }
433 const SUnitIterator &operator=(const SUnitIterator &I) {
434 assert(I.Node == Node && "Cannot assign iterators to two different nodes!");
439 pointer operator*() const {
440 return Node->Preds[Operand].Dep;
442 pointer operator->() const { return operator*(); }
444 SUnitIterator& operator++() { // Preincrement
448 SUnitIterator operator++(int) { // Postincrement
449 SUnitIterator tmp = *this; ++*this; return tmp;
452 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
453 static SUnitIterator end (SUnit *N) {
454 return SUnitIterator(N, N->Preds.size());
457 unsigned getOperand() const { return Operand; }
458 const SUnit *getNode() const { return Node; }
459 bool isCtrlDep() const { return Node->Preds[Operand].isCtrl; }
460 bool isSpecialDep() const { return Node->Preds[Operand].isSpecial; }
463 template <> struct GraphTraits<SUnit*> {
464 typedef SUnit NodeType;
465 typedef SUnitIterator ChildIteratorType;
466 static inline NodeType *getEntryNode(SUnit *N) { return N; }
467 static inline ChildIteratorType child_begin(NodeType *N) {
468 return SUnitIterator::begin(N);
470 static inline ChildIteratorType child_end(NodeType *N) {
471 return SUnitIterator::end(N);
475 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> {
476 typedef std::vector<SUnit>::iterator nodes_iterator;
477 static nodes_iterator nodes_begin(ScheduleDAG *G) {
478 return G->SUnits.begin();
480 static nodes_iterator nodes_end(ScheduleDAG *G) {
481 return G->SUnits.end();